CD4047

CD4047BC Low Power Monostable/Astable Multivibrator October 1987 Revised May 1999 CD4047BC Low Power Monostable/Astable Multivibrator General Description The CD4047B is capable of operating in either the monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor (between pins 2 and 3) to determine the output pulse width in the monostable mode, and the output frequency in the astable mode. Astable operation is enabled by a high level on the astable input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of Q is available at the Oscillator Output; a 50% duty cycle is not guaranteed. Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or HIGH-to-LOW transition at − trigger input. The device can be retriggered by applying a simultaneous LOW-to-HIGH transition to both the + trigger and retrigger inputs. A high level on Reset input resets the outputs Q to LOW, Q to HIGH. s True and complemented buffered outputs s Only one external R and C required MONOSTABLE MULTIVIBRATOR FEATURES s Positive- or negative-edge trigger s Output pulse width independent of trigger pulse duration s Retriggerable option for pulse width expansion s Long pulse widths possible using small RC components by means of external counter provision s Fast recovery time essentially independent of pulse width s Pulse-width accuracy approaching 100% maintained at duty cycles ASTABLE MULTIVIBRATOR FEATURES s Free-running or gatable operating modes s 50% duty cycle s Oscillator output available s Good astable frequency stability typical= ±2% + 0.03%/°C @ 100 kHz Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS SPECIAL FEATURES s Low power consumption: special CMOS oscillator configuration s Monostable (one-shot) or astable (free-running) operation frequency= ±0.5% + 0.015%/°C @ 10 kHz deviation (circuits trimmed to frequency VDD = 10V ±10%) Applications • Frequency discriminators • Timing circuits • Time-delay applications • Envelope detection • Frequency multiplication • Frequency division Ordering Code: Order Number CD4047BCM CD4047BCN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS005969.prf www.fairchildsemi.com CD4047BC Connection Diagram Pin Assignments for SOIC and DIP Top View Function Table Terminal Connections Function Astable Multivibrator Free-Running True Gating Complement Gating Monostable Multivibrator Positive-Edge Trigger Negative-Edge Trigger Retriggerable 4, 14 4, 8, 14 4, 14 5, 6, 7, 9, 12 5, 7, 9, 12 5, 6, 7, 9 5, 6, 7, 8, 9, 12 8 6 8, 12 Figure 1 10, 11 10, 11 10, 11 Figure 1 Figure 1 tM (10, 11) = 2.48 RC 4, 5, 6, 14 4, 6, 14 6, 14 7, 8, 9, 12 7, 8, 9, 12 5, 7, 8, 9, 12 5 4 10, 11, 13 10, 11, 13 10, 11, 13 tA(10, 11) = 4.40 RC tA (13) = 2.20 RC To VDD To VSS Input Pulse To Output Pulse From Typical Output Period or Pulse Width External Countdown (Note 1) 14 Note 1: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3. Typical Implementation of External Countdown Option tEXT = (N − 1) tA + (tM + tA/2) FIGURE 1. www.fairchildsemi.com 2 CD4047BC Block Diagram Logic Diagram *Special input protection circuit to permit larger input-voltage swings. 3 www.fairchildsemi.com CD4047BC Absolute Maximum Ratings(Note 2) (Note 3) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260°C 700 mW 500 mW −0.5V to +18VDC −0.5V to VDD +0.5VDC −65°C to +150°C Recommended Operating Conditions (Note 3) DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15VDC 0 to VDD VDC −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Note 3: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol IDD Parameter Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage |IO| < 1 µA VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1 µA VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VIH HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V IOL LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V Note 4: IOH and IOL are tested one output at a time. Conditions −40°C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 −0.52 −1.3 −3.6 −0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 −0.44 −1.1 −3.0 4.95 9.95 14.95 Min 25°C Typ Max 20 40 80 0 0 0 5 10 15 2.25 4.5 6.75 2.75 5.5 8.25 0.88 2.25 8.8 −0.88 −2.25 −8.8 −10−5 10−5 −0.3 0.3 1.5 3.0 4.0 3.5 7.0 0.05 0.05 0.05 85°C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 Units µA µA µA V V V V V V V V V V V V mA mA mA mA mA mA 11.0 0.36 0.9 2.4 −0.36 −0.9 −2.4 −1.0 1.0 µA µA www.fairchildsemi.com 4 CD4047BC AC Electrical Characteristics Symbol tPHL, tPLH Parameter Propagation Delay Time Astable, Astable to Osc Out tPHL, tPLH (Note 5) Conditions Min Typ 200 100 80 550 250 200 700 300 240 300 175 150 300 125 100 100 50 40 500 200 160 Max 400 200 160 900 500 400 1200 600 480 600 300 250 600 250 200 200 100 80 1000 400 320 15 5 5 5 7.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs pF TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified. VDD = 5V VDD = 10V VDD = 15V Astable, Astable to Q, Q VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH + Trigger, − Trigger to Q VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH + Trigger, Retrigger to Q VDD = 5V VDD = 10V VDD = 15V tPHL, tPLH Reset to Q, Q VDD = 5V VDD = 10V VDD = 15V tTHL, tTLH Transition Time Q, Q, Osc Out VDD = 5V VDD = 10V VDD = 15V tWL, tWH Minimum Input Pulse Duration Any Input VDD = 5V VDD = 10V VDD = 15V tRCL, tFCL + Trigger, Retrigger, Rise and Fall Time CIN Average Input Capacitance VDD = 5V VDD = 10V VDD = 15V Any Input Note 5: AC Parameters are guaranteed by DC correlated testing. 5 www.fairchildsemi.com CD4047BC Typical Performance Characteristics Typical Q, Q, Osc Out Period Accuracy vs Supply Voltage (Astable Mode Operation) Typical Q, Q, Pulse Width Accuracy vs Supply Voltage Monostable Mode Operation f Q, Q A B C D E 1000 kHz 100 kHz 10 kHz 1 kHz 100 Hz 22k 22k R C 10 pF 100 pF 100 pF 1000 pF 1000 pF A B C D E 2 µs 7 µs tM 22k 22k R C 10 pF 100 pF 100 pF 1000 pF 1000 pF 220k 220k 2.2M 60 µs 550 µs 5.5 ms 220k 220k 2.2M Typical Q, Q and Osc Out Period Accuracy vs Temperature Astable Mode Operation Typical Q and Q Pulse Width Accuracy vs Temperature Monostable Mode Operation f Q, Q A B C D 1000 kHz 100 kHz 10 kHz 1 kHz 22k 22k R C 10 pF 100 pF 100 pF 1000 pF A B C D 2 µs 7 µs tM 22k 22k R C 10 pF 100 pF 100 pF 1000 pF 220k 220k 60 µs 550 µs 220k 220k www.fairchildsemi.com 6 CD4047BC Timing Diagrams Astable Mode Monostable Mode Retrigger Mode 7 www.fairchildsemi.com CD4047BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A www.fairchildsemi.com 8 CD4047BC Low Power Monostable/Astable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.