CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
November 1983 Revised April 2002
CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description
The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration.
Features
s Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15Vp-p s Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p signal-input range for VDD − VEE = 15V s High “OFF” resistance: channel leakage of ±10 pA (typ.) at VDD − VEE = 10V s Logic level conversion for digital addressing signals of 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals to 15 Vp-p (VDD − VEE = 15V) s Matched switch characteristics: ∆RON = 5Ω (typ.) for VDD − VEE = 15V s Very low quiescent power dissipation under all digital-control input and supply conditions: 1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V s Binary address decoding on chip
Ordering Code:
Order Number CD4051BCM CD4051BCSJ CD4051BCMTC CD4051BCN CD4052BCM CD4052BCSJ CD4052BCN CD4053BCM CD4053BCSJ CD4053BCN Package Number M16A M16D MTC16 N16E M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS005662
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CD4051BC • CD4052BC • CD4053BC
Connection Diagrams
Pin Assignments for DIP and SOIC CD4051BC CD4052BC
CD4053BC
Truth Table
INPUT STATES INHIBIT 0 0 0 0 0 0 0 0 1
*Don’t Care condition.
“ON” CHANNELS A 0 1 0 1 0 1 0 1 * CD4051B 0 1 2 3 4 5 6 7 NONE NONE CD4052B 0X, 0Y 1X, 1Y 2X, 2Y 3X, 3Y CD4053B cx, bx, ax cx, bx, ay cx, by, ax cx, by, ay cy, bx, ax cy, bx, ay cy, by, ax cy, by, ay NONE
C 0 0 0 0 1 1 1 1 *
B 0 0 1 1 0 0 1 1 *
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Logic Diagrams
CD4051BC
CD4052BC
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CD4051BC • CD4052BC • CD4053BC
Logic Diagrams
(Continued) CD4053BC
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CD4051BC • CD4052BC • CD4053BC
Absolute Maximum Ratings(Note 1)
DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (soldering, 10 seconds) 260°C (Note 2) 700 mW 500 mW
−0.5 VDC to +18 VDC −0.5 VDC to VDD +0.5 VDC −65°C to +150°C
Recommended Operating Conditions
DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4051BC/CD4052BC/CD4053BC
+5 VDC to +15 VDC
0V to VDD VDC
−55°C to +125°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation.
DC Electrical Characteristics
Symbol Parameter Control A, B, C and Inhibit IIN Input Current VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V IDD Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V Signal Inputs (VIS) and Outputs (VOS) RON “ON” Resistance (Peak for VEE ≤ VIS ≤ VDD) RL = 10 kΩ (any channel selected)
Conditions
−55°C Min Max Min
+25° Typ Max −0.1
125°C Min Max
Units
VEE = 0V VEE = 0V
−0.1 0.1 5 10 20
−10−5 10−5
−1.0 µA 1.0 150 300 600 µA
0.1 5 10 20
VDD = 2.5V, VEE = −2.5V or VDD = 5V, VEE = 0V VDD = 5V, VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V 200 80 240 320 Ω 310 120 400 550 Ω 800 270 1050 1300 Ω
∆RON
∆ “ON” Resistance Between Any Two Channels
RL = 10 kΩ (any channel selected)
VDD = 2.5V, VEE = −2.5V or VDD = 5V, VEE = 0V VDD = 5V VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V 5 Ω 10 Ω 10 Ω
“OFF” Channel Leakage “OFF” Channel Leakage Current, all channels “OFF” (Common OUT/IN)
VDD=7.5V, Inhibit = 7.5V VDD = 7.5V, VEE = −7.5V, O/I = 0V I/O = ±7.5V
VEE=−7.5V ±50 ±200 ±200 ±200 ±0.01 ±0.08 ±0.04 ±0.02 ±50 ±200 ±200 ±200 ±500 ±2000 ±2000 ±2000 nA nA CD4051 D4052 CD4053
Current, any channel “OFF” O/I=±7.5V, I/O=0V
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CD4051BC • CD4052BC • CD4053BC
DC Electrical Characteristics
Symbol Parameter
(Continued)
−55°C Min Max Min +25° Typ Max 125°C Min Max
Conditions
Units
Control Inputs A, B, C and Inhibit VIL LOW Level Input Voltage VEE = VSS RL = 1 kΩ to VSS IIS 25°C (calculated from RON values shown). No VDD current will flow through RL if the switch current flows into OUT/IN pin.
Typical Performance Characteristics
“ON” Resistance vs Signal Voltage for TA = 25°C “ON” Resistance as a Function of Temperature for VDD− VEE = 10V
“ON” Resistance as a Function of Temperature for VDD− VEE = 15V
“ON” Resistance as a Function of Temperature for VDD − VEE = 5V
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CD4051BC • CD4052BC • CD4053BC
Switching Time Waveforms
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CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 13 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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