CGS3311

CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal Clock Generators September 1995 Revised March 1999 CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal Clock Generators General Description The CGS3311, CGS3312, CGS3313, CGS3314, CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319 devices are designed for Clock Generation and Support (CGS) applications up to 110 MHz. The CGS331x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 331x devices provide selectable output divide ratio (and selectable crystal drive level). The circuit is designed to operate over a wide frequency range using fundamental model or overtone crystals. Features s Fairchild’s CGS family of devices for high frequency clock source applications s Crystal frequency operation range: fundamental: 10 MHz to 100 MHz typical 3rd or 5th overtone: 10 MHz to 85 MHz s Programmable oscillator drive s Selectable fast output edge rates s Output symmetry circuit to adjust 50% duty cycle point between CMOS and TTL levels s Output current drive of 48 mA for IOL/IOH s FACT™ CMOS output levels s Output has high speed short circuit protection s Basic oscillator type: Pierce s Hysteresis inputs to improve noise margin Ordering Code: Order Number CGS3311M CGS3312M CGS3313M CGS3314M CGS3315M CGS3316M CGS3317M CGS3318M CGS3319M Package Number Package Description M08A M08A M08A M08A M08A M08A M08A M08A M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS010980.prf www.fairchildsemi.com CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Connection Diagrams (A) 3311 (E) 3315 (B)3312 (F) 3316 (C) 3313 (G) 3317 (D) 3314 (H) 3318 (I) 3319 www.fairchildsemi.com 2 CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Truth Tables Division Selection DIVB DIVA OEL F 1 0 F 1 0 X X 0/F 0/F 0/F 1 1 1 X X X 0 0 0 0 0 1 X OEH Divider Output X 1 1 1 1 1 X 0 Divide-by 1 Divide-by 2 Divide-by 4 Divide-by 8 Divide-by 16 Divide-by 32 Output Reset HIGH at Re-enable Output Reset HIGH at Re-enable OSC_DR 0 1 F Rise and Fall Time Selection OSC_DR DIV TRF Rise/Fall Time (ns) F F F F 0,1 0,1 N N Y Y X X 0/F 1 0/F 1 0/F 1 2 less than 2 4 2 4 2 Drive Selection Drive Low Medium High Note: Actual value of the floating OSC_DR and DIVB input is VCC/2 Note: Where “F” indicates floating the input. Pin Descriptions Note: Pin out varies for each device. OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here. OEL Active LOW 3-STATE enable pin. This pin pulls to a low value when left floating and 3-STATE the output when forced HIGH. This pin has TTL compatible input levels. Rise and Fall time override pin. Available only for die form. This pin is the main clock output on the device. The Oscillator LOW pin is the ground for the Oscillator. This pin is the same signal as OSCLO_1. It has been provided as an alternate connection for OSCLO_1 for hybrid assemblies. The power pin for the chip. The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry. OSC_OUT Resistive Buffered Output of the Oscillator Inverter OSC_DR DIVA OEH 3 Level input pin that selects Oscillator Drive Level Input used to select Binary Divide-by Option. This pin has CMOS compatible input levels. TRF OUT OSCLO_1 Active HIGH 3-STATE enable pin. This pin pulls OSCLO_2 to a high value when left floating and 3-STATEs the output when forced low. This pin has TTL compatible input levels. VCC GND Functional Table Summary of Device Options Device 3311 3312 3313 3314 3315 3316 3317 3318 3319 Divide 1, 2, 4 1, 2, 4 8, 16, 32 8, 16, 32 1, 2, 4 4 32 1, 2, 4 1, 2, 4 Enable OEH OEH OEH OEH OEL OEH OEH OEH OEL Drive L, M, H H H L, M, H H H H H L, M, H Output Rise/ Fall Time (ns) 2, 4 2, 4 4 4 1, 2 4 4 1, 2 2, 4 Each drive has one output with the choices of selecting frequency divide, output enable, crystal drive and output rise and fall time. Crystal drive options are: L = LOW Drive M = MEDIUM Drive H = HIGH Drive 3 www.fairchildsemi.com CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Block Diagrams Note: Pin numbers vary for each device Oscillator Stage Output Stage www.fairchildsemi.com 4 CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) DC Input Voltage Diode Current (IIK) DC Input Voltage (VI) DC Output Diode Current (IOK) DC Output Voltage (VO) DC Output Source or Sink Current (IO) Storage Temperature (TSTG) Junction Temperature (TJ) SOIC 140°C/W ±70 mA −55°C to 150°C −0.5V to 7.0V ±9 mA −0.5V to 7.0V ±20 mA -0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 4.5V to 5.5V 0V to 5.5V 0V to VCC V −40° to +85°C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. DC Electrical Characteristics TA = +25°C VCC Symbol VIHTTL Parameter Minimum HIGH Level Input Voltage, TTL Level Inputs (OEH, OEL) Maximum LOW Level Input Voltage, TTL Level Inputs (OEH, OEL) Minimum HIGH Level Input Voltage. CMOS Level Inputs (DIVA) Maximum LOW Level Input voltage. CMOS Level Inputs (DIVA) Minimum Logic 1 Input for Three Level Input (DIVB, OSC_DR) Minimum Logic 1/2 Input for Three Level Input (DIVB, OSC_DR) Maximum Logic 0 Input Level Three Level Input (DIVB, OSC_DR) Minimum HIGH Level Output Voltage (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Minimum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIHRES Input Current for Pins DIVB, OSC_DR, and DIVA (Input is Logic HIGH) Input Current for Pins DIVB, OSC_DR, and DIVA (Input is Logic LOW) Input Current for Enable Pin OEL Input Current for Enable Pin OEH Input Current for OSC_IN Pin (Indicates Bias Resistance) Input Current for OSC_IN Pin (Indicates Bias Resistance) Output Disabled Current (Output HIGH) 5.5 220 0.001 0.001 4.49 5.49 4.40 5.40 3.86 4.86 0.1 0.1 0.44 0.44 360 200 3.15 3.85 1.35 1.65 4.05 4.95 1.8 2.2 2.7 3.3 0.45 0.45 4.40 5.40 3.76 4.76 0.1 0.1 0.44 0.44 380 µA IOL = +48mA VIN = VIL or VIH VIN = 5.5V V IOH = −48 mA VIN = VIH or VIH IOUT = 50µA Typ Guaranteed Limits Min 2.0 2.0 0.8 0.8 3.15 3.85 1.35 1.65 4.05 4.95 1.8 2.2 2.7 3.3 0.45 0.45 V IOUT = −50µA V V V V Max Min 2.0 2.0 0.8 0.8 V V Max Units Conditions V TA = −40° C to +85°C VILTTL VIHCMOS VILCMOS VIN3L_H VIN3L_1/2 VIN3L_L VOH IILRES 5.5 −220 −360 −200 −380 µA VIN = 0.0V IIHENAB IILENAB IIHOSC IILOSC IOZH 5.5 5.5 5.5 5.5 4.5 5.5 90 −90 20 −20 160 −160 100 −100 3.0 3.0 85 −85 20 −20 175 −175 125 −125 5.0 5.0 µA µA µA µA µA VIN = 5.5V VIN = 0.0V VIN = 5.5V VIN = 0.0V VOUT = VCC 5 www.fairchildsemi.com CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 DC Electrical Characteristics VCC Symbol IOZL IOLD IOHD ICCOSC_L ICCOSC_M ICCOSC_H ICCT Parameter Output Disabled Current (Output LOW) Minimum Dynamic Output Current Minimum Dynamic Output Current Additional ICC with OSC_IN Floating. LOW Drive Mode Additional ICC with OSC_IN Floating. LOW Drive Mode Additional ICC with OSC_IN Floating. LOW Drive Mode Additional Maximum ICC per Input (OEH, OEL Pins) Additional Maximum ICC per Input (DIVB, OSC_DR Inputs) (V) 4.5 5.5 5.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 Typ (Continued) TA = −40° C to +85°C Guaranteed Limits Min Max −140 −170 75 −75 0.6 6.5 1.7 12.4 5.5 31.5 1.5 5.5 31.5 1.5 mA VIN = VCC − 2.1V 1.7 12.4 mA OSC_IN = Float 75 −75 0.6 6.5 mA OSC_IN = Float Min Max −150 −180 mA mA mA VOLD = 1.65v VOHD = 3.85V OSC_IN = Float Units Conditions µA VOUT = 0.0V TA = +25°C ICC3L 5.5 1.5 1.5 mA DIVB, OSC_DR Inputs Equal to VCC/2 AC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. VCC (V) Symbol fMAX tPZH tPZL tPHZ tPLZ tRISE tFALL Parameter Frequency Maximum Output HIGH Enable Time Output LOW Enable Time Output HIGH Disable Time Output LOW Disable Time Rise/Fall Time 30 pF (20% to 80%) (Note 2) 5.0 5.0 5.0 5.0 5.0 5.0 TA = −40°C to + 85°C CL = 50 pF Min 100 1.0 1.0 1.0 1.0 4.0 31.5 28.0 21.5 16.0 Type Max Units ns ns ns ns ns ns Note 2: Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 6 CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal Clock Generators Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M08A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.