CGS3322M

CGS3321 • CGS3322 CMOS Crystal Clock Generators September 1195 Revised January 2001 CGS3321 • CGS3322 CMOS Crystal Clock Generators General Description The CGS3321 and CGS3322 devices are designed for Clock Generation and Support (CGS) applications up to 110 MHz. The CGS332x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 332x devices provide selectable output divide ratio. The circuit is designed to operate over a wide frequency range using fundamental mode or overtone crystals. Features s Fairchild’s CGS family of devices for high frequency clock source applications s Crystal frequency operation range: fundamental: 10 MHz to 100 MHz typical 3rd or 5th overtone: 10 MHz to 95 MHz s 1000V ESD protection on OCS_IN and OSC_OUT pins. 2000V ESD protection on all other pins s Output current drive of 48 mA for IOL/IOH s FACT CMOS output levels s Output has high speed short circuit protection s Intended for Pierce oscillator applications s Hysteresis inputs to improve noise margin s CGS3321 has duty cycle adjust s CGS3322 has 1, 2, 4 divide ratio Ordering Code: Order Number CGS3321M CGS3322M Package Number M08A M08A Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CGS3321 Truth Table Division Selection DIVB F 1 0 OEH X 1 1 Divider Output Divide-by 1 Divide-by 2 Divide-by 4 Note: Actual value of the floating DIVB input is VCC/2 CGS3322 FACT is a trademark of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation DS011503 www.fairchildsemi.com CGS3321 • CGS3322 Pin Descriptions Note: Pin out varies for each device. OSC_IN Input to Oscillator Inverter. The output of the crystal would be connected here. OEH Active HIGH 3-STATE enable pin. This pin pulls to a HIGH value when left floating and 3STATEs the output when forced LOW. This pin has TTL compatible input levels. This pin is the main clock output on the device. The Oscillator LOW pin is the ground for the Oscillator. The power pin for the chip. The ground pin for all sections of the circuitry except the oscillator and oscillator related circuitry. OSC_OUT Resistive Buffered Output of the Oscillator Inverter DIVB (CGS3322 only) 3-Level input used to select Binary Divide-by value of output frequency. (CGS3321 only) Active high input that controls output duty cycle. Logic high level will delay the HL transition edge approximately 0.3 ns. OUT OSCLO_1 DC_ADJ VCC GND Note: Pin out varies for each device. Block Diagrams Note: Pin numbers vary for each device www.fairchildsemi.com 2 CGS3321 • CGS3322 Block Diagrams (Continued) Oscillator Stage Output Stage 3 www.fairchildsemi.com CGS3321 • CGS3322 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) DC Input Voltage (VI) DC Output Diode Current (IOK) DC Output Voltage (VO) DC Output Source or Sink Current (IO) Storage Temperature (TSTG) Junction Temperature (TJ) SOIC 140 °C/W −0.5V to 7.0V ±9 mA −0.5V to 7.0V ±20 mA -0.5V to VCC + 0.5V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 4.5V to 5.5V 0V to 5.5V 0V to VCC V −40° to +85°C ±70 mA −55°C to 150°C Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. DC Electrical Characteristics TA = +25°C Symbol Parameter VCC (V) VIHTTL Minimum HIGH Level Input Voltage, TTL Level Inputs (OEH, OEL) Maximum LOW Level Input Voltage, TTL Level Inputs (OEH, OEL) Minimum HIGH Level Input Voltage. CMOS Level Inputs (DC_ADJ) Maximum LOW Level Input voltage. CMOS Level Inputs (DC_ADJ) Minimum Logic 1 Input for Three Level Input (DIVB) Minimum Logic 1/2 Input for Three Level Input (DIVB) Maximum Logic 0 Input Level Three Level Input (DIVB) Minimum HIGH Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Minimum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIHRES IILRES IIHENAB IILENAB IIHOSC IILOSC IOZH IOZL Input Current for Pins DIVB Input Current for Pins DIVB Input Current for Enable Pin OEL Input Current for Enable Pin OEH Input Current for OSC_IN Pin (Indicates Bias Resistance) Input Current for OSC_IN Pin (Indicates Bias Resistance) Output Disabled Current (Output HIGH) Output Disabled Current (Output LOW) 5.5 5.5 5.5 5.5 5.5 5.5 4.5 5.5 4.5 5.5 220 −220 90 −90 20 −20 0.001 0.001 4.49 5.49 4.40 5.40 3.86 4.86 0.1 0.1 0.44 0.44 360 −360 160 −160 100 −100 3.0 3.0 −140 −170 200 −200 85 −85 20 −20 4.05 4.95 1.8 2.2 2.7 3.3 0.45 0.45 4.40 5.40 3.76 4.76 0.1 0.1 0.44 0.44 380 −380 175 −175 125 −125 5.0 5.0 −150 −180 µA µA µA µA µA µA µA µA V V 3.15 3.85 1.35 1.65 4.05 4.95 1.8 2.2 2.7 3.3 0.45 0.45 V IOUT = −50µA IOH = −48 mA VIN = VIH or VIH IOUT = 50µA IOL = +48mA VIN = VIL or VIH VIN = 5.5V VIN = 0.0V VIN = 5.5V VIN = 0.0V VIN = 5.5V VIN = 0.0V VOUT = VCC VOUT = 0.0V V V Typ TA = −40° C to +85°C Guaranteed Limits Min 2.0 2.0 0.8 0.8 3.15 3.85 1.35 1.65 V V Max Min 2.0 2.0 0.8 0.8 V V Max Units Conditions VILTTL VIHCMOS VILCMOS VIN3L_H VIN3L_1/2 VIN3L_L VOH www.fairchildsemi.com 4 CGS3321 • CGS3322 DC Electrical Characteristics Symbol Parameter VCC (V) IOLD IOHD ICCT Minimum Dynamic Output Current Minimum Dynamic Output Current Additional Maximum ICC per Input (OEH, OEL Pins) Additional Maximum ICC per Input (DIVB) 5.5 5.5 5.5 (Continued) TA = +25°C Typ TA = −40° C to +85°C Guaranteed Limits Min 75 −75 1.5 Max Min 75 −75 1.5 Max mA mA mA VOLD = 1.65V VOHD = 3.85V VIN = VCC − 2.1V DIVB, OSC_DR Inputs Equal to VCC/2 Units Conditions ICC3L 5.5 1.5 1.5 mA AC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. VCC Symbol Parameter (V) (Note 2) fMAX tPZH tPZL tPHZ tPLZ tRISE tFALL Frequency Maximum Output HIGH Enable Time Output LOW Enable Time Output HIGH Disable Time Output LOW Disable Time Rise/Fall Time 30 pF (20% to 80%) 5.0 5.0 5.0 5.0 5.0 5.0 Min 95 1.0 1.0 1.0 1.0 1.0 TA = −40°C to + 85°C CL = 50 pF Type 110 31.5 28.0 21.5 16.0 Max MHz ns ns ns ns ns Units Note 2: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.fairchildsemi.com CGS3321 • CGS3322 CMOS Crystal Clock Generators Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com