ECWF2W154JAQ

www.fairchildsemi.com FEB388_002 FAN9611/FAN9612 400W Interleaved Dual BCM PFC Controller Evaluation Board User Guide Featured Fairchild Product: FAN9611, FAN9612 Please contact a local Fairchild Sales representative for an evaluation board. © 2010 Fairchild Semiconductor Corporation 1 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Table of Contents   1.  Overview of the Evaluation Board ............................................................................................. 3  2.  Key Features ............................................................................................................................... 4  3.  Specifications .............................................................................................................................. 5  4.  Test Procedure ............................................................................................................................ 6  5.  Schematic .................................................................................................................................... 7  6.  Boost Inductor Specification....................................................................................................... 8  7.  Line Filter Inductor Specifications ............................................................................................. 9  8.  PCB Layout ............................................................................................................................... 10  9.  Bill of Materials (BOM) ........................................................................................................... 14  10.  Test Results ....................................................................................................................... 16  10.1.  Startup ..................................................................................................................... 16  10.2.  Normal Operation ................................................................................................... 18  10.3.  Line Transient ......................................................................................................... 20  10.4.  Load Transient ........................................................................................................ 21  10.5.  Brownout Protection ............................................................................................... 22  10.6.  Phase Management ................................................................................................. 24  10.7.  Efficiency ................................................................................................................ 27  10.8.  Harmonic Distortion and Power Factor .................................................................. 28  11.  References ......................................................................................................................... 30  12.  Ordering Information ........................................................................................................ 30  13.  Revision History ............................................................................................................... 30  © 2010 Fairchild Semiconductor Corporation 2 FEB279_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com The following user guide supports the FAN9611/12 400W evaluation board for interleaved boundary-conduction-mode power-factor-corrected supply. It should be used in conjunction with the FAN9611/12 datasheet as well as the Fairchild application note AN-6086 Design Considerations for Interleaved Boundary-Conduction Mode PFC using FAN9612. Although marked FAN9612, the evaluation board can be interchangeably used to evaluate either the FAN9611 (10V turn-on threshold) or FAN9612 controller (12.5V turn-on threshold). Please visit Fairchild’s website at www.fairchildsemi.com for additional information. 1. Overview of the Evaluation Board The FAN9611/12 interleaved dual Boundary-Conduction-Mode (BCM) Power-FactorCorrection (PFC) controllers operate two parallel-connected boost power trains 180º out of phase. Interleaving extends the maximum practical power level of the control technique from about 300W to greater than 800W. Unlike the continuous conduction mode (CCM) technique often used at higher power levels, BCM offers inherent zerocurrent switching of the boost diodes (no reverse-recovery losses), which permits the use of less expensive diodes without sacrificing efficiency. Furthermore, the input and output filters can be smaller due to ripple current cancellation between the power trains and doubling of effective switching frequency. The advanced line feedforward with peak detection circuit minimizes the output voltage variation during line transients. To guarantee stable operation with less switching loss at light load, the maximum switching frequency is clamped at 525kHz. Synchronization is maintained under all operating conditions. Protection functions include output over-voltage, over-current, open-feedback, undervoltage lockout, brownout, and redundant latching over-voltage protection. The FAN9611/12 is available in a lead-free 16-lead SOIC package. This FAN9611/12 evaluation board is a four-layer board designed for 400W (400V/1A) rated power. Thanks to the phase management, the efficiency is maintained above 96% at low-line and high-line, even down to 10% of the rated output power. Efficiency is 96.4% at line voltage 115VAC and 98.2% at 230VAC under full-load conditions. © 2010 Fairchild Semiconductor Corporation 3 FEB279_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 2. Key Features Low Total Harmonic Distortion, High Power Factor 180° Out-of-Phase Synchronization Automatic Phase Disable at Light Load 1.8A Sink, 1.0A Source, High-Current Gate Drivers Transconductance (gM) Error Amplifier for Reduced Overshoot Voltage-Mode Control with (VIN)2 Feed-forward Closed-Loop Soft-Start with Programmable Soft-Start Time for Reduced Overshoot Minimum Restart Timer Frequency to Avoid Audible Noise Maximum Switching Frequency Clamp Brownout Protection with Soft Recovery Non-Latching OVP on FB Pin and Second-Level Latching Protection on OVP Pin Open-Feedback Protection Over-Current and Power-Limit Protection for Each Phase Low Startup Current: 80µA Typical Works with DC, 50Hz to 400Hz AC Inputs Figure 1. Block Diagram © 2010 Fairchild Semiconductor Corporation 4 FEB279_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 3. Specifications This board has been designed and optimized for the following conditions: Input Voltage Range VIN Nominal : 85~264VAC VDD Supply : 13VDC~18VDC Rated Output Power 400W Output Voltage (Rated Current) 400V-1A Note: 1. Minimum output voltage during the 20ms hold-up time is 330VDC. VLINE = 85~264VAC VOUT = 400V fSW > 50kHz Efficiency > 96% down to 20% load (115VAC) Efficiency > 97% down to 20% load (230VAC) PF > 0.99 at full load The trip points for the built-in protections are set as below in the evaluation board. The non-latching output OVP trip point is set at 108% of the nominal output voltage. The latching output OVP trip point is set at 117% of the nominal output voltage. The line UVLO (brownout protection) trip point is set at 68VAC (10VAC hysteresis). The pulse-by-pulse current limit for each MOSFET is set at 9.1A. The maximum power limit is set at ~120% of the rated output power. The phase management function permits phase shedding/adding ~15% of the nominal output power for high line (230VAC). This level can be programmed by modifying MOT resistor (R6). © 2010 Fairchild Semiconductor Corporation 5 FEB279_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 4. Test Procedure Before testing the board; DC voltage supply for VDD, AC voltage supply for line input, and DC electric load for output should be connected to the board properly. 1. Supply VDD for the control chip first. It should be higher than 13V (refer to the specification for VDD turn-on threshold voltage in Table 1). Table 1. Symbol Supply ISTARTUP IDD IDD_DYM VON VOFF VHYS Specification Excerpt from FAN9611/12 Datasheet Parameter Startup Supply Current Operating Current Dynamic Operating Current UVLO Start Threshold, FAN9611 UVLO Start Threshold, FAN9612 UVLO Stop Threshold Voltage UVLO Hysteresis, FAN9611 UVLO Hysteresis, FAN9612 Conditions VDD = VON – 0.2V Output Not Switching fSW = 50kHz; CLOAD = 2nF VDD Increasing VDD Decreasing VON – VOFF Min. Typ. 80 3.7 4 Max. 110 5.2 6 10.5 13.0 8.0 Unit µA mA mA V V V V V 9.5 12.0 7.0 10.0 12.5 7.5 2.5 5.0 2. Connect the AC voltage (85~265VAC) to start the FAN9611/12 evaluation board. Since FAN9611/12 has brownout protection, any input voltages lower than operation range triggers the protection. 3. Change load current (0~1A) and check the operation. © 2010 Fairchild Semiconductor Corporation 6 FEB279_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 5. Schematic Figure 2. FAN9611/12 400W Evaluation Board Schematic © 2010 Fairchild Semiconductor Corporation 7 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 6. Boost Inductor Specification PA2075NL from Pulse Engineering (www.pulseeng.com) • • • Core: PQ3230 (Ae=161mm2) Bobbin: PQ3230 Inductance : 200μH Figure 3. Boost Inductor used in this FAN9611/12 Evaluation Board Table 2. Inductor Turns Specifications Pin Turns 30 3 N1 Insulation Tape N2 Insulation Tape 5 2 3 4 © 2010 Fairchild Semiconductor Corporation 8 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 7. Line Filter Inductor Specifications A : 30mm (max) B: 15 mm (max) C: 11 mm D: 13 mm E: 15±1 mm Electrical Specifications (1kHz, 1V) - Inductance: 9.0mH (min.) for each winding - DC resistance: 0.05Ω (max.) for each winding - Number of turns: 0.9mm×2/30.5 turns for each winding Figure 4. Line Filter Inductor Specification Table 3. Component Core Materials List Material T22x14x08 THFN-216 UEWN/U UEWE UWY 96.5%, Sn, 3%, Ag, 0.5% Cu Manufacturer Core T22x14x08, TOMITA Ta Ya Electric Wire Co,. Ltd. PACIFIC Wire and cable Co., Ltd. Tai-1 Electric Wire & Cable Co., Ltd. Jang Shing Wire Co., Ltd. Xin Yuan Co., Ltd. UL File Number E197768 E201757 E85640 E174837 W ire Solder © 2010 Fairchild Semiconductor Corporation 9 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 8. PCB Layout Figure 5. First Layer (Top Side) Figure 6. Second Layer (Plane Layer) © 2010 Fairchild Semiconductor Corporation 10 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 7. Third Layer (Ground layer) Figure 8. Fourth Layer (Bottom Side) © 2010 Fairchild Semiconductor Corporation 11 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 9. Top Solder Mask Figure 10. Bottom Solder Mask © 2010 Fairchild Semiconductor Corporation 12 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 11. Top Silkscreen Figure 12. Bottom Silkscreen © 2010 Fairchild Semiconductor Corporation 13 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 9. Bill of Materials (BOM) Qty Reference 2 1 2 1 2 2 2 1 1 1 1 1 2 1 3 2 1 2 1 1 2 1 1 14 3 2 2 2 2 2 C1 C6 C2 C4 C9 C5 C7 C11 C23 C8 C13 C10 C14 C12 C15 C16 C18 C19 C20-21 C22 D1 D3-4 D2 D8 D5 D6-7 D10 F1 H1 H3 H2 J1 J2 J8-18 J21-22 J3-5 J6 J19 J7 J20 L3-4 Q1 Q4 Q2-3 571-0500 571-0100 TRN-0197 ZXTP25020DFL FDPF18N50 S3J MBR0540 GBU8J ES1J MBR0530 31.8201 534202B33453G 639BG ED100/3DS 3103-1-00-15-0000-08-0 PHE840MB 6100MB05R17 CS85B2GA471KYNS ECWF2W154JA Q B32914A3474 EETUQ2W221E HQX104K275R2 Part Number Value 0.22µF 390nF 150nF 470nF 470nF,330V 220µF 2.2µF 0.1µF, 275V 15n 0.1µF 1µF 0.1µF 470pF 1nF Description CAP, SMD, CERAMIC, 25V, X7R CAP, SMD, CERAMIC, 25V, X7R Cap, 400V, 5%, Polypropylene CAP, SMD, CERAMIC,25V, X7R Package Type 805 805 Radial, Thru-Hole 805 Manufacturer STD STD Panasonic-ECG STD EPCOS Panasonic STD Fuhjyyu Electronic Industrial Co. STD STD STD KEMET TDK Corporation STD Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Schurter Inc Aavid Thermalloy Aavid Thermalloy On Shore Technology, Inc. Mill-Max Custom Deltron Deltron SEN HUEI INDUSTRIAL CO.,LTD Zetex Fairchild Semiconductor Cap, 330VAC, 10%, Polypropylene Box, Thru-Hole Cap, Alum, Elect. CAP, SMD, CERAMIC, 25V, X7R Cap, X series 250VAC, 5%, Polypropylene CAP, SMD, CERAMIC,25V, X7R CAP, SMD, CERAMIC, 25V, X7R CAP, SMD, CERAMIC,50V, X5R Cap, X Type, 275VAC, 10%, Polypropylene Cap, Ceramic, 250VAC, 10%, Y5P, CAP, SMD, CERAMIC, 25V, X7R Diode, 600V, 3A, Std recovery Diode, Schottky,40V, 500mA Bridge Rectifier, 600V, 8A DIODE FAST REC 1A 600V DIODE SCHOTTKY 30V 500MA SOD-123 Fuseholder, 5x20mm, 250VAC, 10A Radial, Thru-Hole 1206 Box, Thru-Hole 805 805 805 Box, Axial Disc, Thru-hole 805 SMC SOD-123 Thru-Hole SMA SOD-123 PCB mount, Thruhole Heatsink, 13.4degC/W, TO-220 with 1"x0.475"x1.18" Tab-Koolclip for Q2-3 TO-220 Heat sink for D5, Bridge 1.65"x1.5" Rectifier Terminal Block, 5MM Vert., 3 Pos. Probe-pin, Gold, 0.3" x 40mil dia., 31mil mounting length Jumper wire, #16, Insulated, for current probe measurement Banana Jack, .175, Horizontal, Insulated_RED Banana Jack, .175, Horizontal, Insulated_BLK Common Mode Choke Transistor, PNP, 20V, 1.5A MOSFET, NCH, 500V, 18A, 0.265 Ohm Thru-hole Thru-Hole Thru-Hole Thru-hole Thru-hole Thru-Hole SOT-23 TO-220 Continued on following page… © 2010 Fairchild Semiconductor Corporation 14 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com BOM (Continued) Qty Reference 2 6 1 1 1 2 2 2 1 1 1 1 1 4 R1-2 R3 R9 R2728 R33-34 R4 R5 R6 R7-8 R10 R20 R11-12 R15 R16 R17 R18 R19 1 inserted into each corner of PCB 1 at D5, H2 1 at D5, H2 1 at D5, H2 1 at D5, H2 PWB R1-2 R3 R9 R2728 R33-34 R4 R5 R6 R7-8 R10 R20 R11-12 R13-14 R15 R16 Part Number Value 47kΩ 665kΩ 332kΩ 68kΩ 100kΩ 340kΩ 100Ω 15Ω DNP 49.9Ω 0 5Ω 14.7kΩ Description RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/2W Thermister, 5Ω RES, SMD, 1/8W LOCKING BOARD SUPPORT 3/4", 1 for each PCB corner Nylon Shoulder Washer #4x0.187", Black Split Lock Washer, Metric M 3 Zinc Nut Hex, #4-40 Zinc Screw Machine Phillips, 4-40x1/2" Zinc Package Type 805 805 805 805 805 805 805 805 805 805 2010 Thru-Hole 805 Standoff Manufacturer STD STD STD STD STD STD STD STD STD STD STD EPCOS STD Richco Plastic Company Keystone Electronics B&F Fastener B&F Fastener B&F Fastener Fairchild Semiconductor STD STD STD STD STD STD STD STD STD STD STD B57237S0509M000 LCBS-12-01 1 1 1 1 1 2 6 1 1 1 2 2 2 2 1 1 3103 MLWZ 003 HNZ440 PMS 440 0050 PH FAN9611/12 FEB388 Rev. 0.0.1 FEB388 47kΩ 665kΩ 332kΩ 68kΩ 100kΩ 340kΩ 100Ω 15Ω 0.022Ω DNP 49.9Ω Washer Washer Nut Screw PWB 805 805 805 805 805 805 805 805 1812 805 805 PWB, 9.8" x 6.8" RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/8W RES, SMD, 1/2W RES, SMD, 1/8W RES, SMD, 1/8W Note: 2. DNP = Do not populate. STD = standard components © 2010 Fairchild Semiconductor Corporation 15 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10. Test Results 10.1. Startup Figure 13 and Figure 14 show the startup operation at 115VAC line voltage for no-load and full-load condition, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div) Figure 13. No-Load Startup at 115VAC Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (10A/div), Time (200ms/div) Figure 14. © 2010 Fairchild Semiconductor Corporation Full-Load Startup at 115VAC 16 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 15 and Figure 16 show the startup operation at 230VAC line voltage for no-load and full-load conditions, respectively. Due to the closed-loop soft-start, almost no overshoot is observed for no-load startup and full-load startup. Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div) Figure 15. No-Load Startup at 230VAC Gate Drive 1 COMP Voltage Output Voltage Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (200V/div), CH4: Line Current (5A/div), Time (100ms/div) Figure 16. Full-Load Startup at 230VAC © 2010 Fairchild Semiconductor Corporation 17 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.2. Normal Operation Figure 17 and Figure 18 show the two inductor currents and sum of two inductor currents at 115VAC line voltage and full-load conditions. The sum of the inductor currents has relatively small ripple due to the ripple cancellation of interleaving operation. IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (5A/div), CH4: Inductor L2 Current (5A/div), F1: Sum of Two Inductor Current (5A/div), Time (2ms/div) Figure 17. Inductor Current Waveforms at Full-Load and 115VAC IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (5A/div), CH4: Inductor L2 Current (5A/div), F1: Sum of Two Inductor Current (5A/div), Time (5μs/div) Figure 18. Zoom of Inductor Current Waveforms of Figure 17 at Peak of Line Voltage © 2010 Fairchild Semiconductor Corporation 18 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 19 and Figure 20 show the two inductor currents and sum of two inductor currents at 230VAC line voltage and full-load conditions. The sum of the inductor currents has relatively small ripple due to the ripple cancellation of interleaving operation. IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (2A/div), CH4: Inductor L2 Current (2A/div), F1: Sum of Two Inductor Current (2A/div), Time (2ms/div) Figure 19. Inductor Current Waveforms at Full-Load and 230VAC IL1 IL2 IL1 + IL2 CH3: Inductor L1 Current (2A/div), CH4: Inductor L2 Current (2A/div), F1: Sum of Two Inductor Current (2A/div), Time (2μs/div) Figure 20. Zoom of Inductor Current Waveforms of Figure 19 at Peak of Line Voltage © 2010 Fairchild Semiconductor Corporation 19 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.3. Line Transient Figure 21 and Figure 22 show the line transient operation and minimal effect on output voltage due to the line feed-forward function. When the line voltage changes from 230VAC to 115VAC, about 20V (5% of nominal output voltage) voltage undershoot is observed. When the line voltage changes from 115VAC to 230VAC, almost no voltage undershoot is observed. Rectified Line Voltage VCOMP VOUT Line Current CH1: Rectified Line Voltage (100V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 21. Line Transient Response at Full-Load Condition (230VAC 115VAC) Rectified Line Voltage VCOMP VOUT Line Current CH1: Rectified Line Voltage (100V/div), CH2: COMP Voltage (2V/div), CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 22. Line Transient Response at Full-Load Condition (115VAC 230VAC) © 2010 Fairchild Semiconductor Corporation 20 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.4. Load Transient Figure 23 and Figure 24 show the load-transient operation. When the output load changes from 100% to 0%, 26V (6.5% of nominal output voltage) voltage overshoot is observed. When the output load changes from 0% to 100%, 43V (11% of nominal output voltage) voltage undershoot is observed. VOUT Rectified Line Voltage Line Current CH2: Rectified line voltage (100V/div), CH3: Output voltage (100V/div), CH4: Line current (5A/div), Time (50ms/div) Figure 23. Load Transient Response at 230VAC (Full Load No Load) VOUT Rectified Line Voltage Line Current CH2: Rectified Line Voltage (100V/div), CH3: Output Voltage (100V/div), CH4: Line Current (5A/div), Time (50ms/div) Figure 24. Load Transient Response at 230VAC (No Load Full Load) © 2010 Fairchild Semiconductor Corporation 21 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.5. Brownout Protection Figure 25 and Figure 26 show the startup operation at slowly increasing line voltage. The power supply starts up when the line voltage reaches around 78VAC . Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div), CH4: Line Current (5A/div), Time (200ms/div) Figure 25. Startup Slowly Increasing the Line Voltage Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div), CH4: Line Current (5A/div), Time (20ms/div) Figure 26. Shutdown Slowly Decreasing the Line Voltage © 2010 Fairchild Semiconductor Corporation 22 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 27 and Figure 28 show the shutdown operation at slowly decreasing line voltage. The power shuts down when line voltage drops below 68VAC. Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div), CH4: Line Current (5A/div), Time (200ms/div) Figure 27. Startup Slowly Increasing the Line Voltage Line Voltage Gate Drive 1 Line Current CH1: Line Voltage (100V/div), CH2: Gate Drive 1 Voltage (20V/div), CH4: Line Current (5A/div), Time (20ms/div) Figure 28. Shutdown Slowly Decreasing the Line Voltage © 2010 Fairchild Semiconductor Corporation 23 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.6. Phase Management Figure 29 and Figure 30 show the phase-shedding waveforms. As observed, when the gate drive signal of Channel 2 is disabled, the duty cycle of Channel 1 gate drive signal is doubled to minimize the line current glitch and guarantee smooth transient. Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div) Figure 29. Phase-Shedding Operation Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div) Figure 30. Phase-Shedding Operation (Zoomed-in Timescale) © 2010 Fairchild Semiconductor Corporation 24 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 31 and Figure 32 show the phase-adding waveforms. As observed, just before the channel 2 gate drive signal is enabled, the duty cycle of Channel 1 gate drive signal is halved to minimize the line current glitch and guarantee smooth transient. In Figure 32, the first pulse of gate drive 2 during the phase-adding operation is skipped to ensure 180 degree out-of-phase interleaving operation during transient. Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5ms/div) Figure 31. Phase-Adding Operation Gate Drive 1 Gate Drive 2 IL1 IL2 CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Inductor L1 Current (1A/div), CH4: Inductor L2 Current (1A/div), Time (5µs/div) Figure 32. © 2010 Fairchild Semiconductor Corporation Phase-Adding Operation (Zoomed-in Timescale) 25 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com Figure 33 and Figure 34 show the sum of two-inductor current and line current for phase shedding and adding, respectively. The small line-current glitch during phase management exists because the actual average value of inductor current is less than half of the peak value due to the negative portion of inductor current, as shown in Figure 30 and Figure 32. However, the phase management takes place at relatively light-load condition and the effect of this phenomenon is negligible. Gate Drive 1 Gate Drive 2 IL1 + IL1 Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Sum of Two Inductor Currents (1A/div), CH4: Line Current (1A/div), Time (5ms/div) Figure 33. Phase Shedding and Line Current Gate Drive 1 Gate Drive 2 IL1 + IL1 Line Current CH1: Gate Drive 1 Voltage (20V/div), CH2: Gate Drive 2 Voltage (20V/div), CH3: Sum of Two Inductor Currents (1A/div), CH4: Line Current (1A/div), Time (5ms/div) Figure 34. Phase Adding Operation and Line Current © 2010 Fairchild Semiconductor Corporation 26 FEB388_FAN9611/12 • Rev. 0.0.2 www.fairchildsemi.com 10.7. Efficiency Figure 35 through Figure 38 show the measured efficiency of the 400W evaluation board with and without phase management at input voltages of 115VAC and 230VAC. Phase management improves the efficiency at light load by up to 7%, depending on the line voltage and load condition. The phase management thresholds on the test evaluation board are around 15% of the nominal output power (Figure 35 and Figure 36). They can be adjusted upwards to achieve a more desirable efficiency profile (Figure 37 and Figure 38) by increasing the MOT resistor. Since phase shedding reduces the switching loss by effectively decreasing the switching frequency at light load, a greater efficiency improvement is achieved at 230VAC, where switching losses dominate. Relatively less improvement is obtained at 115VAC since the MOSFET is turned on with zero voltage and switching losses are negligible. The efficiency measurements include the losses in the EMI filter as well as cable loss; however, the power consumption of the control IC (