ETQ-P6F0R8LFA

FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller November 2010 FAN5236 Dual Mobile-Friendly DDR / Dual-Output PWM Controller Features Highly Flexible, Dual Synchronous Switching PWM Controller that Includes Modes for: Description The FAN5236 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range of 0.9V to 5.5V required to power I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs, and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to high efficiency over a wide range of loads. The Hysteretic Mode can be disabled separately on each PWM converter if PWM Mode is desired for all load levels. Efficiency is enhanced by using MOSFET RDS(ON) as a current-sense component. Feedforward ramp modulation, average-current-mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180-degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode, one of the channels tracks the output voltage of another channel and provides output current sink and source capability — essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of the set point. Built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions cease. Under-voltage protection latches the chip off when output drops below 75% of the set value after the softstart sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may be used. - DDR Mode with In-phase Operation for Reduced Channel Interference 90° Phase-shifted, Two-stage DDR Mode for Reduced Input Ripple Dual Independent Regulators, 180° Phase Shifted VTT Tracks VDDQ/2 VDDQ/2 Buffered Reference Output Complete DDR Memory Power Solution - Lossless Current Sensing on Low-side MOSFET or Precision Over-Current Using Sense Resistor VCC Under-Voltage Lockout Converters can Operate from +5V or 3.3V or Battery Power Input (5V to 24V) Excellent Dynamic Response with Voltage Feedforward and Average-Current-Mode Control Power-Good Signal Supports DDR-II and HSTL Light-Load Hysteretic Mode Maximizes Efficiency TSSOP28 Package Applications DDR VDDQ and VTT Voltage Generation Mobile PC Dual Regulator Server DDR Power Hand-held PC Power Related Resources Application Note — AN-6002 Component Calculations and Simulation Tools for FAN5234 or FAN5236 Application Note — AN-1029 Maximum Power Enhancement Techniques for SO-8 Power MOSFET © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Ordering Information Part Number FAN5236MTCX Operating Temperature Range -10 to +85°C Package 28-Lead Thin-Shrink Small-Outline Package (TSSOP) Packing Method Tape and Reel Block Diagrams +5 VCC FAN5236 VIN (BATTERY) = 5 to 24V Q1 ILIM1 L OUT1 VO UT1 = 2.5V C OUT1 PWM 1 Q2 DDR Q3 ILIM2/ REF2 L OUT2 VO UT 2 = 1.8V C OUT2 PWM 2 Q4 Figure 1. Dual-Output Regulator +5 VCC FAN5236 VIN (BATTERY) = 5 to 24V Q1 ILIM1 L OUT1 VDDQ = 2.5V C OUT1 R PWM 1 Q2 +5 DDR Q3 R VTT = VDDQ /2 C OUT2 PG2/REF 1.25V L OUT2 PWM 2 Q4 IL IM2/REF2 Figure 2. Complete DDR Memory Power Supply © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 2 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Configuration AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 FPWM1 VSEN1 ILIM1 SS1 DDR VIN 1 2 3 4 5 6 28 27 26 25 24 23 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 FPWM2 VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG1 7 22 FAN5236 8 21 9 10 11 12 13 14 20 19 18 17 16 15 Figure 3. Pin Configuration Pin Definitions Pin # 1 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 17 Name AGND LDRV1 LDRV2 PGND1 PGND2 SW1 SW2 HDRV1 HDRV2 BOOT1 BOOT2 ISNS1 ISNS2 EN1 EN2 FPWM1 FPWM2 VSEN1 VSEN2 ILIM1 SS1 SS2 Description Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4. Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. Forced PWM Mode. W hen logic LOW, inhibits the regulator from entering Hysteretic Mode; otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth transition from Hysteretic Mode to PWM Mode. When VOUT is expected to exceed VCC, tie to VCC. Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage, and over-voltage protection and monitoring. Current Limit 1. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5mA current source. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 3 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Pin Descriptions (Continued) Pin # 13 Name DDR Description DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180° out of phase. Input Voltage. Normally connected to battery, providing voltage feedforward to set the amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V input, connect through 100KΩ resistor to ground, which sets the appropriate ramp gain and synchronizes the channels 90° out of phase. Power Good Flag. An open-drain output that pulls LOW when VSEN is outside a ±10% range of the 0.9V reference. Power Good 2. When not in DDR Mode, open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition. Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference. 14 VIN 15 PG1 16 PG2 / REF2OUT 18 Current Limit 2. W hen not in DDR Mode, a resistor from this pin to GND sets the current ILIM2 / REF2 limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2. VCC VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). 28 © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 4 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN Parameter VCC Supply Voltage VIN Supply Voltage BOOT, SW, ISNS, HDRV BOOTx to SWx All Other Pins Min. Max. 6.5 27 33 6.5 Unit V V V V V ºC ºC ºC -0.3 -40 -65 VCC+0.3 +150 +150 +300 TJ TSTG TL Junction Temperature Storage Temperature Lead Temperature (Soldering,10 Seconds) Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN TA ΘJA Parameter VCC Supply Voltage VIN Supply Voltage Ambient Temperature Thermal Resistance, Junction to Ambient Min. 4.75 -10 Typ. 5.00 Max. 5.25 24 +85 90 Unit V V °C °C/W © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 5 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics Recommended operating conditions, unless otherwise noted. Symbol Power Supplies IVCC ISINK ISOURCE ISD VUVLO VUVLOH Oscillator fosc VPP VRAMP G Parameter Conditions LDRV, HDRV Open, VSEN Forced Above Regulation Point Shutdown (EN-0) VIN = 24V VIN = 0V Rising VCC Falling Min. Typ. Max. Units VCC Current VIN Current, Sinking VIN Current, Sourcing VIN Current, Shutdown UVLO Threshold UVLO Hysteresis Frequency Ramp Amplitude Ramp Offset Ramp / VIN Gain 2.2 3.0 30 µA µA µA µA µA V V mV 10 -15 4.30 4.10 4.55 4.25 300 255 300 2 1.25 0.5 125 250 0.891 0.900 5 1.5 30 -30 1 4.75 4.45 345 KHz V V V mV/V mV/V VIN = 16V VIN = 5V VIN ≤ 3V 1V < VIN < 3V Reference and Soft Start VREF ISS VSS Internal Reference Voltage Soft-Start Current Soft-Start Complete Threshold Load Regulators ISEN VSEN Bias Current VOUT Pin Input Impedance UVLOTSD Under-Voltage Shutdown UVLO ISNS Over-Voltage Threshold Over-Current Threshold % of Set Point, 2µs Noise Filter % of Set Point, 2µs Noise Filter RILIM= 68.5KΩ, Figure 12 Sourcing Sinking Sourcing Sinking IOUTX from 0 to 5A, VIN from 5 to 24V -2 50 45 70 115 112 80 55 75 120 140 12.0 2.4 12.0 1.2 At Startup 0.909 V µA V PWM Converters +2 120 65 80 125 168 15.0 4.0 15.0 2.0 % nA KΩ % % µA Output Drivers HDRV Output Resistance LDRV Output Resistance Ω Ω Continued on following page… © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 6 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Electrical Characteristics (Continued) Symbol Parameter Lower Threshold Upper Threshold PG Output Low Leakage Current PG2/REF2OUT Voltage DDR, EN Inputs VINH VINL Input High Input Low FPWM Low FPWM High FPWM Connected to Output 0.9 2 0.8 0.1 V V V V Conditions % of Set Point, 2µs Noise Filter % of Set Point, 2µs Noise Filter IPG = 4mA VPULLUP = 5V DDR = 1, 0mA < IREF2OUT ≤10mA Min. -86 108 Typ. Max. -94 116 0.5 1 Units % % V µA % VREF2 Power-Good Output and Control Pins 99.00 1.01 FPWM Inputs Block Diagram 5V VDD EN BOOT CBOOT VIN Q1 FPWM/VOUT SS HYST OVP HYST SW Q2 VDD LDRV PGND Q S R PWM RAMP PWM PWM/HYST RSENSE SH / L OU T POR/UVLO FPWM DDR HDRV VO UT COUT DDR VIN ADAPTIVE GATE CONTROL LOGIC OSC CLK RAMP ILIM det. MO ISNS VSEN EA DUTY CYCLE CLAMP CURRENT PROCESSING Σ IOU T FPWM/VOUT SS VREF PGOOD REF2 ILIM R ILIM Reference and Soft Start PWM/HYST DDR Figure 4. IC Block Diagram © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 7 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Application VIN (BATTERY) = 5 to 24V 14 VIN 28 6 BOOT1 C1 D1 +5 C5 L1 C9 +5 C4 R3 VCC Q1A 5 ILIM1 EN1 11 8 12 4 HDRV1 SW1 VDDQ = 2.5V C6A R5 C6B C2 +5 R4 SS1 PW M 1 Q1B 2 3 7 LDRV1 PGND2 ISNS1 FPWM1 (VOUT1) VSEN1 BOOT2 R7 PG1 DDR EN2 SS2 9 15 10 13 23 21 17 24 25 R1 +5 Q2A HDRV2 SW2 D2 C7 L2 R6 +5 VTT = VDDQ/2 C8A C3 1.25V at 10mA PG2/REF AGND 16 1 Q2B PW M 2 27 26 22 LDRV2 PGND2 ISNS2 VSEN2 ILIM2/REF2 R2 R8 C8B FPWM2 20 19 18 Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM Description Capacitor 68µf, Tantalum, 25V, ESR 150mΩ Capacitor 10nf, Ceramic Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω Capacitor 150nF, Ceramic Capacitor 180µf, Specialty Polymer 4V, ESR 15mΩ Capacitor 1000µf, Specialty Polymer 4V, ESR 10mΩ Capacitor 0.1µF, Ceramic 18.2KΩ, 1% Resistor 1.82KΩ, 1% Resistor 56.2KΩ, 1% Resistor 10KΩ, 5% Resistor 3.24KΩ, 1% Resistor 1.5KΩ, 1% Resistor Schottky Diode 30V Inductor 6.4µH, 6A, 8.64mΩ Inductor 0.8µH, 6A, 2.24mΩ Dual MOSFET with Schottky DDR Controller Qty. 1 2 1 2 2 1 2 3 1 2 2 1 2 2 1 1 1 1 Ref. C1 C2, C3 C4 C5, C7 C6A, C6B C8 C9 R1, R2 R6 R3 R4 R5 R7, R8 D1, D2 L1 L2 Q1, Q2 U1 Vendor AVX Any AVX Any Panasonic Kemet Any Any Any Any Any Any Any Fairchild Semiconductor Panasonic Panasonic Fairchild Semiconductor Fairchild Semiconductor Part Number TPSV686*025#0150 TAJB686*006 EEFUE0G181R T510E108(1)004AS4115 BAT54 ETQ-P6F6R4HFA ETQ-P6F0R8LFA FDS6986AS FAN5236 (1) Note: 1. Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and use AN-6002 for design calculations. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 8 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Typical Applications (Continued) V IN (BATTERY) = 5 to 24V 14 VIN 28 6 BOOT1 C1 D1 +5 C5 L1 C9 +5 C4 R2 VCC Q1A 5 ILIM1 EN1 11 8 12 4 HDRV1 SW1 2.5V at 6A C6 +5 R3 C2 SS1 PW M 1 Q1B 2 3 7 LDRV1 PGND2 ISNS1 FPWM1 (VOUT1) VSEN1 BOOT2 R6 R4 PG1 DDR 9 15 10 13 23 V IN D2 C7 L2 C8 R7 1.8V at 6A R5 +5 Q2A EN2 PG2 SS2 21 16 17 24 25 HDRV2 SW2 Q2B PW M 2 27 LDRV2 PGND2 ISNS2 VSEN2 ILIM2 C3 AGND 1 26 22 R8 R9 R1 FPWM2 20 19 18 Figure 6. Dual Regulator Application Table 2. DDR Regulator BOM Item 1 2 3 4 5 5 11 12 13 14 15 27 28 29 30 Description Capacitor 68µf, Tantalum, 25V, ESR 95mΩ Capacitor 10nf, Ceramic Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω Capacitor 150nF, Ceramic Capacitor 330µf, Poscap, 4V, ESR 40mΩ Capacitor 0.1µF, Ceramic 56.2KΩ, 1% Resistor 10KΩ, 5% Resistor 3.24KΩ, 1% Resistor 1.82KΩ, 1% Resistor 1.5KΩ, 1% Resistor Schottky Diode 30V Inductor 6.4µH, 6A, 8.64mΩ Dual MOSFET with Schottky DDR Controller Qty. 1 2 1 2 2 2 2 2 1 3 2 2 1 1 1 Ref. C1 C2, C3 C4 C5, C7 C6, C8 C9 R1, R2 R3 R4 R5, R8, R9 R6, R7 D1, D2 L1, L2 Q1 U1 AVX Any AVX Any Sanyo Any Any Any Any Any Vendor Part Number TPSV686*025#095 TAJB686*006 4TPB330ML Any Fairchild Semiconductor Panasonic Fairchild Semiconductor Fairchild Semiconductor BAT54 ETQ-P6F6R4HFA FDS6986AS FAN5236 (2) Note: 2. If currents above 4A continuous are required, use single SO-8 packages. For more information, refer to the Power MOSFET Selection Section and AN-6002 for design calculations. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 9 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Circuit Description Overview The FAN5236 is a multi-mode, dual-channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM, or other low-voltage power applications in modern notebook, desktop, and sub-notebook PCs. The IC integrates control circuitry for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The two synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery), with voltage ranging from 5.0V to 24V, or from a regulated system rail of 3.3V to 5.0V. In either mode, the IC is biased from a +5V source. The PWM modulators use an average-current-mode control with input voltage feedforward for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that reduces the external components needed. Depending on the load level, the converters can operate in fixed-frequency PWM Mode or in a Hysteretic Mode. Switch-over from PWM to Hysteretic Mode improves the converters’ efficiency at light loads and prolongs battery run time. In Hysteretic Mode, comparators are synchronized to the main clock, which allows seamless transition between the modes and reduces channel-to-channel interaction. The Hysteretic Mode can be inhibited independently for each channel if variable frequency operation is not desired. The FAN5236 can be configured to operate as a complete DDR solution. When the DDR pin is set HIGH, the second channel provides the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into Hysteretic Mode if the DDR pin is set HIGH. In DDR Mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. When VIN is from the battery, it’s typically higher than 7.5V. As shown in Figure 7, 180° operation is undesirable because the turn-on of the VDDQ converter occurs very near the decision point of the VTT converter. CLK VD DQ VTT Figure 7. Noise-Susceptible 180° Phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference when VIN is higher than 5V (when VIN is from a battery), as shown in Figure 8. Because the duty cycle of PWM1 (generating VDDQ) is short, the switching point occurs far away from the decision point for the VTT regulator, whose duty cycle is nominally 50%. CLK VDDQ VTT Figure 8. Optimal In-Phase Operation for DDR1 W hen VIN ≈ 5V, 180° phase-shifted operation can be rejected for the reasons demonstrated in Figure 7. In-phase operation with VIN ≈ 5V is even worse, since the switch point of either converter occurs near the switch point of the other converter, as seen in Figure 9. In this case, as VIN is a little higher than 5V, it tends to cause early termination of the VTT pulse width. Conversely, the VTT switch point can cause early termination of the VDDQ pulse width when VIN is slightly lower than 5V. CLK VDDQ VTT Converter Modes and Synchronization Table 3. Converter Modes and Synchronization Mode DDR1 DDR2 DUAL VIN Battery +5V ANY VIN Pin VIN R to GND VIN DDR Pin HIGH HIGH LOW PWM 2 w.r.t. PWM1 IN PHASE +90° +180° Figure 9. Noise-Susceptible In-Phase Operation for DDR2 W hen used as a dual converter, as shown in Figure 6, out-of-phase operation with 180-degree phase shift reduces input current ripple. For “two-step” conversion (where the VTT is converted from VDDQ as in Figure 5) used in DDR Mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on VIN. The objective is to keep noise generated from the switching transition in one converter from influencing the "decision" to switch in the other converter. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 10 These problems are solved by delaying the second converter’s clock by 90°, as shown in Figure 10. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. CLK VDDQ VTT Figure 10. Optimal 90° Phasing for DDR2 www.fairchildsemi.com FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Initialization and Soft Start Assuming EN is HIGH, FAN5236 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal power-on reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin, which is charged with a 5μA current source. Once CSS has charged to VREF (0.9V) the output voltage is in regulation. The time it takes SS to reach 0.9V is: t 0.9 = 0.9 xCSS 5 frequency PWM Mode, as shown in Figure 11. This mode achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. To prevent accidental mode change or "mode chatter," the transition from PWM to Hysteretic Mode occurs when the SW node is positive for eight consecutive clock cycles, as shown in Figure 11. The polarity of the SW node is sampled at the end of the lower MOSFET conduction time. At the transition between PWM and Hysteretic Mode, the upper and lower MOSFETs are turned off. The phase node “rings” based on the output inductor and the parasitic capacitance on the phase node and settles out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression: ⎛ (V − V )V OUT ⎜ OUT I LOAD ( DIS ) = ⎜ IN 2 FSW L OUT V IN ⎜ ⎝ ⎞ ⎟ ⎟ ⎟ ⎠ (1) where t0.9 is in seconds if CSS is in μF. When SS reaches 1.5V, the power-good outputs are enabled and Hysteretic Mode is allowed. The converter is forced into PWM Mode during soft-start. Operation Mode Control The mode-control circuit changes the converter mode from PWM to hysteretic and vice versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed- (2) VCORE IL 0 PWMMode 1 2 3 4 5 6 7 8 HystereticMode VCORE IL HystereticMode 0 PWMMode 4 5 6 7 8 1 2 3 Figure 11. Transitioning Between PWM and Hysteretic Mode Hysteretic Mode Conversely, the transition from Hysteretic Mode to PWM Mode occurs when the SW node is negative for eight consecutive cycles. A sudden increase in the output current causes a change from Hysteretic to PWM Mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSNS) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. In Hysteretic Mode, the PWM comparator and the error amplifier that provide control in PWM Mode are inhibited and the hysteretic comparator is activated. In Hysteretic Mode, the low-side MOSFET is operated as a synchronous rectifier, where the voltage across © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 11 VDS(ON) is monitored and switched off when VDS(ON) goes positive (current flowing back from the load), allowing the diode to block reverse conduction. The hysteretic comparator initiates a PFM signal to turn on HDRV at the rising edge of the next oscillator clock, when the output voltage (at VSNS) falls below the lower threshold (10mV below VREF) and terminates the PFM signal or when VSNS rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: Spread between the two hysteretic thresholds ILOAD Output inductor and capacitor ESR. www.fairchildsemi.com FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller A transition back to PWM continuous conduction mode (CCM) mode occurs when the inductor current rises sufficiently to stay positive for eight consecutive cycles. This occurs when: ⎛ ΔVHYSTERESIS ⎞ I LOAD( CCM ) = ⎜ ⎟ 2 ESR ⎝ ⎠ (3) Because of the different control mechanisms, the value of the load current where transition into CCM operation takes place is typically higher compared to the load level at which transition into Hysteretic Mode occurs. Hysteretic Mode can be disabled by setting the FPWM pin LOW. where ΔVHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. Figure 12. Current Limit / Summing Circuits Current Processing Section The current through the RSENSE resistor (ISNS) is sampled (typically 400ns) after Q2 is turned on, as shown in Figure 12. That current is held and summed with the output of the error amplifier. This effectively creates a current-mode control loop. The resistor connected to ISNSx pin (RSENSE) sets the gain in the current feedback loop. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET RDS(ON): ⎛ I LOAD( MAX ) • RDS( ON ) ⎞ RSENSE = ⎜ − 100 ⎟ ⎜ ⎟ 75 µA ⎝ ⎠ (4) RSENSE must, however, be kept higher than 700Ω even if the number calculated comes out to be less than 700Ω. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors, it is fairly accurate if the voltage drop on the switching-node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value varies from device to device and has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET datasheet for actual values), so the actual current limit set point decreases proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit set point should compensate for MOSFET RDS(ON) variations, assuming the MOSFET heat sinking keeps its operating die temperature below 125°C. Q2 LDRV ISNS RSENSE Setting the Current Limit A ratio of ISNS is compared to the current established when a 0.9V internal reference drives the ILIM pin: R LIM = ⎛ (100 + R ⎞ 11 ⎜ SENSE ) ⎟ x ⎟ I LOAD ⎜ R DS( ON ) ⎜ ⎟ ⎝ ⎠ R1 (5) PGND Figure 13. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 12 Improving Current-Sensing Accuracy www.fairchildsemi.com FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET, as shown in Figure 13. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT. R1 is a low value resistor (e.g. 10mΩ). Current limit (ILIMIT) should be set high enough to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, multiply ILOAD(MAX) by the inductor ripple current (e.g. 25%). For example, in Figure 6, the target for ILIMIT: ILIMIT > 1.2 x 1.25 x 1.6 x 6A Frequency Loop Compensation Due to the implemented current-mode control, the modulator has a single-pole response with -1 slope at frequency determined by load: 1 f PO = (8) 2 π ROCO where RO is load resistance; CO is load capacitance. For this type of modulator, a Type-2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design, the PWM controller has an internally compensated error amplifier. Figure 14 shows a Type-2 amplifier, its response, and the responses of a current-mode modulator and the converter. The Type-2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. fZ = fP = 1 = 6 kHz 2 π R2 C1 1 = 600kHz 2ππ 2 C2 (9) (10) ≈ 14.5A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit, pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure at especially high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to: DC MAX = V OUT V IN ⎛ 2 .4 +⎜ ⎜V ⎝ IN ⎞ ⎟ ⎟ ⎠ (7) This is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. This region is also associated with phase “bump” or reduced phase shift. The amount of phase-shift reduction depends on the width of the region of flat gain and has a maximum value of 90°. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feedforward of VIN to the oscillator ramp. The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency gain. The system designer must specify the output filter capacitors to position the load main pole somewhere within a decade lower than the amplifier zero frequency. With this type of compensation, plenty of phase margin is achieved due to zero-pole pair phase “boost.” C2 R2 Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals, providing necessary amplification, level shifting, and shoot-through protection. It also has functions that optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-to-source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to function properly. Any delay along that path subtracts from the delay generated by the adaptive dead-time circuit and shootthrough may occur. C1 VIN R1 REF EA Out C err on or ve am r te p r 18 14 0 modul ator f P0 f Z f P Figure 14. Compensation © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 13 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz to 50kHz range gives some additional phase boost. There is an opposite trend in mobile applications to keep the output capacitor as small as possible. If a larger inductor value or low-ESR values are required by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved with a capacitor across the feedback resistor (e.g. R5 from Figure 6), as shown in Figure 15. L(OUT) R5 VSEN R6 C(Z) VOUT C(OUT) regulator. If ILIM det does not occur between cycles nine and sixteen, normal operation is restored and the over-current circuit resets itself. Figure 16. Figure 15. Improving Phase Margin Over-Current Protection Waveforms The optimal value of C(Z) is: C(Z) = L(OUT) ×C(OUT) R (11) Protections The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and under-voltage conditions. A sustained overload on an output sets the PGx pin LOW and latches off the regulator on which the fault occurs. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the regulator shuts down immediately. Over-Current Sensing If the circuit’s current limit signal (“ILIM det” in Figure 12) is HIGH at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next eight clock cycles. If at any time from the ninth to the sixteenth clock cycle, the ILIM det is again reached, the over-current protection latch is set, disabling the Over-Voltage / Under-Voltage Protection Should the VSNS voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure or for other reasons, the over-voltage protection comparator forces LDRV HIGH. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, eventually blows the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ”soft” crowbar function, which accommodates severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to drop to less than 75% of the regulation set point, the regulator shuts down. Over-Temperature Protection The chip incorporates an over-temperature protection circuit that shuts the chip down if a die temperature of about 150°C is reached. Normal operation is restored at die temperature below 125°C with internal power-on reset asserted, resulting in a full soft-start cycle. © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 14 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Design and Component Selection Guidelines As an initial step, define operating input voltage range, output voltage, and minimum and maximum load currents for the controller. Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, inductor ripple current (ΔI), and the allowable ripple voltage (ΔV): Setting the Output Voltage The internal reference voltage is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 5). The output voltage therefore is: 0.9V V OUT − 0.9V = R6 R5 (12) ESR < ΔV ΔI (18) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K; for example, R6 at 1.82KΩ. Then choose R5: R5 = (1.82 KΩ )(VOUT 0 .9 − 0. 9 ) = 3.24 K (13) In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 6 is 120mVPP. Some additional ripple appears due to the capacitance value itself: For DDR applications converting from 3.3V to 2.5V or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter’s FPWM to GND. When converter’s FPWM is at GND, the converter’s maximum duty cycle is greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for in-phase synchronization by tying the VIN pin to +5V. ΔV = ΔI COUT × 8 × fSW (19) which is only about 1.5mV, for the converter in Figure 6, and can be ignored. The capacitor must also be rated to withstand the RMS current, which is approximately 0.3 X (ΔI), or about 400mA for the converter in Figure 6. High-frequency decoupling capacitors should be placed as close to the loads as physically possible. Output Inductor Selection The minimum practical output inductor value keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to Hysteretic Mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor: Input Capacitor Selection The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR Mode (shown in Figure 5), the VTT power input is powered by the VDDQ output; therefore, all of the input capacitor ripple current is produced by the VDDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: ΔI = 2 × 1MIN ΔV = OUT ESR (14) where ΔI is the inductor ripple current and ΔVOUT is the maximum ripple allowed: I REGI = I VDDQ + I VTT 2 (20) L= VIN − V OUT f SW × ΔI × V OUT VIN (15) As an example, if the average IVDDQ is 3A and average IVTT is 1A, IVDDQ current is about 3.5A. If average input voltage is 16V, RMS input ripple current is: for this example, use: VIN = 20, V OUT = 2.5 ΔI = 20 % • 6 A = 1.2A f SW = 300KHz I RMS = I OUT (MAX ) D − D (16) 2 (21) where D is the duty cycle of the PWM1 converter: D< V OUT VIN = 2.5 16 2 (22) therefore: L ≈ 6µH therefore: (17) I RMS 2.5 ⎛ 2.5 = 3.5 −⎜ 16 ⎜ 16 ⎝ ⎞ ⎟ = 1.49 A ⎟ ⎠ (23) © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 15 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller Dual Converter 180° Phased In dual mode (shown in Figure 6), both converters contribute to the capacitor input ripple current. With each converter operating 180° out of phase, the RMS currents add in the following fashion: PUPPER is the upper MOSFET’s total losses and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time), shown as t2+t3 in Figure 17. I RMS =I 2 RMS(1) +I 2 RMS( 2) or (24) (25) VDS CISS C GD C ISS IRMS = (I1 )2 (D1 − D12 ) + (I2 )2 (D 2 − D 2 2 ) which, for the dual 3A converters shown in Figure 6, calculates to: I RMS = 1.4 A (26) ID QGS VSP VTH QGD 4.5V Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5236 converter’s output voltage is low with respect to its input voltage. Therefore, the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). In contrast, the high-side MOSFET (Q1) has a shorter duty cycle and it’s conduction loss has less impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. VGS t1 t2 QG(SW) t3 t4 t5 Figure 17. Switching Losses and QG 5V C GD RD HDRV RGATE G CGS SW VIN High-Side Losses Figure 17 shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the drain-to-source and the lower graph detailing VGS vs. time with a constant current charging the gate. The Xaxis, therefore, is also representative of gate charge (QG). CISS = CGD + CGS and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by: PUPPER = PSW + PCOND Figure 18. Drive Equivalent Circuit The driver’s impedance and CISS determine t2, while t3’s period is controlled by the driver’s impedance and QGD. Since most of tS occurs when VGS = VSP, use a constant current assumption for the driver to simplify the calculation of tS: (27) (28) ⎞ ⎛ V −V (30) CC SP ⎟ ⎜ ⎜R + R GATE ⎟ ⎠ ⎝ DRIVER Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: I DRIVER QG( SW ) = QGD + QGS − QTH ts = Q G( SW ) = Q G( SW ) ⎞ ⎛ V ×I PSW = ⎜ DS L × 2 × t s ⎟ f SW ⎟ ⎜ 2 ⎠ ⎝ PCOND = V OUT VIN × I OUT 2 × R DS( ON ) (31) where QTH is the gate charge required to get the MOSFET to its threshold (VTH). (29) © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 16 FAN5236 — Dual Mobile-Friendly DDR / Dual-Output PWM Controller For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET’s gate power (PGATE) in calculating the power dissipation required for the FAN5236: PG ATE Layout Considerations Switching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of EMI if layout constraints are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rates and are noise generators. The low-power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high-dV/dt voltage swing; such as SW, HDRV, and LDRV. All surrounding circuitry tends to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use highdensity interconnect systems, or micro-vias, on these signals. The use of blind or buried vias should be limited to the low-current signals only. The use of normal thermal vias is at the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components, like the soft-start capacitor and current sense resistors, as close as possible to the respective pins of the IC. The FAN5236 utilizes advanced packaging technology with lead pitch of 0.6mm. High-performance analog semiconductors utilizing narrow lead spacing may require special considerations in design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. = Q G × V CC × f SW (32) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel Schottky diode conducting; therefore VDS ≈ 0.5V. Since PSW is proportional to VDS, Q2’s switching losses are negligible and Q2 is selected based on RDS(ON) only. Conduction losses for Q2 are given by: PCOND = (1 − D ) × I OUT 2 × R DS ( ON ) (33) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature, and: D= V OUT V IN (34) is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX)) is a function of the maximum allowable die temperature of the low-side MOSFET, the ΘJA, and the maximum allowable ambient temperature rise: PD(MAX ) = T J(MAX ) − T A (MAX ) Θ JA (35) ΘJA depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC Application Note AN-1029 — Maximum Power Enhancement Techniques for SO-8 Power MOSFETs). © 2002 Fairchild Semiconductor Corporation FAN5236 • Rev. 1.3.2 www.fairchildsemi.com 17 FAN5236 — Dual Mobile-Friendly DDR/Dual-Output PWM Controller Physical Dimensions Figure 19. 28-Lead, Thin Shrink Outline Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2002 Fairchild Semiconductor Corporation FAN5236 Rev. 1.3.2 www.fairchildsemi.com 18 FAN5236 — Dual Mobile-Friendly DDR/Dual-Output PWM Controller © 2002 Fairchild Semiconductor Corporation FAN5236 Rev. 1.3.2 www.fairchildsemi.com 19