FAN100

www.fairchildsemi.com AN-6067 Design and Application of Primary-Side Regulation (PSR) PWM Controller FAN100 / FAN102 / FSEZ1016A / FSEZ1216 Abstract This application note describes a typical charger using the PSR controller. Both the features of this controller, as well as the operation of the power supply adaptor, are presented in detail. Based on the proposed design guideline, a design example with detailed parameters is given to demonstrate the superior performance of the controller. Features Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Accurate Constant Current Achieved by Fairchild’s Proprietary TRUECURRENT™ Technique Green-Mode Function: PWM Frequency Decreasing Linearly Fixed PWM Frequency at 42kHz with Frequency Hopping to Solve EMI Problems Low Startup Current: 10μA (Typical) Low Operating Current: 3.5mA (Typical) Peak-Current-Mode Control Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection (OVP) VDD Under-Voltage lockout (UVLO) Gate Output Maximum Voltage Clamped at 18V Fixed Over-Temperature Protection (OTP) Cable Compensation for Tight CV Regulation (FAN102 / FSEZ1216) Applications Battery chargers for cellular phones, cordless phones, PDAs, digital cameras, power tools Optimal choice for the replacement of linear transformers and RCC SMPS PSR PWM Controller FAN100 FAN102 FSEZ1016A FSEZ1216 PSR PWM Controller FAN100 + Cable Compensation FAN100 + MOSFET (1A/600V) FAN102 + MOSFET (1A/600V) Pin Configurations Figure 1. FAN100 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 Figure 2. FAN102 Figure 3. FSEZ1016A Figure 4. FSEZ1216 www.fairchildsemi.com AN-6067 APPLICATION NOTE Typical Applications Vbus 7 VDD VS 5 GATE 7 VDD 3 COMI 4 COMV VS 5 GATE 3 COMI 4 COMV 6 SGND 8 8 CS PGND 1 2 CS 1 6 GND COMR 2 FAN100 Figure 5. FAN100 Figure 6. FAN102 (FAN100 + Cable Compensation) Vbus Vbus 6 VDD 3 COMI 4 COMV VS 5 6 VDD 3 COMI VS 5 DRAIN DRAIN CS 8 8 1 1 4 COMV 7 GND CS 2 GND N.C. 7 COMR 2 FSEZ1016A Figure 7. FSEZ1016A (FAN100 + MOSFET) FSEZ1216 Figure 8. FSEZ1216 (FAN102 + MOSEFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 2 AN-6067 APPLICATION NOTE Block Diagrams Figure 9. FSEZ1016A (FAN100 + MOSFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 3 AN-6067 APPLICATION NOTE Block Diagrams (Continued) Figure 10. FSEZ1216 (FAN102 + MOSFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 4 AN-6067 APPLICATION NOTE Introduction This highly integrated PSR PWM controller contains several features to enhance the performance of low-power flyback converters. The patented topology of the PSR controller allows for simplified of circuit designs, particularly battery charger applications. CV and CC control can be accurately achieved without secondary feedback circuitry. With the addition of frequency-hopping in PWM operation, EMI problems can be solved using minimized filter components. As a result, a low-cost, smaller, and lighter charger is produced when compared to a conventional design or a linear transformer. To minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease the PWM frequency under light-load conditions. This green-mode function is designed to help the power supply meet power conservation requirements. The startup current is only 10µA, which allows for the use of large startup resistance for further power savings. The PSR controller also provides numerous protection functions. The VDD pin is equipped with over-voltage protection and under-voltage lockout. Pulse-by-pulse current limiting and CC control ensure over-current protection during heavy loads. The GATE output is clamped at 15V to protect the external/internal MOSFET from over-voltage damage. Additionally, the internal over-temperatureprotection function shuts down the controller with auto recovery when over heating occurs. By using the PSR controller, a charger can be implemented with few external components and at a minimized cost. Internal Block Operation Constant Voltage Output Regulation PSR controller’s innovative method can achieve accurate output CV/CC characteristic without voltage and current sensing circuitry on the secondary side. The application circuit and a conceptualized internal block diagram relating to the constant voltage regulation are shown in Figure 11, and the key waveform is shown in Figure 12. The secondary output status is taken from the primary auxiliary winding when the MOSFET is off. A unique sampling method is used to acquire a duplication of the output voltage (Vsah) and the output diode discharge time (tdis). The sampled voltage (Vsah) is then compared with the precise internal reference voltage (Vref) to determine the on-time of the MOSFET by modulating error amplifier’s output. This inexpensive method achieves accurate output voltage regulation. Vin iS IO Naux Npri Nsec CO RO n :1 + VO − R1 VS Vref S/H PWM Vsah iP CS R2 COMV RS Figure 11. Internal Block of Constant Voltage Output Operation © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 5 AN-6067 APPLICATION NOTE Constant Current Output Regulation As shown in Figure 12, the output current IO can be expressed by Equation 1 when the flyback converter is operated in DCM. As a result, the output current IO can be calculated by the signal ipk, tdis. The PSR controller then determines the on-time of the MOSFET to modulate input power and provide constant output current. Green-Mode Operation The proprietary green-mode function of the PSR controller provides off-time modulation to linearly decrease the PWM frequency at light-load conditions, as low as 500Hz. With the green-mode function, the power supply can easily meet the most stringent of power conservation requirements. Figure 13 shows the characteristics of the PWM frequency vs. the output voltage of the error amplifier (VCOMV). The PSR controller uses the positive, proportional, output load parameter (VCOMV) as an indication of the output load for modulating the PWM frequency. In heavy load conditions, the PWM frequency is fixed at 42KHz. Once VCOMV is lower than VN, the PWM frequency starts to linearly decrease from 42KHz to 500Hz. Figure 14 is a measured waveform at burst-mode operation. Frequency Gate Vin Lp Ts iP i pk ton tdis n ⋅ Vo Lp 2 iS VS IO 42KHz 40KHz sampling voltage 1KHz 500Hz Figure 12. Principal Operation Waveform of the Flyback Converter (DCM) VG VN VCOMV Figure 13. PWM Frequency vs. VCOMV The current-sense resistor can adjust the value of the constant current. Through better design of the transformer operations under discontinuous current mode, the PSR controller’s proprietary control structure is able to achieve accurate and constant current characteristics. Detailed design guideline for the transformer is introduced in the following section. Vo(AC) 100mV/Div Gate 10V/Div VCOMV 500mV/Div Io = = 1 ⋅ t dis ⋅ is , pk 2Ts [ ] ] (1) 1 ⋅ n p ⋅ i pk ⋅ t dis 2Ts ⎤ V 1⎡ = ⋅ ⎢n p ⋅ CS ⋅ t dis ⎥ 2Ts ⎣ RCS ⎦ [ Figure 14. Measured Waveform at Burst-Mode Operation where: is,pk is the peak inductor current of the secondary side, ipk is the peak inductor of primary side. tdis is discharge-time of transformer inductor current. np is the turn ratio between primary and secondary winding. RCS is the current-sense resistor. VCS is the voltage on current-sense resistor. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 6 AN-6067 APPLICATION NOTE Frequency Hopping Operation A frequency hopping function is built in to further improve EMI system performance. The frequency hopping period is no longer than 3ms and the PWM switching frequency range is 42kHz +/- 2.6kHz. 42kHz frequency, the MOSFET’s on-time is determined by VCOMI to modulate the output current. CC Regulation CV Regulation decreasing output impedance VCOMV 4.5V VCOMI Charging Sequence Deep Green Mode 44.6KHz +/- 2.6KHz Figure 17. CV/CC Regulation Charging Sequence 39.4KHz Frequency Hopping Period → 3mS Temperature Compensation The PSR controller has built-in temperature compensation circuitry to provide constant reliable voltage regulation even at a different ambient temperature. This internal positive temperature coefficient (PTC) compensation current is used to compensate for the temperature due to the forwardvoltage drop of the diode output. Without temperature compensation, the output voltage is distinctly higher in high temperatures than in lower temperature condition, as shown in Figure 18. Figure 15. Gate Signal with Frequency Hopping CV / CC Regulation Battery chargers are typically designed for two modes of operation, constant-voltage charging and constant-current charging. The basic charging characteristic is shown in Figure 16. When the battery voltage is low, the charger operates on a constant current charging. This is the main method for charging batteries and most of the charging energy is transferred into the batteries. When the battery voltage reaches its end-of-charge voltage, the current begins to taper-off. The charger then enters the constant voltage method of charging. Finally, the charging current continues to taper-off until reaching zero. Vo(V) CV Regulation Vo high temp. after compensation at high temp. room temp. Io Figure 18. Output V-I Curve with Temperature Compensation CC Regulation Charging Sequence As shown in Figure 19, the accuracy value of R1 and R2 determines the voltage regulation amount. The suggested deviation for R1 and R2 is a +/-1% tolerance. Temperature Compensation Io(mA) Figure 16. Basic Charging V-I Characteristic PTC As mentioned in the CV regulation region section, the VCOMV modulates MOSFET’s on-time and PWM frequency to provide enough power to the output load. As shown in Figure 17, as the output load increases, VCOMV gradually rises until the system shifts into the CC regulation region. At the same time, VCOMV increases to 4.5V and the MOSEFT’s on time is controlled by VCOMI. However, when power system operates in the CC regulation region at a fixed Vs S/H Auxiliary Winding Vref PSR Controller Figure 19. Temperature Compensation www.fairchildsemi.com 7 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 AN-6067 APPLICATION NOTE Startup Circuitry When the power is activated, the input voltage charges the hold-up capacitor (C1) via the startup resistors, as shown in Figure 20. As the voltage (VDD) reaches the startup voltage threshold (VDD-ON), the PSR controller activates and drives the entire power supply. The maximum power dissipation of RIN is: PRIN ,MAX (V = dc , max − VDD ) 2 RIN V ≅ dc ,max RIN 2 (3) where Vdc,max is the maximum rectified input voltage. Take a wide-ranging input (90VAC~264VAC) as an example, Vdc =100V~380V: Vdc R IN TD_ON PRIN ,MAX VDD PSR Controller GND 380 2 = ≅ 96mW 1.5 ×10 6 (4) D1 C1 Built-in Slope Compensation The sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Within every switching cycle, the PSR controller produces a positively sloped, synchronized ramp signal. The built-in slope compensation function improves power supply stability and prevents peak-current-mode control from causing sub-harmonic oscillations. Figure 20. Single-Step Circuit Connected to the PSR Controller The power-on delay is determined as follows: TD _ ON ⎛ VDD −ON = − RIN ⋅ C1 ⋅ ln⎜1 − ⎜ V ⋅ 2−I ac DD − ST ⋅ RIN ⎝ ⎞ ⎟ ⎟ ⎠ Leading Edge Blanking (LEB) (2) where IDD-ST is the startup current of the PSR controller. Due to the low startup current, a large RIN value, such as 1.5MΩ can be used. With a hold-up capacitor of 4.7µF, the power-on delay TD_ON is less than 3s for a 90VAC input. If a shorter startup time is required, a two-step startup circuit, as shown in Figure 21, is recommended. In this circuit, a smaller C1 capacitor can be used to decrease startup time without a need for a smaller startup resistor (RIN) and increase the power dissipation on the RIN resistor. The energy supporting the PSR controller after startup is mainly from a larger capacitor C2. Each time the MOSFET is powered on, a spike, induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, appears on the sensed signal. To avoid premature termination of the MOSEFT, a leadingedge blanking time is introduced in the PSR controller. During the blanking period, the current-limit comparator is disabled and unable to switch off the gate driver. Under-Voltage Lockout (UVLO) The power-on and off thresholds of the PSR controller are fixed at 16V/5V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable PSR controller. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer (VDD must not drop below 5V during this startup process). This UVLO hysteresis window ensures that the hold-up capacitor can adequately supply VDD during startup. Vdc R IN VDD PSR Controller GND TD_ON VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage due to overvoltage conditions. When VDD exceeds 28V due to abnormal conditions, PWM output is turned off. Over-voltage conditions are usually caused by open feedback loops. C1 C2 Over-Temperature Protection (OTP) The PSR controller has a built-in temperature sensing circuit to shut down the PWM output if the junction temperature exceeds 145°C. When the PWM output shuts down, the VDD voltage gradually drops to the UVLO voltage. Some of the internal circuits shut down and VDD gradually starts www.fairchildsemi.com 8 Figure 21. Two Steps of Providing Power to the PSR Controller © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 AN-6067 APPLICATION NOTE increasing again. When VDD reaches 16V, all the internal circuits, including the temperature sensing circuit, start operating normally. If the junction temperature is still higher than 145°C, the PWM controller shuts down immediately. This continues until the temperature drops below 120°C. For example, a power board for a charger application is 5V/1A. Short the COMR pin to GND first and measure the output voltage from light load to maximum load. If the output voltage with cable is 4.7V at 1A, the percentage to 5V is 6%. Calculate the RCOMR as: GATE Output The PSR controller BiCMOS output stage is a fast totem pole gate driver. Cross conduction design elimination was used to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode for the protection of power MOSFET against over-voltage gate signals. RCOMR = 6 ≅ 59.5KΩ 100.8 × 10 −6 (6) Choose the approximate value of RCOMR and let the output voltage compensate gradually. Figure 23 is RCOMR compared to percentage curve for reference. 12 10 Percentage (%) Brownout Protection The PSR controller has a built-in brownout protection circuit to shut down the PWM output. As the input voltage decreases, the flowing current from VS pin is less than IVSUVP, the PWM output shuts down immediately and enters an auto restart mode. The VDD voltage gradually drops to the UVLO voltage. 8 6 4 2 0 10 20 30 39 51 60 R COMR (K ohm) 68 81 91 100 Figure 23. RCOMR vs. Percentage R VS Vs I VS-UVP Lab Note Auxiliary Winding PSR Controller MOS turns on Figure 22. Brownout Protection Before reworking or soldering / desoldering on the power supply, discharge the primary capacitors by way of the external bleeding resistor. If not, the PWM IC may be destroyed by external high-voltage discharge during the soldering / desoldering. Cable Compensation The FAN102/FSEZ1216 PWM controller has a cable compensation function used to compensate the output voltage drop due to output cable loss. Use an external resistor connected from COMR pin to GND adjusts the amount of cable compensation. In CV regulation control, the on-time of MOSFET only regulates on-board voltage, not including output cable. Different cable wire gauge or length results in different output voltage. As previous mentioned in the CC regulation control section that can calculate the output current. This calculated signal can provide the controller the output load condition and determine the amount of cable compensation, then rescue output voltage drop. To calculate compensation percentage, use the equation below: RCOMR = Percentage 100.8 × 10 −6 (5) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 9 AN-6067 APPLICATION NOTE Application Information Transformer Design The transformer inductor current must operate in DCM under any conditions. A typical output V-I curve is shown in Figure 24. For discontinuous current mode operation, the transformer inductor should be small enough to meet this condition. Point “B” is the lowest output voltage within the CC regulation and the widest discharge time of the transformer inductor due to the reflected voltage on the primary inductor. It is the easiest into CCM condition for transformer inductor. Point “A” is the maximum output power of the power system. Ensure that the magnetic flux density falls within 0.25~0.3 Tesla, considered a safe range. The number of turns for primary transformer inductor can be determined on point “A.” Figure 25 shows the characteristic curve of turn ratio and transformer inductance. Determine Maximum and Minimum Input Voltage Figure 26 shows the corrected input voltage waveform. The red line shows ripple voltage on the bulk capacitor and the minimum and maximum voltage on the bulk capacitor is expressed in equations 7 and 8, respectively. The CBULK is the input capacitor and a typical value is 2-3µF per watt of output power for wide range input voltage (90-264V). Vin.min Assume 2.5mS Figure 26. Bridge Rectifier and Bulk Capacitor Voltage Waveform Vo maximum output power (determine turn number ) Vin. min = 2 ⋅ Vac ,min 2 - 2 ⋅Vo ⋅ I o ⋅ (1- 0.3) η ⋅ Cbulk ⋅ 120 (7) Vin.max = 2 ⋅Vac.max (8) A determine primary inductor B Io Figure 24. Critical Operating Points to Determine the Transformer Determine the Turn Ratio The transformer turn ratio (np=Npri/Nsec) is an important parameter of the flyback converter; it affects the maximum duty ratio when the input voltage is at a minimum value. It also influences the voltage stresses on the MOSFET and the secondary rectifier. The permissible voltage stresses and the maximum voltage stresses on the MOSFET, as well as the secondary rectifier, can be expressed as: VDS . max = Vin.max + n p ⋅ (Vo + V f ) B=0.5V 3.5 3 inductance(mH) 2.5 2 1.5 1 0.5 0 5 6 7 8 9 10 11 12 13 14 15 n(turn ratio) B=1V B=1.5V B=2V (9) VF .max = Vin.max + Vo np (10) The leakage spike due to leakage inductance on the MOSFET and rectifier must also be taken into account. Determine Transformer Inductance Determine the VDD voltage level and if the output voltage is defined. The turn ratio between auxiliary winding and secondary winding can be calculated as: Io = 1A, Vf = 0.45V na = VDD + V fa VO + V f (11) Figure 25. Characteristic Curve of Turn Ratio and Inductance where VDD is voltage on VDD cap, usually ranging from about 15V~20V. In the CC regulation region, on point “B,” the power system shuts down if the output voltage is too low and the VDD © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 10 AN-6067 APPLICATION NOTE voltage reaches the turn-off threshold voltage of the PSR controller. Therefore, if na was calculated, the Vo,“B” can be obtained as: Determine Primary Inductance Turn Number Based on Faraday’s law and the peak inductor current, the minimum turns for the primary inductance is calculated as: ⎛ V fa + 6.75 - V f ⋅ na ⎞ VO ," B " = ⎜ ⎟ na ⎝ ⎠ where: (12) N pri = where: Lp ⋅ i pk ," A" Bmax ⋅ Ae ⋅ 106 (17) Vfa is forward-voltage of rectifier diode of auxiliary winding. Vf is forward-voltage of output diode. 6.75V is typically the turn-off threshold voltage of the PSR controller. The maximum duty ratio can be calculated by using a point “B” output condition: Bmax is the saturation magnetic flux density, Ae is the effective area of the core-section. The number of turns for the secondary winding is defined as: N sec = N pri np (18) d on.max," B " = n p ⋅ (Vo ," B " + V f ) Vin.min," B " + n p ⋅ (Vo ," B " + V f ) (13) Once the secondary winding has been calculated, the number of turns for the auxiliary winding is defined as: The transformer inductance (Lp) is designed specifically for DCM operation and a CC tolerance of +/-10% should be considered. The transformer inductance can be obtained as: N aux = na ⋅ Nsec (19) Lp = where: η," B " ⋅ Vin. min," B "2 ⋅ d max," B " 2 2 ⋅Vo," B " ⋅ I o ⋅ f s (14) Determine the Divider Resistor (R1) and CurrentSense Resistor (RS) Once the output voltage VO and auxiliary winding have been defined, the feedback signal divider resistor, R1, can be calculated as: η,”B” is the estimated system efficiency of point “B.” If no values are available, use 0.45~0.5 as an initial value. fs is the PWM frequency. After the primary inductance is calculated, the maximum duty ratio of point “A” can be expressed as: ⎡n ⎤ R1 = R2 ⋅ ⎢ a ⋅ (VO + V f ) − 1⎥ ⎢ Vref ⎥ ⎣ ⎦ where Vref=2.5V, R2 is typically set to 15~20KΩ. (20) d on . max," A" 2 ⋅ VO ," A" ⋅ I O ⋅ LP = η," A" ⋅ Vin . min," A" 2 ⋅ Ts (15) where Ts is the switching period. The primary peak inductor current (IPK) of point “A” at full load and low line input voltage condition is: As discussed in the Constant Current Output Regulation section, the region of constant current output operation can be adjusted by the current-sense resistor. After the turn ratio (np) has been determined, the relationship between the output current IO and current sense resistor Rs is expressed as: RS = 0.111875 ⋅ n p IO (21) i pk ," A" = Vin.min," A" Lp ⋅ don.max," A" ⋅ TS (16) As Figure 27 shows, a design spreadsheet can be used to calculate the transformer design and select the power system components for a first prototype. A 5V/1A design example is shown in Figure 27. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 11 AN-6067 APPLICATION NOTE Figure 27. Calculated System Parameter by Design Spreadsheet The parameters in Figure 27 can be found in the corresponding components in Figure 28. Vdc Rin Vdc - VFa + + VF - Naux R1 VDD Npri Nsec + n : n p :1 Vds a + VO − VS VDD Cap. Vs Cap. R2 RS - Figure 28. Application Circuit Vin 1 6 Transformer Structure As mentioned in the Constant Voltage Output Regulation section, the PSR controller incorporates a proprietary control design to achieve CV/CC regulations. A correct sampling voltage of the auxiliary winding is critical to the CV/CC performance. Therefore, the coupling of the auxiliary winding and the secondary winding should be precise. The suggested transformer structure is shown in Figure 29 and Figure 30. The coupling coefficient between the secondary winding and the auxiliary winding can be effectively improved by sloughing off the EMI shielding between auxiliary winding and secondary winding. Further effectiveness is achieved by increasing the coupling area through a well-paved the auxiliary winding on the top layer. Primary Winding MOS ' s Drain N1 N2 Secondary Winding 8 2 3 Auxiliary Winding 4 N3 EMI Shielding Figure 29. Transformer Winding 3 6 EMI Shielding 1 4 Auxiliary Winding ( N 3) Secondary Winding ( N 2) ( Insulated ) Primary Winding ( N1) 8 2 EMI Shielding Figure 30. Recommended Transformer Structure © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 12 AN-6067 APPLICATION NOTE Effect of the Vs Pin Capacitor A VS capacitor with 22~68pF placed closely between Vs pin and the GND pin is recommended. The capacitor is used to bypass switching induced noise and keep the accuracy of the sampled voltage. The value of the capacitor affects the load regulation and constant current performance. Figure 31 illustrates the measured waveform on the Vs pin with a different VS capacitor. If a higher value VS capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. Figure 32 shows the effect on the sampled voltage with a different VS capacitor. Figure 33 shows a measured Vs pin waveform at a no-load condition. As illustrated, the feedback voltage is too narrow. Additionally, a large VS capacitor causes the inaccurate sampling of the voltage; resulting in the rising of the output voltage. Figure 24 shows the influence of the VS capacitor on the V-I curve. VS No-Load No-Load Gate COMV Vf Figure 33. Measured Vs Pin Waveform at No Load Vo Lower Vs Cap. Higher Vs Cap. Io Figure 34. Comparison of V-I Curve with Different Vs Capacitor Effect of VDD and Snubber Capacitors VDD voltage and snubber capacitors are related to the feedback signal inaccuracy and cause output voltage to rise at no-load condition. Figure 31. Measured Waveform with Different VS Capacitor Vs pin waveform higher Vs Cap lower Vs Cap sampling voltage If the VDD capacitor is not big enough, the decreasing PWM frequency at no-load condition causes VDD voltage to drop quickly. In such a condition, the feedback signal is dominated by the VDD voltage, but not the secondary output voltage. To avoid this, it is recommended the VDD capacitor value be larger than 4.7µF(6.8~10µF). On the other hand, the value of the snubber capacitor also affects the output voltage performance. When the MOSEFT is turned off, the polarity of the transformer primary side inductor is reversed and the energy stored in the transformer inductor is delivered to the secondary to supply load current. In the meantime, if the output voltage is higher than the voltage on the secondary winding (Vsec), the output diode is still reversed. The resulting voltage Vpri is then applied to the primary inductor, Lp, which charges the snubber capacitor. The charge time influences the feedback voltage signal on the auxiliary winding. It is recommended that the snubber capacitor remain under 472pF(332~102pF). www.fairchildsemi.com 13 sampling voltage No - Load Figure 32. Effect on Sampling Voltage with Different VS Capacitor © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 AN-6067 APPLICATION NOTE - V fa + Ra Vin + Vf - + R1 VDD + Vpri - + Vsec - Vaux - + VO − VO > Vsec SGP100 VS na : n p : 1 R2 VDD Cap. Vs Cap. Figure 35. VDD and Snubber Capacitors Effect on Output Voltage Reducing No-Load Output Voltage with a “Dummy” Load At no-load and very light load conditions, due to the very low PWM frequency caused by feedback signal deviations and output voltage rises, especially at low-line input voltage condition. Increasing the addition of a dummy load can fix this problem. Figure 36 shows the effect of a higher and lower dummy load on the V-I curve. The level of the dummy load is suggested at about 25~100mW. Vo lower snubber cap, higher VDD cap , dummy load higher snubber cap, lower VDD cap , dummy load Io Figure 36. Dummy Load Effect on Output Characteristic © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 14 AN-6067 APPLICATION NOTE PCB Layout Considerations High-frequency switching current / voltage make PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. Suggestion for the Ground Connections GND 3→2→4→1: May make it possible to avoid common impedance interference for the sense signal. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. Then the charges go from GND2 to GND1 and back to the mains. It should be noted that control circuits should not be placed on the discharge path. 5 Should a point-discharge route to bypass the static electricity energy. As shown in Figure 38, it is suggested to map out this discharge route. Start in secondary GND to the positive terminal of C2, then to front terminal of bridge rectifier. If this discharge route is connected to the primary GND, it should be connected to the negative terminal of C2 (GND1) directly. However, the creepage distance between these two pointed ends should be long enough to satisfy the requirements of applicable standards. General Guidelines The numbers in the following guidelines refer to Figure 37. To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors C1 and C2 first, then to the switching circuits. The high-frequency current loop is in C2 – Transformer – MOSFET – R7 – C2. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4→1) short, direct, and wide. High voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to a ground. As indicated by 3, the ground of the control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by the transformer aux winding, D1 and C3, should also be kept small. Place C3 close to the PSR controller for good decoupling. R13 5 BD1 C1 C2 L1 5 T1 R8 C6 D4 R1 1 D1 C3 R2 R3 U1 7 VDD VS 5 GATE 2 C5 D3 3 COMI C8 R10 8 1 2 R4 R5 4 6 COMV SGND CS PGND R6 R7 C7 R9 4 PSR Controller 3 Figure 37. Layout Consideration © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 15 AN-6067 APPLICATION NOTE PCB Layout Considerations (Continued) Figure 38. PCB Layout Example (5V/1A, 5W Power Board) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 16 AN-6067 APPLICATION NOTE Reference Circuits R13 BD1 L1 R11 T1 D4 C8 L2 R8 C1 C2 C5 C9 D3 R1 D1 C3 C10 R12 R2 R3 U1 7 3 C7 R10 VDD VS 5 C4 R4 COMI GATE 8 R5 R6 R7 4 COMV CS PGND 1 2 C6 R9 6 SGND Figure 39. Application Circuit FAN100 (5V/1A) BOM List Symbol Component R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 BD1 D1 D3 Resistor 1.5MΩ 1/2W Resistor 4.7Ω Resistor 115KΩ 1% Resistor 18KΩ 1% Resistor 47Ω Resistor 100Ω Resistor 1.4Ω 1/2W 1% Resistor 100KΩ 1/2W Resistor 200KΩ Resistor 30KΩ Resistor 47Ω Resistor 510Ω WireWound Resistor 18Ω Rectifier Diode 1N4007 *4 Diode 1A/200V FR103 Diode 1A/1000V 1N4007 Symbol Component D4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 L1 L2 Q1 U1 TR1 Diode 5A/60V SB560 Electrolytic Capacitor 1µF/400V Electrolytic Capacitor 10µF/400V Electrolytic Capacitor 10µF/50V MLCC X7R 22pF Snubber Capacitor 472pF/1KV MLCC X7R 683pF MLCC X7R 103pF MLCC 102pF/100V Electrolytic Capacitor 560uF/10V L-ESR Electrolytic Capacitor 330µF/10V L-ESR Inductor 1mH Inductor 5µH Fairchild 2A/600V 2N60 TO-251 FAN100 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 17 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R10 L1 BD1 C1 C2 R8 C8 D4 L2 T1 R5 C5 C9 D3 C10 R9 R1 D1 C3 U1 R2 6 VDD VS DRAIN CS 5 C4 R3 3 C7 R7 COMI COMV 8 4 1 7 R4 C6 R6 2 GND N.C. Figure 40. Application Circuit FSEZ1016A (FAN100 + MOSFET) (5V/1A) BOM List Symbol R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 BD1 D1 D3 D4 Component Resistor 1.5MΩ Resistor 127KΩ 1% Resistor 20KΩ 1% Resistor 1.36Ω 1/2W 1% Resistor 100KΩ 1/2W Resistor 200KΩ Resistor 39KΩ Resistor 47Ω Resistor 510Ω WireWound Resistor 18Ω Rectifier Diode 1N4007 *4 Diode 1A/200V FR103 Diode 1A/1000V 1N4007 Diode 5A/60V SB560 Symbol C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 L1 L2 U1 TR1 Component Electrolytic Capacitor 1µF/400V Electrolytic Capacitor 10µF/400V Electrolytic Capacitor 10µF/50V MLCC X7R 47pF Snubber Capacitor 472pF/1KV MLCC X7R 683pF MLCC X7R 103pF MLCC 102pF/100V Electrolytic Capacitor 560µF/10V Electrolytic Capacitor 330µF/10V Inductor 1mH Inductor 5µH FSEZ1016A EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 18 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R13 BD1 L1 T1 R8 R11 D4 C9 L2 C6 C1 C2 D3 R1 C10 C11 R12 D1 C3 R3 U1 R4 7 VDD VS GATE 5 C5 3 COMI C8 R10 8 1 R5 R6 Q1 R7 4 COMV CS C7 R9 6 GND COMR 2 R2 C4 Figure 41. Application Circuit FAN102 (5V/1A) BOM List Symbol Component R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 BD1 D1 Resistor 1.5MΩ 1/2 W Resistor 82KΩ 1% Resistor 110KΩ 1% Resistor 18KΩ 1% Resistor 47Ω Resistor 100Ω Resistor 1.4Ω 1/4W 1% Resistor 100KΩ 1/2W Resistor 200KΩ Resistor 47KΩ Resistor 20Ω Resistor 510Ω WireWound Resistor 18Ω Rectifier Diode 1N4007 *4 Diode 1A/200V FR103 Symbol Component D3 D4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 L1 L2 Diode 1A/1000V 1N4007 Diode 5A/60V SB560 Electrolytic Capacitor 1µF/400V Electrolytic Capacitor 10µF/400V Electrolytic Capacitor 10µF/50V MLCC 104pF MLCC X7R 22pF Snubber Capacitor 472pF/1KV MLCC X7R 683pF MLCC X7R 103pF MLCC 102pF/100V Electrolytic Capacitor 560µF/10V L-ESR Electrolytic Capacitor 330µF/10V L-ESR Inductor 1mH 1/2W Inductor 5µH Symbol Component Q1 TR1 U1 1A/600V 1N60 TO-251 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 FAN102 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 19 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R10 BD1 C1 C2 D3 L1 R8 C8 D4 L2 T1 R5 C5 C9 C10 R9 R1 D1 C3 U1 R2 6 VDD VS DRAIN CS 5 C4 R3 3 C7 R7 COMI COMV 8 4 1 2 R11 R4 C6 R6 7 GND COMR C11 Figure 42. Application Circuit FSEZ1216 (5V/1A) BOM List Symbol Component R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 BD1 D1 D3 Resistor 1.5M Ω Resistor 110KΩ 1% Resistor 18KΩ 1% Resistor 1.4Ω 1/2W 1% Resistor 100KΩ 1/2W Resistor 200KΩ Resistor 47KΩ Resistor 47Ω Resistor 510Ω WireWound Resistor 18Ω Resistor 82KΩ 1% Rectifier Diode 1N4007 *4 Diode 1A/200V FR103 Diode 1A/1000V 1N4007 Symbol Component D4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 L1 L2 Diode 5A/60V SB560 Electrolytic Capacitor 1µF/400V Electrolytic Capacitor 10µF/400V Electrolytic Capacitor 10µF/50V MLCC X7R 47pF Snubber Capacitor 472pF/1KV MLCC X7R 683pF MLCC X7R 103pF MLCC 102pF/100V Electrolytic Capacitor 560µF/10V Electrolytic Capacitor 330µF/10V MLCC X7R 104pF Inductor 1mH Inductor 5µH Symbol Component U1 TR1 FSEZ1216 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 20 AN-6067 APPLICATION NOTE Related Datasheets FAN100 — Primary-Side Regulation PWM Controller FAN102 — Primary-Side Regulation PWM Controller FSEZ1016A — Primary-Side Regulation PWM with Integrated Power MOSFET FSEZ1216 — Primary-Side Regulation PWM with Integrated Power MOSFET DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 21