FAN3111

FAN3111 — Single 1A High-Speed, Low-Side Gate Driver January 2011 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Features             1.4A Peak Sink / Source at VDD = 12V 1.1A Sink / 0.9A Source at VOUT = 6V 4.5 to 18V Operating Range FAN3111C Compatible with FAN3100C Footprint Two Input Configurations: Dual CMOS Inputs Allow Configuration as Non-Inverting or Inverting with Enable Function Single Non-Inverting, Low-Voltage Input for Compatibility with Low-Voltage Controllers Small Footprint Facilitates Distributed Drivers for Parallel Power Devices 15ns Typical Delay Times 9ns Typical Rise / 8ns Typical Fall times with 470pF Load 5-Pin SOT23 Package Rated from –40°C to 125°C Ambient Description The FAN3111 1A gate driver is designed to drive an Nchannel enhancement-mode MOSFET in low-side switching applications. Two input options are offered: FAN3111C has dual CMOS inputs with thresholds referenced to VDD for use with PWM controllers and other input-signal sources that operate from the same supply voltage as the driver. For use with low-voltage controllers and other input-signal sources that operate from a lower supply voltage than the driver, that supply voltage may also be used as the reference for the input thresholds of the FAN3111E. This driver has a single, non-inverting, low-voltage input plus a DC input VXREF for an external reference voltage in the range 2 to 5V. The FAN3111 is available in a lead-free finish industrystandard 5-pin SOT23. Applications      Switch-Mode Power Supplies Synchronous Rectifier Circuits Pulse Transformer Driver Logic to Power Buffer Motor Control Figure 1. FAN3111C (Top View) Figure 2. FAN3111E (Top View) © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Ordering Information Part Number FAN3111CSX FAN3111ESX Input Threshold CMOS External Package 5-Pin SOT23 5-Pin SOT23 Packing Method Tape & Reel Tape & Reel Quantity per Reel 3,000 3,000 Thermal Characteristics(1) Package 5-Pin SOT23 JL(2) 58 JT(3) 102 JA(4) 161 JB(5) 53 JT(6) 6 Units °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board,, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. Pin Definitions Pin # 1 2 3 4 5 Name VDD GND IN+ IN– XREF OUT Description Supply Voltage. Provides power to the IC. Ground. Common ground reference for input and output circuits. Non-Inverting Input. Connect to VDD to enable output. FAN3111C Inverting Input. Connect to GND to enable output. FAN3111E External Reference Voltage. Reference for input thresholds, 2V to 5V. Gate Drive Output. Held low unless required inputs are present. Output Logic with Dual-Input Configuration IN+ 0 0 (7) (7) IN− 0 1 (7) OUT 0 0 1 0 1 1 0 1 (7) Note: 7. Default input signal if no external connection is made. © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 2 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Block Diagrams 1 IN+ 3 100kΩ VDD 5 OUT VDD 100kΩ 100kΩ IN- 4 2 GND Figure 3. FAN3111C Simplified Block Diagram 1 VDD XREF 4 IN+ 3 100k 100k 5 OUT 2 GND Figure 4. FAN3111E Simplified Block Diagram © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 3 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VIN VXREF VOUT TL TJ TSTG ESD VDD to GND Voltage on IN to GND Voltage on XREF to GND Voltage on OUT to GND Parameter Min. -0.3 Max. 20.0 VDD + 0.3 VXREF+0.3 5.5 VDD+0.3 +260 +150 Uni t V V V V V ºC ºC ºC V FAN3111C FAN3111E FAN3111E -0.3 -0.3 -0.3 -0.3 Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -65 2000 2500 +150 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VIN VXREF TA Supply Voltage Range Input Voltage IN Parameter Min. 4.5 FAN3111C FAN3111E FAN3111E 0 0 2.0 -40 Max. 18.0 VDD VXREF 5.0 +125 Unit V V V V ºC External Reference Voltage XREF Operating Ambient Temperature © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 4 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Electrical Characteristics Unless otherwise noted, VDD = 12V, VXREF = 3.3V, TJ = -40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Supply VDD IDD Parameter Operating Range Static Supply Current Conditions Min. 4.5 Typ. Max. 18.0 Unit V µA Inputs Not Connected 5 10 Inputs (FAN3111C) VIL_C VIH_C IINL IINH VHYS_C IN Logic, Low-Voltage Threshold IN Logic, High-Voltage Threshold IN Current, Low IN Current, High Input Hysteresis Voltage IN from 0 to VDD IN from 0 to VDD -1 -175 17 30 38 55 70 175 1 %VDD %VDD µA µA %VDD Inputs (FAN3111E) VIL_E VIH_E IINL IINH VHYS_E Output ISINK ISOURCE IPK_SINK OUT Current, Mid-Voltage, Sinking(8) OUT Current, Mid-Voltage, Sourcing(8) OUT Current, Peak, Sinking(8) (8) (9) IN Logic, Low-Voltage Threshold IN Logic, High-Voltage Threshold IN Current, Low IN Current, High Input Hysteresis Voltage IN from 0 to VXREF IN from 0 to VXREF 25 30 50 60 50 1 20 %VXREF %VXREF µA µA %VXREF -1 -50 OUT at VDD/2, CLOAD = 47nF, f = 1KHz OUT at VDD/2, CLOAD = 47nF, f = 1KHz CLOAD = 47nF, f = 1KHz CLOAD = 47nF, f = 1KHz CLOAD = 470pF CLOAD = 470pF FAN3111C: 0 - 12VIN, 1V/ns Slew Rate FAN3111E: 0 - 3.3VIN, 1V/ns Slew Rate 1.1 -0.9 1.4 -1.4 9 8 18 17 A A A A ns ns IPK_SOURCE OUT Current, Peak, Sourcing tRISE tFALL Output Rise Time Output Fall Time (9) tD1, tD2 Output Prop. Delay (9) 15 30 ns IRVS Output Reverse Current Withstand(8) 250 mA Notes: 8. Not tested in production. 9. See Timing diagrams. © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 5 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Timing Diagrams 90% Output 10% VINH VINL tD1 tRISE tD2 tFALL IN Output 10% 90% IN+ VINH VINL tD1 tFALL tD2 tRISE Figure 5. Non-Inverting Waveforms Figure 6. Inverting Waveforms © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 6 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25°C, VDD = 12V, and VXREF = 3.3V unless otherwise noted. 2.5 2.0 2.5 FAN3111C IDD ( μ A) FAN3111E 2.0 1.5 1.0 Inputs Floating, Output Low Inputs Floating, Output Low IDD ( μ A) 1.5 1.0 0.5 0.0 4 6 8 10 12 14 16 18 Supply Voltage (V) 0.5 0.0 4 6 8 10 12 14 16 18 Supply Voltage (V) Figure 7. IDD (Static) vs. Supply Voltage Figure 8. IDD (Static) vs. Supply Voltage 2.0 2.0 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 0 FAN3111C FAN3111C V DD = 15V 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 FAN3111E V DD = 15V V DD = 12V V DD = 12V V DD = 8V V DD = 4.5V IIDD (mA) DD (mA) IDD (mA) V DD = 8V V DD = 4.5V 200 200 400 400 600 600 800 800 1000 1000 0 200 400 600 800 1000 Sw itching Frequency (kHz) Sw itching Frequency (kHz) Sw itching Frequency (kHz) Figure 9. IDD (No-Load) vs. Frequency Figure 10. IDD (No-Load) vs. Frequency 9 8 7 6 FAN3111C V DD = 15V V DD = 12V IDD (mA) 9 8 7 6 5 4 3 2 1 0 FAN3111E V DD = 15 V V DD = 12 V IDD (mA) 5 4 3 2 1 0 0 V DD = 8V V DD = 4.5V V DD = 8 V V DD = 4.5 V 200 400 600 800 1000 0 200 400 600 800 1000 Sw itching Fre quency ( kHz ) Sw itching Fre quency (kHz ) Figure 11. IDD (470pF Load) vs. Frequency Figure 12. IDD (470pF Load) vs. Frequency © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 7 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25°C, VDD = 12V, and VXREF = 3.3V unless otherwise noted. 3 3 FAN3111C 2 IDD ( μA) 2 FAN3111E Inputs Floating, Output Low IDD ( μ A) 1 1 Inputs Floating, Output Low 0 -50 -25 0 25 50 75 Tem p erature ( °C) 100 125 0 -50 -25 0 25 50 75 Tem perature (°C) 100 125 Figure 13. IDD (Static) vs. Temperature Figure 14. IDD (Static) vs. Temperature 10 9 Input Thresholds (V) 2.5 FAN3111C Input Thresholds (V) FAN3111E 2.0 V IH 8 7 6 5 4 3 2 1 0 4 6 8 V IH 1.5 V IL 1.0 V IL 0.5 10 12 14 Supply Voltage (V) 16 18 2.5 3.0 3.5 4.0 XREF (V) 4.5 5.0 Figure 15. Input Thresholds vs. Supply Voltage Figure 16. Input Threshold vs. XREF Voltage 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 4 DD) 7.0 FAN3111C VIH FAN3111C Input Thresholds (V) 6.5 6.0 5.5 5.0 4.5 4.0 -50 V IL V IH Input Thresholds (% of V V IL 6 8 10 12 14 16 18 -25 0 Supply Voltage (V) 25 50 75 Tem perature (°C) 100 125 Figure 17. Input Thresholds % vs. Supply Voltage Figure 18. Input Threshold vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 8 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25°C, VDD = 12V, and VXREF = 3.3V unless otherwise noted. 2.0 70 Propagation Delays (ns) Input Thresholds (V) 1.8 1.6 1.4 1.2 1.0 0.8 -50 FAN3111E 60 50 40 30 20 10 0 4 FAN3111C Inverting Input V IH IN rise to OUT fall V IL IN fall to OUT 6 8 10 12 14 Supply Voltage (V) 16 18 -25 0 25 50 75 Tem perature (°C) 100 125 Figure 19. Input Threshold vs. Temperature Figure 20. Propagation Delay vs. Supply Voltage 80 90 Propagation Delays (ns) FAN3111C Non-Inverting Input Propagation Delays (ns) 70 60 50 40 30 20 10 0 4 80 70 60 50 40 30 20 10 0 4 FAN3111E IN Fall to OUT Fall IN Fall to OUT Fall IN Ris e t o OUT Ris e 6 8 10 12 14 16 18 IN Rise to OUT Rise 6 8 10 12 14 16 18 Supply Voltage (V) Supply Voltage (V) Figure 21. Propagation Delay vs. Supply Voltage Figure 22. Propagation Delay vs. Supply Voltage 24 20 Propagation Delays (ns) Propagation Delays (ns) 22 20 18 16 14 12 10 -50 FAN3111C Non-Inverting Input FAN3111E 18 16 14 12 10 8 -50 IN Rise to OUT Rise IN Fall to OUT Fall IN Fall to OUT Fall IN Rise to OUT Rise -25 0 25 50 75 Tem perature (°C) 100 125 -25 0 25 50 75 Tem perature (°C) 100 125 Figure 23. Propagation Delay vs. Temperature Figure 24. Propagation Delays vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 9 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25°C, VDD = 12V, and VXREF = 3.3V unless otherwise noted. 22 Propagation Delays (ns) FAN3111C Inverting Input Fall Time (ns) IN Rise to OUT Fall 120 100 80 60 40 20 CL = 2.2nF CL = 1.0nF CL = 470pF CL = 4.7nF 20 18 16 14 12 10 -50 IN Fall to OUT Rise -25 0 25 50 75 100 125 0 0 5 10 Supply Voltage (V) 15 20 Tem perature (°C) Figure 25. Propagation Delays vs. Temperature Figure 26. Fall Time vs. Supply Voltage 140 12 CL = 4.7nF Rise and Fall Times (ns) 120 CL = 470pF 11 Rise Tim e 10 9 8 7 -50 Fall Tim e Rise Time (ns) 100 80 60 40 20 0 0 5 10 Supp ly V oltag e ( V ) 15 20 CL = 2.2nF CL = 1.0nF CL = 470pF -25 0 25 50 75 Tem perature (°C) 100 125 Figure 27. Rise Time vs. Supply Voltage Figure 28. Rise and Fall Time vs. Temperature Figure 29. Rise and Fall Waveforms (470pF) Figure 30. Quasi-Static Source Current (VDD=12V) © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 10 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Performance Characteristics Typical characteristics are provided at 25°C, VDD = 12V, and VXREF = 3.3V unless otherwise noted. Figure 31. Quasi-Static Sink Current (VDD=12V) Figure 32. Quasi-Static Source Current (VDD=8V) VDD 4.7µF Ceramic 470µF Al. El. FAN3111 IOUT 1µF Ceramic Current Probe LECROY AP015 IN 1kHz VOUT CLOAD 47nF Figure 33. Quasi-Static Sink Current (VDD=8V) Figure 34. Quasi-Static IOUT / VOUT Test Circuit © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 11 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Applications Information The FAN3111 offers CMOS- or logic-level-compatible input thresholds. In the FAN3111C, the logic input thresholds are dependent on the VDD level and, with VDD of 12V, the logic rising-edge threshold is approximately 55% of VDD and the input falling-edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input-voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver. In the FAN3111E, the input thresholds are dependent on the VXREF voltage that typically is chosen between 2V and 5V. This range of VXREF allows compatibility with TTL and other logic levels up to 5V by connecting the XREF pin to the same source as the logic circuit that drives the FAN3111E input stage. The logic rising edge threshold is approximately 50% of VXREF and the input falling-edge threshold is approximately 30% of VXREF. The TTL-like input configuration offers a hysteresis voltage of approximately 20% of VXREF. Figure 36 illustrates startup operation as VDD increases from 0 to 12V with the output commanded to the high level (IN+ tied to VDD, IN- tied to GND). This configuration might not be suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would attempt to turn the P-channel MOSFET on with low VDD levels. VDD OUT FAN3111C OUT @ 5 V/Div VDD @ 5 V/Div t = 200 us/Div Figure 36. Startup Operation as VDD Increases Figure 37 illustrates FAN3111E startup operation with the output commanded to the low level (IN+ tied to ground) and the voltage on XREF ramped from 0 to 3.3V. VDD XREF VDD @ 5 V/Div OUT FAN3111E Startup Operation The FAN3111 internal logic is optimized to drive ground referenced N-channel MOSFETs as VDD supply voltage rises during startup operation. As VDD rises from 0V to approximately 2V, the OUT pin is held LOW by an internal resistor, regardless of the state of the input pins. When the internal circuitry becomes active at approximately 2V, the output assumes the state commanded by the inputs. Figure 35 illustrates FAN3111C startup operation with VDD increasing from 0 to 12V, with the output commanded to the low level (IN+ and IN- tied to ground). Note that OUT is held LOW to maintain an Nchannel MOSFET in the OFF state. VDD OUT @ 2 V/Div VXREF @ 2 V/Div t = 50 us/Div Figure 37. FAN3111E Startup Operation MillerDrive™ Gate Drive Technology FAN3111 drivers incorporate the MillerDrive architecture shown in Figure 38 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a wide range of supply-voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive architecture is to speed up switching by providing the highest current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. www.fairchildsemi.com 12 OUT FAN3111C OUT @ 5 V/Div VDD @ 5 V/Div t = 200 us/Div Figure 35. FAN3111C Startup Operation © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver The output-pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slower rise or fall time at the MOSFET gate is needed, a series resistor can be added.  Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be especially obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized as discussed in the following sections.   Figure 38. MillerDrive™ Output Architecture VDD Bypass Capacitor Guidelines To enable this IC to turn a power device on quickly, a local, high-frequency, bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply ≤5%. Often this is achieved with a value ≥ 20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, which have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF, mounted closest to the VDD and GND pins to carry the higher-frequency components of the current pulses. Figure 39 shows the pulsed gate-drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak-current pulses within this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD CBYP FAN3111 PWM VDS Figure 39. Current Path for MOSFET Turn-On Figure 40 shows the current path when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. Layout and Connection Guidelines The FAN3111 incorporates fast reacting input circuits, short propagation delays, and output stages capable of delivering current peaks over 1A to facilitate voltage transition times from under 10ns to over 100ns. The following layout and connection guidelines are strongly recommended: VDD CBYP FAN3111 VDS  Keep high-current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds. PWM Figure 40. Current Path for MOSFET Turn-Off © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 13 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Truth Table of Logic Operation The FAN3111 truth table indicates the operational states using the dual-input configuration. In a non-inverting driver configuration, the IN- pin should be a logic low signal. If the IN- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the IN+ pin. Table 1. FAN3111 Truth Table Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of three components; PGATE, PQUIESCENT, and PDYNAMIC: IN+ 0 0 1 1 IN0 1 0 1 OUT 0 0 1 0 Ptotal  Pgate  PDynamic (1) In the non-inverting driver configuration in Figure 41, the IN- pin is tied to ground and the input signal (PWM) is applied to the IN+ pin. The IN- pin can be connected to logic high to disable the driver and the output remains low, regardless of the state of the IN+ pin. Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gate-source voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE  QG  VGS  fsw (2) VDD IN+ INFAN3111 GND OUT PWM Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pulldown resistors, can be obtained using the graphs in Figure 11 and Figure 12 in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC  IDYNAMIC  VDD (3) Once the power dissipated in the driver is determined, the driver junction temperature rise with respect to the device lead can be evaluated using thermal equation: TJ  PTOTAL JL  TC where: TJ = driver junction temperature; θJL = thermal resistance from junction to lead; and TL = lead temperature of device in application. (4) Figure 41. Dual-Input Driver Enabled, NonInverting Configuration In the inverting driver application shown in Figure 42, the IN+ pin is tied high. Pulling the IN+ pin to GND forces the output low, regardless of the state of the IN- pin. VDD The power dissipated in a gate-drive circuit is independent of the drive-circuit resistance and is split proportionately among the resistances present in the driver, any discrete series resistor present, and the gate resistance internal to the power switching MOSFET. Power dissipated in the driver may be estimated using the following equation:   ROUT,Driver  PPKG  PTOTAL   ROUT,DRIVER  REXT  RGATE,FET  (5)   where: PPKG = power dissipated in the driver package; ROUT,DRIVER = estimated driver impedance derived from IOUT vs. VOUT waveforms; REXT = external series resistance connected between the driver output and the gate of the MOSFET; and RGATE,FET = resistance internal to the load MOSFET gate and source connections. www.fairchildsemi.com 14 IN+ PWM IN- FAN3111 GND OUT Figure 42. Dual-Input Driver Enabled, Inverting Configuration © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Typical Application Diagrams Rectified AC Input VDD 33 FAN3111 Downstream Converters Q1A Logic PWM VDD 33 FAN3111 Q1B Figure 43. PFC Boost Circuit Utilizing Distributed Drivers for Parallel Power Switches Q1A and Q1B Figure 44. Driver for Forward Converter Low-Side Switch VIN T2 Q1 T1 D1 VSEC VDD Q2 D2 PWM CC FAN3111 0.1µF Figure 45. © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 Driver for Two-Transistor, Forward-Converter Gate Transformer www.fairchildsemi.com 15 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Table 2. Related Products Part Number Gate (10) Drive (Sink/Src) Input Threshold CMOS External CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL (11) Type Logic Package FAN3111C Single 1A +1.1A / -0.9A FAN3111E FAN3100C FAN3100T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3268T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T FAN3121C FAN3121T FAN3122T FAN3122C Single 1A +1.1A / -0.9A Single 2A Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Single 9A Single 9A Single 9A Single 9A +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A Single Channel of Dual-Input/Single-Output SOT23-5, MLP6 Single Non-Inverting Channel with External Reference SOT23-5, MLP6 Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 18V Half-Bridge Driver: Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channel + Enable Single Inverting Channel + Enable Single Non-Inverting Channel + Enable Single Non-Inverting Channel + Enable SOT23-5, MLP6 SOT23-5, MLP6 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 Notes: 10. Typical currents with OUT at 6V and VDD = 12V. 11. Thresholds proportional to an externally supplied reference voltage. © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 16 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver Physical Dimensions 3.00 2.80 5 4 A SYMM C L 0.95 0.95 B 3.00 2.60 1.70 1.50 2.60 1 2 3 (0.30) 0.95 1.90 0.50 0.30 0.20 CAB 0.70 1.00 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 0.15 0.05 1.45 MAX C 0.10 C 0.22 0.08 NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE 0.25 8° 0° 0.55 0.35 0.60 REF A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 SEATING PLANE Figure 46. 5-Lead SOT-23 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 17 FAN3111 — Single 1A High-Speed, Low-Side Gate Driver © 2008 Fairchild Semiconductor Corporation FAN3111 • Rev. 1.0.2 www.fairchildsemi.com 18