FAN3214

FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers January 2011 FAN3213 / FAN3214 Dual-4A, High-Speed, Low-Side Gate Drivers Features              Industry-Standard Pinouts 4.5 to 18V Operating Range 5A Peak Sink/Source at VDD = 12V 4.3A Sink / 2.8A Source at VOUT = 6V TTL Input Thresholds Two Versions of Dual Independent Drivers: Description The FAN3213 and FAN3214 dual 4A gate drivers are designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. They are both available with TTL input thresholds. Internal circuitry provides an undervoltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET. The FAN3213/14 drivers incorporate MillerDrive™ architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3213 offers two inverting drivers and the FAN3214 offers two non-inverting drivers. Both are offered in a standard 8-pin SOIC package. - Dual Inverting (FAN3213) Dual Non-Inverting (FAN3214) Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 12ns / 9ns Typical Rise/Fall Times with 2.2nF Load Typical Propagation Delay Under 20ns Matched within 1ns to the Other Channel Double Current Capability by Paralleling Channels Standard SOIC-8 Package Rated from –40°C to +125°C Ambient Applications      Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control FAN3213 FAN3214 Figure 1. Pin Configurations Ordering Information Part Number FAN3213TMX FAN3214TMX Logic Dual Inverting Channels Dual Non-Inverting Channels Input Threshold TTL TTL Package SOIC-8 SOIC-8 Packing Method Tape & Reel Tape & Reel Quantity per Reel 2,500 2,500 © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Package Outlines Figure 2. SOIC-8 (Top View) Thermal Characteristics(1) Package 8-Pin Small Outline Integrated Circuit (SOIC) Notes: 1. 2. 3. 4. Estimates derived from thermal simulation; actual values depend on the application. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink, using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. JL(2) 38 JT(3) 29 JA(4) 87 JB(5) 41 JT(6) 2.3 Units °C/W 5. 6. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 2 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Pin Configurations FAN3213 FAN3214 Figure 3. Pin Configurations (Repeated) Pin Definitions Pin 1 2 3 2 4 7 5 (FAN3213) 5 (FAN3214) 6 7 (FAN3213) 7 (FAN3214) 8 Name NC INA GND INA INB OUTA Input to Channel A. Pin Description No Connect. This pin can be grounded or left floating. Ground. Common ground reference for input and output circuits. Input to Channel A. Input to Channel B. Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold. Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold. Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold. Supply Voltage. Provides power to the IC. Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold. Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold. No Connect. This pin can be grounded or left floating. OUTB OUTB VDD OUTA OUTA NC Output Logic FAN3213 (x=A or B) INx 0 1 (7) FAN3214 (x=A or B) INx 0(7) 1 0 (7) OUTx 0 0 1 0 OUTx 0 0 0 1 0 1(7) 1 Note: 7. Default input signal if no external connection is made. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 3 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Block Diagrams Figure 4. FAN3213 Block Diagram Figure 5. FAN3214 Block Diagram © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 4 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VIN VOUT TL TJ TSTG ESD VDD to PGND Parameter INA, INA+, INA–, INB, INB+ and INB– to GND OUTA and OUTB to GND Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 Min. -0.3 Max. 20.0 Unit V V V ºC ºC ºC kV GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 +260 -55 -65 4 1 +150 +150 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VIN TA Supply Voltage Range Parameter Input Voltage INA, INA+, INA–, INB, INB+ and INB– Operating Ambient Temperature Min. 4.5 0 -40 Max. 18.0 VDD +125 Unit V V ºC © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 5 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Electrical Characteristics Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Supply VDD IDD VON VOFF Inputs VIL_T VIH_T IIN+ IINVHYS_T Output ISINK ISOURCE IPK_SINK Parameter Operating Range Supply Current, Inputs Not Connected Turn-On Voltage Turn-Off Voltage Conditions Min. 4.5 Typ. Max. 18.0 Unit V mA V V 0.70 INA = VDD, INB = 0V INA = VDD, INB = 0V 3.5 3.3 3.9 3.7 0.95 4.3 4.1 INx Logic Low Threshold INx Logic High Threshold Non-Inverting Input Inverting Input TTL Logic Hysteresis Voltage IN from 0 to VDD IN from 0 to VDD 0.8 1.2 1.6 2.0 175.0 1.5 0.4 0.8 V V µA µA V -1.5 -175.0 0.2 OUT Current, Mid-Voltage, Sinking(8) OUT Current, Mid-Voltage, Sourcing(8) OUT Current, Peak, Sinking(8) (8) (9) OUTx at VDD/2, CLOAD=0.22µF, f=1kHz OUTx at VDD/2, CLOAD=0.22µF, f=1kHz CLOAD=0.22µF, f=1kHz CLOAD=0.22µF, f=1kHz CLOAD=2200pF CLOAD=2200pF (9) 4.3 -2.8 5 -5 12 9 9 17 2 500 20 17 29 4 A A A A ns ns ns ns mA IPK_SOURCE OUT Current, Peak, Sourcing tRISE tFALL tD1, tD2 Output Rise Time Output Fall Time (9) Output Propagation Delay, TTL Inputs 0 - 5VIN, 1V/ns Slew Rate INA=INB, OUTA and OUTB at 50% Point Propagation Matching Between Channels IRVS Output Reverse Current Withstand(8) Notes: 8. Not tested in production. 9. See Timing Diagrams of Figure 6 and Figure 7. Figure 6. Non-Inverting Timing Diagram © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 Figure 7. Inverting Timing Diagram www.fairchildsemi.com 6 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 8. IDD (Static) vs. Supply Voltage(10) Figure 9. IDD (Static) vs. Temperature(10) Figure 10. IDD (No Load) vs. Frequency Figure 11. IDD (2.2nF Load) vs. Frequency Figure 12. Input Thresholds vs. Supply Voltage Figure 13. Input Thresholds vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 7 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. UVLO Threshold vs. Temperature Figure 14. Propagation Delay vs. Supply Voltage Figure 15. Propagation Delay vs. Supply Voltage Figure 16. Propagation Delays vs. Temperature Figure 17. Propagation Delays vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 8 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 18. Fall Time vs. Supply Voltage Figure 19. Rise Time vs. Supply Voltage Figure 20. Rise and Fall Times vs. Temperature Figure 21. Rise/Fall Waveforms with 2.2nF Load Figure 22. Rise/Fall Waveforms with 10nF Load © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 9 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 23. Quasi-Static Source Current with VDD=12V(11) Figure 24. Quasi-Static Sink Current with VDD=12V(11) Figure 25. Quasi-Static Source Current with VDD=8V(11) Figure 26. Quasi-Static Sink Current with VDD=8V(11) Notes: 10. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in Figure 4 and Figure 5. 11. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the currentmeasurement loop. Test Circuit Figure 27. Quasi-Static IOUT / VOUT Test Circuit © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 10 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Applications Information Input Thresholds The FAN3213 and the FAN3214 drivers consist of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. The input thresholds meet industry-standard TTL-logic thresholds independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V should be 550ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. Figure 28. MillerDrive™ Output Architecture Under-Voltage Lockout The FAN321x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would turn the P-channel MOSFET on with VDD below 3.9V. Static Supply Current In the IDD (static) typical performance characteristics shown in Figure 8 and Figure 9, each curve is produced with both inputs floating and both outputs LOW to indicate the lowest static IDD current. For other states, additional current flows through the 100k resistors on the inputs and outputs shown in the block diagram of each part (see Figure 4 and Figure 5). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDrive™ Gate Drive Technology FAN3213 and FAN3214 gate drivers incorporate the MillerDrive™ architecture shown in Figure 28. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the HIGH or LOW rail. The purpose of the MillerDrive™ architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched ON. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. VDD Bypass Capacitor Guidelines To enable this IC to turn a device ON quickly, a local high-frequency bypass capacitor, CBYP, with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤ 5%. This is often achieved with a value ≥ 20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased, to 50-100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF mounted closest to the VDD and GND pins to carry the higherfrequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP would be twice as large as when a single channel is switching. www.fairchildsemi.com 11 © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Layout and Connection Guidelines The FAN3213 and FAN3214 gate drivers incorporate fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 4A to facilitate voltage transition times from under 10ns to over 150ns. The following layout and connection guidelines are strongly recommended:  Keep high-current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical for TTL-level logic thresholds at driver input pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100k resistors indicated on block diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input or output leads. For best results, make connections to all pins as short and direct as possible. FAN3213 and FAN3214 are pin-compatible with many other industry-standard drivers. The turn-on and turn-off current paths should be minimized, as discussed in the following section. Figure 30. Current Path for MOSFET Turn-Off Figure 29. Current Path for MOSFET Turn-On   Figure 30 shows the current path when the gate driver turns the MOSFET OFF. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized.    Figure 29 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 12 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Operational Waveforms At power-up, the driver output remains LOW until the VDD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises with VDD until steadystate VDD is reached. The non-inverting operation illustrated in Figure 31 shows that the output remains LOW until the UVLO threshold is reached, then the output is in-phase with the input. The inverting configuration of startup waveforms are shown in Figure 32. With IN+ tied to VDD and the input signal applied to IN–, the OUT pulses are inverted with respect to the input. At power-up, the inverted output remains LOW until the VDD voltage reaches the turn-on threshold, then it follows the input with inverted phase. Figure 31. Non-Inverting Startup Waveforms Figure 32. Inverting Startup Waveforms © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 13 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE = QG • VGS • fSW • n (2) where n is the number of driver channels in use (1 or 2). Dynamic Pre-Drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD • n (3) To give a numerical example, if the synchronous rectifier switches in the forward converter of Figure 33 are FDMS8660S, the datasheet gives a total gate charge of 60nC at VGS = 7V, so two devices in parallel would have 120nC gate charge. At a switching frequency of 300kHz, the total power dissipation is: PGATE = 120nC • 7V • 300kHz • 2 = 0.504W PDYNAMIC = 7.5mA • 7V • 2 = 0.011W PTOTAL = 0.515W ≈ 0.52W (5) (6) (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB = 42°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB,MAX = TJ - PTOTAL • JB TB,MAX = 120°C – 0.52W • 42°C/W = 98°C (8) (9) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ = PTOTAL • JB + TB (4) where: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 14 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Typical Application Diagrams Figure 33. High-Current Forward Converter with Synchronous Rectification Figure 34. Center-Tapped Bridge Output with Synchronous Rectifiers Vin QC QA QD QB FAN3214 PWM-A FAN3227 PWM-B PWM-C FAN3227 PWM-D SR-1 Secondary Phase Shift Controller SR-2 Figure 35. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers (Simplified) © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 15 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Table 1. Type Single 1A Single 1A Single 2A Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Single 9A Single 9A Single 9A Single 9A Related Products Part Number FAN3111C FAN3111E FAN3100C FAN3100T FAN3216T FAN3217T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3268T FAN3278T FAN3213T FAN3214T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T FAN3121C FAN3121T FAN3122T FAN3122C Gate Drive (Sink/Src) +1.1A / -0.9A +1.1A / -0.9A +2.5A / -1.8A +2.5A / -1.8A +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.5A / -1.8A +2.5A / -1.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A (12) Input Threshold CMOS External CMOS TTL TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL TTL TTL TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL (13) Logic Single Channel of Dual-Input/Single-Output Single Non-Inverting Channel with External Reference Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels Dual Non-Inverting Channels Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 20V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables 30V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables Dual Inverting Channels Dual Non-Inverting Channels Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channel + Enable Single Inverting Channel + Enable Single Non-Inverting Channel + Enable Single Non-Inverting Channel + Enable Package SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOIC8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8 SOIC8 SOIC8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 Notes: 12. Typical currents with OUTx at 6V and VDD=12V. 13. Thresholds proportional to an externally supplied reference voltage. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 16 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 36. 8-Lead Small Outline Integrated Circuit (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 17 FAN3213 / FAN3214 — Dual-4A, High-Speed, Low-Side Gate Drivers © 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 • Rev. 1.0.2 www.fairchildsemi.com 18