FAN3227_10

FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers January 2010 FAN3226 / FAN3227 / FAN3228 / FAN3229 Dual 2A High-Speed, Low-Side Gate Drivers Features Industry-Standard Pinouts 4.5 to 18V Operating Range 3A Peak Sink/Source at VDD = 12V 2.4A Sink / 1.6A Source at VOUT = 6V Choice of TTL or CMOS Input Thresholds Four Versions of Dual Independent Drivers: Description The FAN3226-29 family of dual 2A gate drivers is designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL or CMOS input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET. The FAN322X drivers incorporate MillerDrive™ architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3226 offers two inverting drivers and the FAN3227 offers two non-inverting drivers. Each device has dual independent enable pins that default to ON if not connected. In the FAN3228 and FAN3229, each channel has dual inputs of opposite polarity, which allows configuration as non-inverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled low to hold the power MOSFET off. - Dual Inverting + Enable (FAN3226) Dual Non-Inverting + Enable (FAN3227) Dual Inputs in Two Pin-Out Configurations: o o Compatible with FAN3225x (FAN3228) Compatible with TPS2814D (FAN3229) Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 12ns / 9ns Typical Rise/Fall Times with 1nF Load Typical Propagation Delay Under 20ns Matched within 1ns to the Other Channel Double Current Capability by Paralleling Channels 8-Lead 3x3mm MLP or 8-Lead SOIC Package Rated from –40°C to +125°C Ambient Applications Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control Servers Related Resources AN-6069: Application Review and Comparative Evaluation of Low-Side Gate Drivers FAN3226 FAN3227 FAN3228 FAN3229 Figure 1. Pin Configurations © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Ordering Information Part Number FAN3226CMPX FAN3226CMX FAN3226TMPX FAN3226TMX FAN3227CMPX FAN3227CMX FAN3227TMPX FAN3227TMX FAN3228CMPX FAN3228CMX FAN3228TMPX FAN3228TMX FAN3229CMPX FAN3229CMX FAN3229TMPX FAN3229TMX Dual Channels of Two-Input / One-Output Drivers, Pin Configuration 2 Dual Channels of Two-Input / One-Output Drivers, Pin Configuration 1 Dual Non-Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Logic Input Threshold CMOS TTL CMOS TTL CMOS TTL CMOS TTL Package 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 3x3mm MLP-8 SOIC-8 Packing Method Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Quantity per Reel 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 3,000 2,500 All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package Outlines Figure 2. 3x3mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View) Thermal Characteristics(1) Package 8-Lead 3x3mm Molded Leadless Package (MLP) 8-Pin Small Outline Integrated Circuit (SOIC) ΘJL (2) ΘJT (3) ΘJA (4) ΨJB (5) ΨJT (6) Units °C/W °C/W 1.6 40 68 31 43 89 3.5 43 0.8 3.0 Notes: 1. 2. 3. 4. Estimates derived from thermal simulation; actual values depend on the application. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. www.fairchildsemi.com 2 5. 6. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers FAN3226 FAN3227 FAN3228 FAN3229 Figure 4. Pin Configurations (Repeated) Pin Definitions Name ENA ENB GND INA INA+ INAINB INB+ INBOUTA OUTB Pin Description Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds for both TTL and CMOS INx threshold. Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds for both TTL and CMOS INx threshold. Ground. Common ground reference for input and output circuits. Input to Channel A. Non-Inverting Input to Channel A. Connect to VDD to enable output. Inverting Input to Channel A. Connect to GND to enable output. Input to Channel B. Non-Inverting Input to Channel B. Connect to VDD to enable output. Inverting Input to Channel B. Connect to GND to enable output. Gate Drive Output A: Held low unless required input(s) are present and VDD is above UVLO threshold. Gate Drive Output B: Held low unless required input(s) are present and VDD is above UVLO threshold. Gate Drive Output A (inverted from the input): Held low unless required input is present and VDD is above UVLO threshold. Gate Drive Output B (inverted from the input): Held low unless required input is present and VDD is above UVLO threshold. Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected to GND; NOT suitable for carrying current. Supply Voltage. Provides power to the IC. OUTA OUTB P1 VDD Output Logic FAN3226 (x=A or B) ENx INx FAN3227 (x=A or B) OUTx 0 0 1 0 ENx 0 0 1 1 (7) (7) FAN3228 and FAN3229 (x=A or B) INx+ 0 0 (7) (7) INx 0 0 (7) OUTx 0 0 0 1 INx− 0 1 1 (7) OUTx 0 0 1 0 0 0 1 1 (7) (7) 0 1 1 (7) 1 (7) 0 (7) 1 1 0 (7) 1 Note: 7. Default input signal if no external connection is made. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 3 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Block Diagrams Figure 5. FAN3226 Block Diagram Figure 6. FAN3227 Block Diagram © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 4 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Block Diagrams Figure 7. FAN3228 Block Diagram Figure 8. FAN3229 Block Diagram © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 5 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VEN VIN VOUT TL TJ TSTG ESD VDD to PGND ENA and ENB to GND Parameter Min. -0.3 Max. 20.0 Unit V V V V ºC ºC ºC kV kV GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 +260 -55 -65 Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 4 1 +150 +150 INA, INA+, INA–, INB, INB+ and INB– to GND OUTA and OUTB to GND Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VEN VIN TA Supply Voltage Range Enable Voltage ENA and ENB Parameter Min. 4.5 0 0 -40 Max. 18.0 VDD VDD +125 Unit V V V ºC Input Voltage INA, INA+, INA–, INB, INB+ and INB– Operating Ambient Temperature © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 6 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Electrical Characteristics Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Supply VDD IDD VON VOFF VINL_T VINH_T IIN+ IINVHYS_T VINL_C VINH_C IINL IINH VHYS_C VENL VENH VHYS_T RPU tD3 tD4 Parameter Operating Range Supply Current Inputs / EN Not Connected Turn-On Voltage Turn-Off Voltage (9) Conditions Min. 4.5 Typ. Max. 18.0 0.75 1.20 1.05 4.3 4.1 0.65 Unit V mA mA V V V TTL CMOS (8) INA=ENA=VDD, INB=ENB=0V INA=ENA=VDD, INB=ENB=0V 3.5 3.3 0.8 3.9 3.7 1.2 1.6 Inputs (FAN322xT) INx Logic Low Threshold INx Logic High Threshold Non-inverting Input Inverting Input TTL Logic Hysteresis Voltage (9) 2.0 175.0 1.5 V µA µA V %VDD IN from 0 to VDD IN from 0 to VDD -1.5 -175.0 0.2 30 0.4 38 55 0.8 Inputs (FAN322xC) INx Logic Low Threshold INx Logic High Threshold IN Current, Low IN Current, High CMOS Logic Hysteresis Voltage Enable Logic Low Threshold Enable Logic High Threshold TTL Logic Hysteresis Voltage Enable Pull-up Resistance (10) (10) 70 175 1 %VDD µA µA %VDD V IN from 0 to VDD IN from 0 to VDD -1 -175 17 ENABLE (FAN3226C, FAN3226T, FAN3227C, FAN3227T) EN from 5V to 0V EN from 0V to 5V 0.8 1.2 1.6 0.4 100 (12) 2.0 V V kΩ EN to Output Propagation Delay 0V to 5V EN, 1V/ns Slew Rate 0V to 5V EN, 1V/ns Slew Rate 10 10 19 18 34 32 ns ns Continued on the following page… © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 7 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Electrical Characteristics (Continued) Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Output ISINK ISOURCE IPK_SINK IPK_SOURCE tRISE tFALL tD1 tD2 tD1 tD2 tDEL.MATCH IRVS Parameter Conditions OUT at VDD/2, CLOAD=0.1µF, f=1kHz OUT at VDD/2, CLOAD=0.1µF, f=1kHz CLOAD=0.1µF, f=1kHz CLOAD=0.1µF, f=1kHz CLOAD=1000pF CLOAD=1000pF CMOS Input CMOS Input TTL Input TTL Input INA=INB, OUTA and OUTB at 50% point (10) Min. Typ. Max. Unit OUT Current, Mid-Voltage, Sinking (10) 2.4 -1.6 3 -3 12 9 7 6 10 10 15 15 19 18 1 500 22 17 30 29 34 32 2 A A A A ns ns ns OUT Current, Mid-Voltage, Sourcing OUT Current, Peak, Sinking (12) (10) (10) (10) OUT Current, Peak, Sourcing Output Rise Time Output Fall Time (12) Output Propagation Delay, CMOS (12) Inputs Output Propagation Delay, TTL (12) Inputs Propagation Matching Between Channels Output Reverse Current Withstand ns ns mA Notes: 8. Lower supply current due to inactive TTL circuitry. 9. EN inputs have TTL thresholds; refer to the ENABLE section. 10. Not tested in production. 11. See Timing Diagrams of Figure 11 and Figure 12. 12. See Timing Diagrams of Figure 9 and Figure 10. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 8 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Timing Diagrams 90% Output 10% VINH VINL tD1 t RISE tD2 t FALL Output 90% 10% VINH VINL tD1 tFALL tD2 tRISE Input Input Figure 9. Non-Inverting (EN HIGH or Floating) Figure 10. Inverting (EN HIGH or Floating) Figure 11. Non-Inverting (IN HIGH) Figure 12. Inverting (IN LOW) © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 9 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. 1.6 1.4 1.2 IDD ( mA) IDD (mA) 1.0 0.8 0.6 0.4 0.2 0.0 4 6 8 10 12 14 16 18 Supply Voltage (V) 1.6 FAN3226C, 27C 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4 TTL Input Inputs and Enables Floating, Outputs Inputs and Enables Floating, Outputs Low 6 8 10 12 14 16 18 Supply Voltage (V) (13) Figure 13. IDD (Static) vs. Supply Voltage 1.6 1.4 1.2 IDD (mA) 1.0 0.8 0.6 0.4 0.2 0.0 4 Figure 14. IDD (Static) vs. Supply Voltage (13) FAN3228C, 29C All Inputs Floating, Outputs Low 6 8 10 12 14 16 V DD - Supply Voltage (V) 18 (13) Figure 15. IDD (Static) vs. Supply Voltage Figure 16. IDD (No-Load) vs. Frequency Figure 17. IDD (No-Load) vs. Frequency © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 10 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 18. IDD (1nF Load) vs. Frequency Figure 19. IDD (1nF Load) vs. Frequency 1.6 1.4 1.2 IDD ( mA) 1.6 FAN3226C, 27C 1.4 1.2 IDD ( mA) 1.0 0.8 0.6 0.4 0.2 125 TTL Input 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 Inputs and Enables Floating, Outputs 25 50 75 Tem perature (°C) 100 Inputs and Enables Floating, Outputs -25 0 25 50 75 Tem perature (°C) 100 125 0.0 -50 Figure 20. IDD (Static) vs. Temperature 1.6 1.4 1.2 (13) Figure 21. IDD (Static) vs. Temperature (13) FAN3228C, 29C IDD (mA) 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 All Inputs Floating, Outputs Low 0 25 50 75 Tem perature (°C) 100 (13) 125 Figure 22. IDD (Static) vs. Temperature © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 11 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 23. Input Thresholds vs. Supply Voltage Figure 24. Input Thresholds vs. Supply Voltage Figure 25. Input Threshold % vs. Supply Voltage Figure 26. Input Thresholds vs. Temperature Figure 27. Input Thresholds vs. Temperature © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 12 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 28. UVLO Thresholds vs. Temperature Figure 29. UVLO Threshold vs. Temperature Figure 30. Propagation Delays vs. Supply Voltage Figure 31. Propagation Delays vs. Supply Voltage Figure 32. Propagation Delays vs. Supply Voltage Figure 33. Propagation Delays vs. Supply Voltage © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 13 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 34. Propagation Delays vs. Temperature Figure 35. Propagation Delays vs. Temperature Figure 36. Propagation Delays vs. Temperature Figure 37. Propagation Delays vs. Temperature Figure 38. Fall Time vs. Supply Voltage Figure 39. Rise Time vs. Supply Voltage © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 14 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 40. Rise and Fall Times vs. Temperature Figure 41. Rise/Fall Waveforms with 1nF Load Figure 42. Rise/Fall Waveforms with 10nF Load Figure 43. Quasi-Static Source Current with VDD=12V Figure 44. Quasi-Static Sink Current with VDD=12V © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 15 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at 25°C and VDD=12V unless otherwise noted. Figure 45. Quasi-Static Source Current with VDD=8V Figure 46. Quasi-Static Sink Current with VDD=8V Note: 13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in the block diagram. Test Circuit Figure 47. Quasi-Static IOUT / VOUT Test Circuit © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 16 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Applications Information Input Thresholds Each member of the FAN322x driver family consists of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. In the FAN3226 and FAN3227, channels A and B can be enabled or disabled independently using ENA or ENB, respectively. The EN pin has TTL thresholds for parts with either CMOS or TTL input thresholds. If ENA and ENB are not connected, an internal pull-up resistor enables the driver channels by default. If the channel A and channel B inputs and outputs are connected in parallel to increase the driver current capacity, ENA and ENB should be connected and driven together. The FAN322x family offers versions in either TTL or CMOS input thresholds. In the FAN322xT, the input thresholds meet industry-standard TTL-logic thresholds independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic high. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V should be 550ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN322xC, the logic input thresholds are dependent on the VDD level and, with VDD of 12V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver. MillerDrive™ Gate Drive Technology FAN322x gate drivers incorporate the MillerDrive™ architecture shown in Figure 48. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive™ architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications that have zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. Figure 48. MillerDrive™ Output Architecture Static Supply Current In the IDD (static) typical performance characteristics (see Figure 13 - Figure 15 and Figure 20 - Figure 22), the curve is produced with all inputs / enables floating (OUT is low) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100kΩ resistors on the inputs and outputs shown in the block diagram of each part (see Figure 5 - Figure 8). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. Under-Voltage Lockout The FAN322x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9V operational level, this circuit holds the output low, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would turn the P-channel MOSFET on with VDD below 3.9V. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 17 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local high-frequency bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%. This is often achieved with a value ≥20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF mounted closest to the VDD and GND pins to carry the higher frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP would be twice as large as when a single channel is switching. The FAN322x is compatible with many other industry-standard drivers. In single input parts with enable pins, there is an internal 100kΩ resistor tied to VDD to enable the driver by default; this should be considered in the PCB layout. The turn-on and turn-off current paths should be minimized, as discussed in the following section. Figure 49 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. Layout and Connection Guidelines The FAN3226-26 family of gate drivers incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2A to facilitate voltage transition times from under 10ns to over 150ns. The following layout and connection guidelines are strongly recommended: Keep high-current output and power ground paths separate logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds at driver inputs and enable pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100kΩ resistors indicated on block diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 18 Figure 49. Current Path for MOSFET Turn-on Figure 50 shows the current path when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. Figure 50. Current Path for MOSFET Turn-off www.fairchildsemi.com FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Truth Table of Logic Operation The FAN3228/FAN3229 truth table indicates the operational states using the dual-input configuration. In a non-inverting driver configuration, the IN- pin should be a logic low signal. If the IN- pin is connected to logic high, a disable function is realized, and the driver output remains low regardless of the state of the IN+ pin. IN+ 0 0 1 1 IN0 1 0 1 OUT 0 0 1 0 Operational Waveforms At power-up, the driver output remains low until the VDD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises with VDD until steady-state VDD is reached. The non-inverting operation illustrated in Figure 53 shows that the output remains low until the UVLO threshold is reached, the output is in-phase with the input. In the non-inverting driver configuration in Figure 51, the IN- pin is tied to ground and the input signal (PWM) is applied to IN+ pin. The IN- pin can be connected to logic high to disable the driver and the output remains low, regardless of the state of the IN+ pin. VDD IN+ INFAN3228/9 GND OUT Figure 53. Non-Inverting Startup Waveforms For the inverting configuration of Figure 52, startup waveforms are shown in Figure 54. With IN+ tied to VDD and the input signal applied to IN–, the OUT pulses are inverted with respect to the input. At power-up, the inverted output remains low until the VDD voltage reaches the turn-on threshold, then it follows the input with inverted phase. PWM Figure 51. Dual-Input Driver Enabled, Non-Inverting Configuration In the inverting driver application in Figure 52, the IN+ pin is tied high. Pulling the IN+ pin to GND forces the output low, regardless of the state of the IN- pin. Figure 52. Dual-Input Driver Enabled, Inverting Configuration Figure 54. Inverting Startup Waveforms © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 19 Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, FSW, is determined by: PGATE = QG • VGS • FSW • n (2) n is the number of driver channels in use (1 or 2). Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC • VDD • n (3) In the forward converter with synchronous rectifier shown in the typical application diagrams, the FDMS8660S is a reasonable MOSFET selection. The gate charge for each SR MOSFET would be 60nC with VGS = VDD = 7V. At a switching frequency of 500kHz, the total power dissipation is: PGATE = 60nC • 7V • 500kHz • 2 = 0.42W PDYNAMIC = 3mA • 7V • 2 = 0.042W PTOTAL = 0.46W (5) (6) (7) The SOIC-8 has a junction-to-board thermal characterization parameter of ψJB = 43°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB = TJ - PTOTAL • ψ JB TB = 120°C – 0.46W • 43°C/W = 100°C (8) (9) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming ψJB was determined for a similar thermal design (heat sinking and air flow): TJ = PTOTAL • ψJB + TB (4) For comparison, replace the SOIC-8 used in the previous example with the 3x3mm MLP package with ψJB = 3.5°C/W. The 3x3mm MLP package could operate at a PCB temperature of 118°C, while maintaining the junction temperature below 120°C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider tradeoffs between reducing overall circuit size with junction temperature reduction for increased reliability. where: = driver junction temperature TJ ψJB = (psi) thermal characterization parameter relating temperature rise to total power dissipation TB = board temperature in location defined in Note 1 under Thermal Resistance table. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 20 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Typical Application Diagrams Figure 55. Forward Converter with Synchronous Rectification Figure 56. Primary-Side Dual Driver in a Push-Pull Converter Figure 57. Phase-Shifted Full-Bridge with Two Gate Drive Transformers (Simplified) © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 21 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Table 1. Type Single 1A Single 1A Single 2A Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Single 9A Single 9A Single 9A Single 9A Related Products Part Number Gate Drive (Sink/Src) +1.1A / -0.9A +1.1A / -0.9A +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.5A / -1.8A +2.5A / -1.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A (14) Input Threshold CMOS External(15) CMOS TTL TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL TTL TTL TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL Logic Single Channel of Dual-Input/Single-Output Package SOT23-5, MLP6 FAN3111C FAN3111E FAN3100C FAN3100T FAN3216T FAN3217T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3268T FAN3278T FAN3213T FAN3214T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T FAN3121C FAN3121T FAN3122T FAN3122C Single Non-Inverting Channel with External Reference SOT23-5, MLP6 Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels Dual Non-Inverting Channels Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 20V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables 30V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables Dual Inverting Channels Dual Non-Inverting Channels Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channel + Enable Single Inverting Channel + Enable Single Non-Inverting Channel + Enable Single Non-Inverting Channel + Enable SOT23-5, MLP6 SOT23-5, MLP6 SOIC8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8 SOIC8 SOIC8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 Notes: 14. Typical currents with OUTx at 6V and VDD=12V. 15. Thresholds proportional to an externally supplied reference voltage. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 22 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Physical Dimensions 2X 0.8 MAX 2X RECOMMENDED LAND PATTERN 0.05 0.00 SEATING PLANE A. CONFORMS TO JEDEC REGISTRATION MO-229, VARIATION VEEC, DATED 11/2001 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. FILENAME: MKT-MLP08Drev2 Figure 58. 3x3mm, 8-Lead Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 23 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers Physical Dimensions (Continued) 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 59. 8-Lead, Small Outline Integrated Curcuit (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 24 FAN3226 / FAN3227 / FAN3228 / FAN3229 — Dual 2A High-Speed, Low-Side Gate Drivers © 2007 Fairchild Semiconductor Corporation FAN3226 / FAN3227 / FAN3228 / FAN3229 • Rev. 1.0.6 www.fairchildsemi.com 25