FAN3268TMX

FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver January 2011 FAN3268 2A Low-Voltage PMOS-NMOS Bridge Driver Features          4.5V to 18V Operating Range Drives High-Side PMOS and Low-Side NMOS in Motor Control or Buck Step-down Applications Inverting Channel B Biases High-Side PMOS Device Off (with internal 100kΩ Resistor) when VDD is below UVLO Threshold TTL Input Thresholds 2.4A Sink / 1.6A Source at VOUT=6V Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 8-Lead SOIC Package Rated from –40°C to +125°C Ambient Description The FAN3268 dual 2A gate driver is optimized to drive a high-side P-channel MOSFET and a low-side N-channel MOSFET in motor control applications operating from a voltage rail up to 18V. The driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. Internal circuitry provides an under-voltage lockout function that prevents the output switching devices from operating if the VDD supply voltage is below the operating level. Internal 100kΩ resistors bias the non-inverting output low and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. The FAN3268 driver incorporates MillerDrive™ architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3268 has two independent enable pins that default to on if not connected. If the enable pin for noninverting channel A is pulled low, OUTA is forced low; if the enable pin for inverting channel B is pulled low, OUTB is forced high. If an input is left unconnected, internal resistors bias the inputs such that the external MOSFETs are off. Applications    Motor Control with PMOS / NMOS Half-Bridge Configuration Buck Converters with High-Side PMOS Device; 100% Duty Cycle Operation Possible Logic-Controlled Load Circuits with High-Side PMOS Switch Figure 1. Typical Motor Drive Application © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 1 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Ordering Information Part Number FAN3268TMX Logic Non-Inverting Channel and Inverting Channel + Dual Enables Input Threshold TTL Packing Method 2,500 Units on Tape & Reel Package Outline Figure 2. Pin Configuration (Top View) Thermal Characteristics(1) Package 8-Pin Small Outline Integrated Circuit (SOIC) Notes: 1. 2. 3. 4. Estimates derived from thermal simulation; actual values depend on the application. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. JL(2) 40 JT(3) 31 JA(4) 89 JB(5) 43 JT(6) 3 Units °C/W 5. 6. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 2 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Pin Definitions Pin# 1 8 3 2 4 7 5 6 Name ENA ENB GND INA INB OUTA OUTB Description Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds. Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds. Ground. Common ground reference for input and output circuits. Input to Channel A. Input to Channel B. Gate Drive Output A: Held low unless required input(s) are present and VDD is above the UVLO threshold. Gate Drive Output B (inverted from the input): Held high unless required input is present and VDD is above UVLO threshold. Supply Voltage. Provides power to the IC. VDD Output Logic FAN3268 (Channel A) ENA 0 0 1(7) 1(7) INA 0 (7) FAN3268 (Channel B) OUTA 0 0 0 1 ENB 0 0 1(7) 1(7) INB 0 (7) OUTB 1 1 1 0 1 0(7) 1 1 0(7) 1 Note: 7. Default input signal if no external connection is made. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 3 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Block Diagram VDD 100k VDD 100k ENA 1 8 ENB INA 2 7 100k 100k OUTA GND 3 UVLO 6 VDD VDD_OK 100k INB 4 100k 5 OUTB Figure 3. Block Diagram © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 4 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VEN VIN VOUT TL TJ TSTG ESD VDD to PGND ENA, ENB to GND INA, INB to GND OUTA, OUTB to GND Parameter Min. -0.3 Max. 20.0 Unit V V V V ºC ºC ºC kV kV GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 +260 -55 -65 Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 3.5 2 +150 +150 Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VEN VIN TA Supply Voltage Range Enable Voltage (ENA, ENB) Input Voltage (INA, INB) Parameter Min. 4.5 0 0 -40 Max. 18.0 VDD VDD +125 Unit V V V ºC Operating Ambient Temperature Electrical Characteristics Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol SUPPLY VDD IDD VON VOFF (8) Parameter Operating Range Supply Current Inputs / EN Not Connected Turn-On Voltage Turn-Off Voltage Conditions Min. 4.5 Typ. Max. 18.0 0.75 1.20 4.3 4.1 Unit V mA V V INA=ENA=VDD, INB=ENB=0V INA=ENA=VDD, INB=ENB=0V 3.5 3.3 3.9 3.7 INPUT VIL VIH INx Logic Low Threshold INx Logic High Threshold Logic Hysteresis Voltage 5 0.8 1.2 1.6 2.0 0.8 V V V VHYS 0.2 0.4 © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Electrical Characteristics (Continued) Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. ENABLE VENL VENH VHYS RPU Enable Logic Low Threshold Enable Logic High Threshold Logic Hysteresis Voltage (9) (9) EN from 5V to 0V EN from 0V to 5V 0.8 1.2 1.6 0.4 100 2.0 V V V kΩ Enable Pull-up Resistance OUTPUT ISINK ISOURCE IPK_SINK Out Current, Mid-Voltage, Sinking(9) Out Current, Mid-Voltage, Sourcing(9) Out Current, Peak, Sinking(9) (9) Out at VDD/2, CLOAD=0.1µF, f=1kHz Out at VDD/2, CLOAD=0.1µF, f=1kHz CLOAD=0.1µF, f=1kHz CLOAD=0.1µF, f=1kHz CLOAD=1000pF CLOAD=1000pF 0 - 5VIN, 1V/ns Slew Rate 0 - 5VIN, 1V/ns Slew Rate 7 10 2.4 -1.6 3 -3 12 9 14 19 22 17 25 34 A A A A ns ns ns ns IPK_SOURCE Out Current, Peak, Sourcing tRISE tFALL tD1 tD2 Output Rise Time(10) Output Fall Time (10) (10) (10) Propagation Delay Propagation Delay Notes: 8. EN inputs have TTL thresholds; refer to the ENABLE section. 9. Not tested in production. 10. See the Timing Diagrams of Figure 4 and Figure 5. Timing Diagrams Figure 4. Non-Inverting Figure 5. Inverting © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 6 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 6. IDD (Static) vs. Supply Voltage(11) Figure 7. IDD (No-Load) vs. Frequency Figure 8. IDD (1nF Load) vs. Frequency Figure 9. IDD (Static) vs. Temperature(11) Figure 10. Input Thresholds vs. Supply Voltage Figure 11. Input Thresholds vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 7 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 12. UVLO Threshold vs. Temperature Figure 13. Propagation Delays vs. Supply Voltage Figure 14. Propagation Delays vs. Supply Voltage Figure 15. Propagation Delays vs. Temperature Figure 16. Propagation Delays vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 8 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 17. Fall Time vs. Supply Voltage Figure 18. Rise Time vs. Supply Voltage Figure 19. Rise and Fall Times vs. Temperature Figure 20. Rise/Fall Waveforms with 1nF Load Figure 21. Rise/Fall Waveforms with 10nF Load © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 9 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 22. Quasi-Static Source Current with VDD=12V Figure 23. Quasi-Static Sink Current with VDD=12V Figure 24. Quasi-Static Source Current with VDD=8V Figure 25. Quasi-Static Sink Current with VDD=8V Note: 11. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in the block diagram in Figure 3. Test Circuit Figure 26. Quasi-Static IOUT / VOUT Test Circuit © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 10 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Applications Information Input Thresholds The FAN3268 driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. The input thresholds meet industry-standard TTL-logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic high. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V should be 550ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. Figure 27. MillerDrive™ Output Architecture Under-Voltage Lockout Internal circuitry provides an under-voltage lockout function that prevents the output switching devices from operating if the VDD supply voltage is below the operating level. When VDD is rising, but below the 3.9V operational level, internal 100k resistors bias the noninverting output low and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. After the part is active, the supply voltage must drop 0.2V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. Static Supply Current In the IDD (static) typical performance characteristics (see Figure 6), the curve is produced with all inputs / enables floating (OUT is low) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100k resistors on the inputs and outputs shown in the block diagram (see Figure 3). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDrive™ Gate Drive Technology FAN3268 gate drivers incorporate the MillerDrive™ architecture shown in 0. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between one and two thirds VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive™ architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local high-frequency bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%. This is often achieved with a value ≥20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF mounted closest to the VDD and GND pins to carry the higher frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP would be twice as large as when a single channel is switching. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 11 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Layout and Connection Guidelines The FAN3268 gate driver incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2A to facilitate voltage transition times from under 10ns to over 150ns. The following layout and connection guidelines are strongly recommended: Operational Waveforms Figure 28 shows startup waveforms for non-inverting channel A. At power-up, the driver output for channel A remains low until the VDD voltage reaches the UVLO turnon threshold, then OUTA operates in-phase with INA.  Keep high-current output and power ground paths separate from logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds at driver inputs and enable pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100k resistors indicated on block diagrams command a low output (channel A) or a high output (channel B). In noisy environments, it may be necessary to tie inputs or enables of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized.   Figure 28. Non-Inverting Startup Waveforms Figure 29 illustrates startup waveforms for inverting channel B. At power-up, the driver output for channel B is tied to VDD through an internal 100kΩ resistor until the VDD voltage reaches the UVLO turn-on threshold, then OUTB operates out of phase with INB.   Figure 29. Inverting Startup Waveforms © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 12 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL=PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE=QG • VGS • fSW • n (2) where n is the number of driver channels in use (1 or 2). Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC=IDYNAMIC • VDD • n (3) As an example of a power dissipation calculation, consider an application driving two MOSFETs with a gate charge of 60nC with VGS=VDD=7V. At a switching frequency of 500kHz, the total power dissipation is: PGATE=60nC • 7V • 500kHz • 2=0.42W PDYNAMIC=3mA • 7V • 2=0.042W PTOTAL=0.46W (5) (6) (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB=43°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB=TJ - PTOTAL • JB TB=120°C – 0.46W • 43°C/W=100°C (8) (9) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ =PTOTAL • JB + TB (4) where: TJ =driver junction temperature JB =(psi) thermal characterization parameter relating temperature rise to total power dissipation TB =board temperature in location defined in Note 1 under Thermal Resistance table. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 13 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Table 1. Part Number FAN3111C FAN3111E FAN3100C FAN3100T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3268T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T FAN3121C FAN3121T FAN3122T FAN3122C Related Products Type Gate Drive(12) (Sink/Src) +1.1A / -0.9A +1.1A / -0.9A +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A Input Threshold CMOS External CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL (13) Logic Package Single 1A Single 1A Single 2A Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Single 9A Single 9A Single 9A Single 9A Single Channel of Dual-Input/Single-Output Single Non-Inverting Channel with External Reference Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channel + Enable Single Inverting Channel + Enable Single Non-Inverting Channel + Enable Single Non-Inverting Channel + Enable SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 Notes: 12. Typical currents with OUT at 6V and VDD=12V. 13. Thresholds proportional to an externally supplied reference voltage. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 14 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 30. 8-Lead Small Outline Integrated Circuit (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 15 FAN3268 —2A Low-Voltage PMOS-NMOS Bridge Driver © 2009 Fairchild Semiconductor Corporation FAN3268 • Rev. 1.0.1 www.fairchildsemi.com 16