FAN3278TMX

FAN3278 — 30V PMOS-NMOS Bridge Driver January 2011 FAN3278 30V PMOS-NMOS Bridge Driver Features             8V to 27V Optimum Operating Range Drives High-Side PMOS and Low-Side NMOS in Motor Control or Buck Step-Down Applications Output Drive-Voltage Magnitude Limited: < 13V for VDD up to 30V Biases Each Load Device OFF with a 100kΩ Resistor when VDD Below Operating Level Low-Voltage TTL Input Thresholds Peak Gate Drives at 12V: +1.5A Sink, -1.0A Source Internal Resistors Hold Driver Off When No Inputs Present 8-Lead SOIC Package Rated from –40°C to +125°C Ambient Description The FAN3278 dual 1.5A gate driver is optimized to drive a high-side P-channel MOSFET and a low-side N-channel MOSFET in motor control applications operating from a voltage rail up to 27V. Internal circuitry limits the voltage applied to the gates of the external MOSFETs to 13V maximum. The driver has TTL input thresholds and provides buffer and level translation from logic inputs. Internal circuitry prevents the output switching devices from operating if the VDD supply voltage is below the IC operation level. Internal 100kΩ resistors bias the non-inverting output LOW and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. The FAN3278 driver incorporates MOSFET devices for the final output stage, providing high current throughout the MOSFET turn-on / turn-off transition to minimize switching loss. The internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8V to 27V. The FAN3278 can be driven from a voltage rail of less than 8V; however, its gate drive current is reduced. The FAN3278 has two independent ENABLE pins that default to ON if not connected. If the ENABLE pin for non-inverting channel A is pulled LOW, OUTA is forced LOW. If the ENABLE pin for inverting channel B is pulled LOW, OUTB is forced HIGH. If an input is left unconnected, internal resistors bias the inputs such that the external MOSFETs are OFF. Applications Motor Control with PMOS / NMOS Half-Bridge Configuration Buck Converters with High-Side PMOS Device; 100% Duty Cycle Operation Possible Logic-Controlled Load Circuits with High-Side PMOS Switch Figure 1. Typical Application © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com FAN3278 — 30V PMOS-NMOS Bridge Driver Ordering Information Part Number FAN3278TMX Logic Non-Inverting Channel and Inverting Channel with Dual Enable Input Threshold TTL Packing Method 2,500 Units on Tape & Reel Figure 2. Typical 3-Phase Blower Motor Drive Application © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 2 FAN3278 — 30V PMOS-NMOS Bridge Driver Pin Configuration Figure 3. Pin Configuration (Top View) Thermal Characteristics(1) Package 8-Pin Small-Outline Integrated Circuit (SOIC) JL(2) 40 JT(3) 31 JA(4) 89 JB(5) 43 JT(6) 3 Unit °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. Pin Definitions Pin# 1 8 3 2 4 7 5 6 Name ENA ENB GND INA INB OUTA OUTB Description Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds. Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds. Ground. Common ground reference for input and output circuits. Input to Channel A. Input to Channel B. Gate Drive Output A: Held LOW unless required input is present and VDD is above the internal voltage threshold where the IC is functional. Gate Drive Output B (inverted from the input). Held HIGH unless the required input is present and VDD is above the internal voltage threshold where the IC is functional. Supply Voltage. Provides power to the IC. VDD © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 3 FAN3278 — 30V PMOS-NMOS Bridge Driver Output Logic FAN3278 (Channel A) ENA 0 0 1(7) 1(7) INA 0 (7) FAN3278 (Channel B) OUTA 0 0 0 1 ENB 0 0 1(7) 1(7) INB 0 (7) OUTB 1 1 1 0 1 0(7) 1 1 0(7) 1 Note: 7. Default input signal if no external connection is made. Block Diagram VDD 100k VDD 100k ENA 1 13V 8 ENB INA 2 100k LS Predriver 100k 7 OUTA Low-Side Drive Regulator GND 3 6 VDD High-Side Drive Regulator HS Predriver 100k INB 4 100k 5 OUTB VDD - 13V Figure 4. Block Diagram © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 4 FAN3278 — 30V PMOS-NMOS Bridge Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VEN VIN VOUT TL TJ TSTG ESD VDD to PGND ENA, ENB to GND INA, INB to GND OUTA, OUTB to GND Parameter Min. -0.3 Max. 30.0 Unit V V V V ºC ºC ºC kV GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 GND - 0.3 VDD + 0.3 +260 -55 -65 Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 2 2 +150 +150 Lead Soldering Temperature (10 Seconds) Junction Temperature Storage Temperature Electrostatic Discharge Protection Level Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD VEN VIN TA Supply Voltage Range Enable Voltage (ENA, ENB) Input Voltage (INA, INB) Parameter Min. 8 0 0 -40 Max. 27 VDD VDD +125 Unit V V V °C Operating Ambient Temperature © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 5 FAN3278 — 30V PMOS-NMOS Bridge Driver Electrical Characteristics Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device (Isink) and negative out of the device (Isource). Symbol Supply VDD IDD VON VHYS Input(9) VIL VIH VHYS Enable VENL VENH VHYS RPU tD1 tD2 tD2 tD1 Parameter Optimum Operating Range(8) Supply Current Inputs / EN Not Connected Turn-On Voltage(9) Turn-On / Turn-Off Hysteresis (9) Conditions Min. 8 Typ. Max. 27 Unit V mA V mV 1.3 INA=ENA=VDD, INB=ENB=0V INA=ENA=VDD, INB=ENB=0V 3.8 10 2.0 INx Logic Low Threshold INx Logic High Threshold Logic Hysteresis Voltage 0.8 1.1 1.80 2.25 1.0 V V V 0.4 0.7 Enable Logic Low Threshold Enable Logic High Threshold Logic Hysteresis Voltage (10) EN from 5V to 0V EN from 0V to 5V 0.8 1.2 1.60 0.7 100 2.25 V V V kΩ 70 60 70 60 ns ns ns ns Enable Pull-Up Resistance Propagation A Delay, EN Rising (11) (11) 0 - 5VIN, 1V/ns Slew Rate 0 – 5VIN, 1V/ns Slew Rate 0 - 5VIN, 1V/ns Slew Rate 0 – 5VIN, 1V/ns Slew Rate 44 33 39 29 Propagation A Delay, EN Falling Propagation B Delay, EN Rising (11) (11) Propagation B Delay, EN Falling Continued on the following page… Timing Diagrams 90% Output 10% Input V INH or VINL Enable tD1 tRISE tD2 tFALL Figure 5. Non-Inverting Figure 6. Inverting © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 6 FAN3278 — 30V PMOS-NMOS Bridge Driver Electrical Characteristics (Continued) Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device (Isink) and negative out of the device (Isource). Symbol Output IPK_OFF IPK_ON IOFF ION VOUTA VOUTB VOUTA VOUTB Parameter OUT Current, Peak, Turn-Off(10) OUT Current, Peak, Turn-On (10) Conditions CLOAD=0.1µF, f=1kHz CLOAD=0.1µF, f=1kHz OUT at VDD, CLOAD=0.1µF, f=1kHz OUT at VDD/2, CLOAD=0.1µF, f=1kHz VDD=27V, INA=“HI” VDD=27V, INA=“HI” VDD=10V, INB=“HI” VDD=10V, INB=“HI” VDD=6V, CLOAD=0.1µF (10) Min. Typ. Max. 1.5 -1.0 1.0 -0.5 11 11 13 13 Unit A A A A V V V V Ω Ω Ω Ω OUT Current, Mid-Voltage, Turn-Off(10 OUT Current, Mid-Voltage, Turn-On(10) OUTA Drive Voltage OUTB Drive Voltage, VDD – VOUTB OUTA Drive Voltage OUTB Drive Voltage, VDD – VOUTB 6.5 6.5 7.0 7.0 4.2 10.3 6.8 13.7 17 8 21 8 45 35 500 30 15 30 15 70 60 RO_A_SINK OUTA Sink Impedance (Turn-Off)(10) RO_A_SRC OUTA Source Impedance (Turn-On) RO_B_SINK OUTB Sink Impedance (Turn-On) (11) (10) (10) VDD=6V, CLOAD=0.1µF VDD=6V, CLOAD=0.1µF VDD=6V, CLOAD=0.1µF CLOAD=1000pF to GND CLOAD=1000pF to GND CLOAD=1000pF to VDD CLOAD=1000pF to VDD RO_B_SRC OUTB Source Impedance (Turn-Off) tON,N tOFF,N tON,P tOFF,P tD1 tD2 IRVS Output A Rise Time Output A Fall Time(11) Output B Fall Time (11) (11) (11) (11) ns ns ns ns ns ns mA Output B Rise Time Output Propagation Delay On Output Propagation Delay Off 0 - 5VIN, 1V/ns Slew Rate 0 - 5VIN, 1V/ns Slew Rate (10) Output Reverse Current Withstand Notes: 8. The internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8V to 27V. The FAN3278 can be driven from a voltage rail of less than 8V; however, with reduced gate drive current. 9. EN inputs have near-TTL thresholds (refer to the ENABLE section). 10. Not tested in production. 11. See the Timing Diagrams of Figure 5 and Figure 6. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 7 FAN3278 — 30V PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 7. IDD (Static) vs. Supply Voltage(12) Figure 8. IDD (Static) vs. Temperature(12) Figure 9. IDD (No Load) vs. Frequency Figure 10. IDD (1nF Load) vs. Frequency Figure 11. Input Thresholds vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 8 FAN3278 — 30V PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12V unless otherwise noted. Figure 12. Propagation Delays vs. Temperature Figure 13. Propagation Delays vs. Temperature Figure 14. Rise and Fall Times vs. Temperature Figure 15. Rise and Fall Times vs. Temperature Figure 16. Gate Drive Voltage vs. Temperature Figure 17. Gate Drive Voltage vs. Temperature Note: 12. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static IDD increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 4. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 9 FAN3278 — 30V PMOS-NMOS Bridge Driver Applications Information Input Thresholds The FAN3278 driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. The input thresholds meet industrystandard TTL-logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6V/µs or faster, so a rise time from 0 to 3.3V should be 550ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input inadvertently. Static Supply Current In the IDD (static) typical performance characteristics (see Figure 7 and Figure 8), the curve is produced with all inputs / enables floating (OUTA is LOW, OUTB is HIGH) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100k resistors on the inputs and outputs, shown in the block diagram (see Figure 4). In these cases, the static IDD current is the value obtained from the curves plus this additional current. Figure 18. Non-Inverting Startup Waveforms Figure 19 illustrates startup waveforms for inverting channel B. At power-up, the driver output for channel B is tied to VDD through an internal 100kΩ resistor until VDD reaches the voltage where the device starts operating, then OUTB operates out of phase with INB. Gate Drive Regulator FAN3278 incorporates internal regulators to regulate the gate drive voltage. The output pin slew rate is determined by this gate drive voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time is needed at the MOSFET gate. Startup Operation The FAN3278 startup logic is optimized to drive a groundreferenced N-channel MOSFET with channel A and a VDD-referenced P-channel MOSFET with channel B. The optimum operating voltage of the FAN3278 is 8V to 27V. It has an internal “watchdog” circuit that provides a loose UVLO turn-on voltage (VON) of approximately 3.8V with a small hysteresis of about 10mV. However, it is recommended that VDD is greater than 4.75V in all application circuits. When the VDD supply voltage is below the level needed to operate the internal circuitry, the outputs are biased to hold the external MOSFETs in OFF state. Internal 100kΩ resistors bias the non-inverting output LOW and the inverting output to VDD to keep the external MOSFETs off during startup intervals when input control signals may not be present. Figure 18 shows startup waveforms for non-inverting channel A. At power-up, the driver output for channel A remains LOW until VDD reaches the voltage where the device starts operating, then OUTA operates in-phase with INA. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 10 Figure 19. Inverting Startup Waveforms It is possible, during startup, before VDD has reached approximately 4.5V, that the output pulse width may take a few switching cycles to reach the full duty-cycle of the input pulse. This is due to internal propagation delays affecting the operation with higher switching frequency (e.g. >100kHz) and slow VDD ramp-up (e.g. 4.75V is not possible, the use of ENABLES to actively hold the outputs LOW until VDD > 4.75V assures the driver output pulse width follows the input from 4.75V up to 28V. www.fairchildsemi.com FAN3278 — 30V PMOS-NMOS Bridge Driver VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local high-frequency bypass capacitor, CBYP, with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10µF to 47µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%. This is often achieved with a value ≥20 times the equivalent load capacitance CEQV, defined as QGATE/VDD. Ceramic capacitors of 0.1µF to 1µF or larger are common choices, as are dielectrics, such as X5R and X7R, with stable temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10nF, mounted closest to the VDD and GND pins to carry the higher-frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP can be twice as large as when a single channel is switching. best results, make connections to all pins as short and direct as possible.  The turn-on and turn-off current paths should be minimized, as discussed above. Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL=PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET with a specified gate-source voltage, VGS, with gate charge, QG, at switching frequency, fSW, is determined by: PGATE=QG • VGS • fSW (2) This needs to be calculated for each P-channel and Nchannel MOSFET where the QG is likely to be different. Dynamic Pre-drive / Shoot-through Current: Power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (NoLoad) vs. Frequency” graphs in Figure 9 to determine the current IDYNAMIC drawn from VDD under actual operating conditions. PDYNAMIC=IDYNAMIC • VDD (3) Layout and Connection Guidelines The FAN3278 gate driver incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 1.5A to facilitate fast voltage transition times. The following layout and connection guidelines are strongly recommended:  Keep high-current output and power ground paths separate from logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds at driver inputs and enable pins. Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while minimizing the loop area that can couple EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100k resistors indicated on block diagrams command a low output on channel A and a high output on channel B. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output mistriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For 11  Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ =PTOTAL • JB + TB (4)  where: TJ =driver junction temperature JB =(psi) thermal characterization parameter relating temperature rise to total power dissipation TB =board temperature in location defined in Note 1 under Thermal Resistance table. As an example of a power dissipation calculation, consider an application driving two MOSFETs (one Pchannel and one N-channel, both with a gate charge of 60nC each) with VGS=VDD=12V. At a switching frequency of 200kHz, the total power dissipation is: PGATE=60nC • 12V • 200kHz • 2=0.288W PDYNAMIC=1.65mA • 12V =0.020W PTOTAL=0.308W (5) (6) (7)  © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com FAN3278 — 30V PMOS-NMOS Bridge Driver The SOIC-8 package has a junction-to-board thermal characterization parameter of JB=43°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must not exceed the absolute maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB=TJ - PTOTAL • JB TB=120°C – 0.308W • 43°C/W=107°C (8) (9) Test Circuit Figure 20. Quasi-Static IOUT / VOUT Test Circuit Differences between FAN3278 and FAN3268 FAN3278 and FAN3268 are pin-compatible to each other and are designed to drive one P-Channel and one N-channel MOSFET in applications such as battery-powered compact fan / pump DC motor drives. However, there are key differences, highlighted in Table 1. Table 1. Differences between FAN3278 and FAN3268 FAN3278 Supply Voltage Gate Drive Regulator 27V Operating Maximum 30V Absolute Maximum FAN3268 18V Operating Maximum 20V Absolute Maximum Yes, since the maximum operating VDD can No gate drive regulator is needed. The be as high as 27V, the gate voltage to the gate drive voltage is VDD and the external MOSFETs is limited to about 13V. FAN3268 switches rail-to-rail. The optimum operating range is 8V to 27V. After the IC turns on at about 3.8V, the 4.1V is the UVLO turn-off voltage output tracks VDD up to the regulated which is the minimum operating voltage rail of about 11~13V. Below 8V of VDD, the FAN3278 operates, but (a) slower voltage. and (b) with limited gate drive voltage until it reaches around 8V. The IC starts operating approximately at 3.8V which acts as a loose UVLO threshold. It incorporates a “smart startup” feature where the outputs are held OFF before the IC starts operating. Standard MOS-based output structure with gate drive clamp. Optimized for P-channel: The turn-OFF (1.5 A) is stronger than turn-ON (1.0A). Has the tight UVLO threshold of 4.5V on / 4.1V off. Incorporates “smart startup” (outputs held OFF before IC is fully operational at the UVLO threshold). Compound MillerDrive™ architecture in the final output stage to provide a more efficient gate drive current during the Miller plateau stage of the turnon/turn-off switching transition. P-channel turn-ON (2.4A) is stronger than turn-OFF (1.6A). Minimum Operating Voltage Startup Output Gate Drive Architecture OUTB Gate Drive Current Strength © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 12 FAN3278 — 30V PMOS-NMOS Bridge Driver Table 2. Related Products Part Number Type Gate Input Drive(13) Threshold (Sink / Src) +1.1A / -0.9A +1.1A / -0.9A +2.5A / -1.8A +2.5A / -1.8A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +2.4A / -1.6A +1.4A / -1.0A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +4.3A / -2.8A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A +9.7A / -7.1A CMOS External (14) Logic Single Channel of Dual-Input/Single-Output Single Non-Inverting Channel with External Reference Single Channel of Two-Input/One-Output Single Channel of Two-Input/One-Output Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.1 Dual Channels of Two-Input/One-Output, Pin Config.2 Dual Channels of Two-Input/One-Output, Pin Config.2 Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables 30V Non-Inverting (NMOS) and Inverting (PMOS) + Dual Enable Dual Inverting Channels + Dual Enable Dual Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Non-Inverting Channels + Dual Enable Dual Channels of Two-Input/One-Output Dual Channels of Two-Input/One-Output Single Inverting Channel + Enable Single Inverting Channel + Enable Single Non-Inverting Channel + Enable Single Non-Inverting Channel + Enable Package SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOT23-5, MLP6 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8 SOIC8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 SOIC8, MLP8 FAN3111C Single 1A FAN3111E Single 1A FAN3100C Single 2A FAN3100T FAN3226C FAN3226T FAN3227C FAN3227T FAN3228C FAN3228T FAN3229C FAN3229T FAN3268T FAN3278T FAN3223C FAN3223T FAN3224C FAN3224T FAN3225C FAN3225T Single 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 2A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A Dual 4A CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL TTL TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL FAN3121C Single 9A FAN3121T FAN3122T Single 9A Single 9A FAN3122C Single 9A Notes: 13. Typical currents with OUT at 6V and VDD=12V. 14. Thresholds proportional to an externally supplied reference voltage. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 13 FAN3278 — 30V PMOS-NMOS Bridge Driver Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 21. 8-Lead, Small-Outline Integrated Circuit (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 14 FAN3278 — 30V PMOS-NMOS Bridge Driver © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 www.fairchildsemi.com 15