FAN3850AUC19X

FAN3850A — Microphone Pre-Amplifier with Digital Output July 2011 FAN3850A Microphone Pre-Amplifier with Digital Output Features ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Optimized for Mobile Handset and Notebook PC Microphone Applications Accepts Input from Electret Condenser Microphones (ECM) Pulse Density Modulation (PDM) Output Standard 5-Wire Digital Interface 16dB and 19dB Gain Versions Available(1) Low Input Capacitance, High PSR, 20kHz Pre-Amplifier Low-Power 1.5μA Sleep Mode Typical 470μA Supply Current SNR of 62/61dB(A) for 16/19dB Gain Respectively Total Harmonic Distortion 0.02% Input Clock Frequency Range of 1-4MHz Integrated Low Drop-Out Regulator (LDO) Small 1.26mm x 0.86mm 6-Ball WLCSP Package Description The FAN3850A integrates a pre-amplifier, LDO, and ADC that converts Electret Condenser Microphone (ECM) outputs to digital Pulse Density Modulation (PDM) data streams. The pre-amplifier accepts analog signals from the ECM and drives an over-sampled sigma delta Analog-to-Digital Converter (ADC) and outputs PDM data. The PDM digital audio has the advantage of noise rejection and easy interface to mobile handset processors. The FAN3850A features an integrated LDO and is powered from the system supply rails up to 3.63V, with low power consumption of only 0.85mW and less than 20 W in Power-Down Mode. Applications ƒ ƒ ƒ ƒ Electret Condenser Microphones with Digital Output Mobile Handset Headset Accessories Personal Computer (PC) . Ordering Information Part Number Operating Temperature Range -30°C to +85°C -30°C to +85°C Package Packing Method 3000 Units on Tape & Reel 3000 Units on Tape & Reel FAN3850AUC16X FAN3850AUC19X 6 Ball, Wafer-Level Chip-Scale Package (WLCSP) 6-Ball, Wafer-Level Chip-Scale Package (WLCSP) Note: 1. Alternate gain options are possible. Please contact Fairchild. © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com FAN3850A — Microphone Pre-Amplifier with Digital Output Block Diagram VDD LDO Sleep Mode Ctrl INPUT Pre-Amp 6' ADC CLOCK DATA SELECT GND Figure 1. Block Diagram Pin Configuration Figure 2. Pin Assignments Pin Definitions Pin# A1 B1 C1 A2 B2 C2 Name CLOCK GND DATA SELECT INPUT VDD Type Input Input Output Input Input Input Clock Input Ground Pin PDM Output – 1 Bit ADC Description Rising or Falling Clock Edge Select Microphone Input Device Power Pin © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 2 FAN3850A — Microphone Pre-Amplifier with Digital Output Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VIO ESD DC Supply Voltage Analog and Digital I/O Parameter Min. -0.3 -0.3 ±7 ±300 Max. 4.0 VCC+0.3 Unit V V kV V Human Body Model, JESD22-A114, All Pins Except Microphone Input Human Body Model, JESD22-A114 – Microphone Input Note: 2. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic discharges. Appropriate precautions must be taken during handling and storage of this device to prevent exposure to ESD. Reliability Information Symbol TJ TSTG TRFLW 4JA Parameter Junction Temperature Storage Temperature Range Peak Reflow Temperature Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air Min. -65 Typ. Max. +150 +125 +260 Unit °C °C °C °C/W 90 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA VDD tRF-CLK Parameter Operating Temperature Range Supply Voltage Range Clock Rise and Fall Time Min. -30 1.64 Typ. 1.80 Max. +85 3.63 10 Unit °C V ns © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 3 FAN3850A — Microphone Pre-Amplifier with Digital Output Device Specific Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol SNR eN VIN Parameter Signal-to-Noise Ratio fIN=1kHz (1Pa), A-Weighted Total Input RMS Noise(4) 20Hz to 20kHz, A-Weighted Maximum Input Signal fIN=1kHz, THD+N < 10%, Level=0V FAN3850AUC16X Min. Typ. 62 5.74 6.80 448 FAN3850AUC19X Min. Typ. 61 4.45 5.30 317 Max. Max. Unit dB(A) μVRMS mVPP Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB (SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol VDD IDD ISLEEP Parameter Supply Voltage Range Supply Current Sleep Mode Current Condition INPUT=AC Coupled to GND, CLOCK=On, No Load fCLK=GND INPUT=AC Coupled to GND, Test Signal on VDD=217Hz Square Wave and Broadband Noise(3), Both 100mVP-P INPUT=94dBSPL (1Pa) (6) Min. 1.64 Typ. 1.80 470 1.5 Max. 3.63 Unit V A 8.0 A PSR Power Supply Rejection(4) -74 dBFS INNOM THD Nominal Sensitivity (5) -26 0.02 0.2 1.0 5.0 0.2 >100 0.3 1.5 VDD+0.3 0.35*VDD 0.65*VDD 0.20 1.0 5.0 10.0 dBFS % Total Harmonic Distortion fIN=1kHz, INPUT=-26dBFS 50Hz ” fIN ” 1kHz, INPUT=-20dBFS fIN=1kHz, INPUT=-5dBFS fIN=1kHz, INPUT=0dBFS THD+N THD and Noise(4) % CIN RIN VIL VIH VOL VOH VOUT Input Capacitance Input Resistance (7) INPUT INPUT pF G V V V V dBSPL (7) CLOCK & SELECT Input Logic LOW Level CLOCK & SELECT Input Logic HIGH Level Data Output Logic LOW Level Data Output Logic HIGH Level Acoustic Overload Point (7) THD < 10% 120 Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 4 FAN3850A — Microphone Pre-Amplifier with Digital Output Electrical Characteristics (Continued) Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), and fCLK=2.4MHz. Duty Cycle=50% and CMIC=15pF. Symbol tA tB tA tB fCLK CLKdc tWAKEUP tFALLASLEEP CLOAD Parameter Time from CLOCK Transition to Data becoming Valid Time from CLOCK Transition to Data becoming HIGH-Z Time from CLOCK Transition to Data becoming Valid Time from CLOCK Transition to Data becoming HIGH-Z Input CLOCK Frequency CLOCK Duty Cycle Wake-Up Time (9) (10) (4) (8) Condition On Falling Edge of CLOCK, SELECT=GND, CLOAD=15pF On Rising Edge of CLOCK, SELECT=GND, CLOAD=15pF On Rising Edge of CLOCK, SELECT=VDD, CLOAD=15pF On Falling Edge of CLOCK, SELECT=VDD, CLOAD=15pF Active Mode fCLK=2.4MHz fCLK=2.4MHz Min. 18 0 18 0 1.0 40 0 Typ. 43 5 56 5 2.4 50 0.35 0.01 Max. Unit ns 16 ns ns 16 4.0 60 2.00 1.00 100 ns MHz % ms ms pF Fall-Asleep Time Load Capacitance on Data Notes: 3. Pseudo-random noise with triangular probability density function. Bandwidth up to 10MHz. 4. Guaranteed by characterization. 5. Assuming that 120dB(SPL) is mapped to 0dBFS. 6. Assuming an input of -45dBV 7. Guaranteed by design. 8. All parameters are tested at 2.4MHz. Frequency range guaranteed by characterization. 9. Device wakes up when fCLK • 300kHz. 10. Device falls asleep when fCLK ” 70kHz. Figure 3. Interface Timing © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 5 FAN3850A — Microphone Pre-Amplifier with Digital Output Typical Performance Characteristics Unless otherwise specified, all limits are guaranteed for TA=25°C, VDD=1.8V, VIN=94dB(SPL), fCLK=2.4MHz, and duty cycle=50%. Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 % Noise Noise(A) Signal -20 m Fo(0)= -26.15 dBFS THD = 81.95 dB SNR = 60.88 dBc(A) SINAD = 56.87 dB ENOB = 13.50 N = 2097152 pts Blackman Window -40 -60 Amplitude [dBFS] -80 p Integrated Noise = -87.03 dBFS(A) -100 p Spur = -101.34 dBFS, SFDR = 75.19 dBc m Fo(1)= -110.28 dBFS m Fo(2)= -116.40 dBFS -120 m Fo(3)= -120.45 dBFS m Fo(4)= -125.03 dBFS -140 -160 10 1 10 2 10 3 10 4 10 5 10 6 Frequency [Hz] Filename: fan3850a-1-BD92M-20110125T122914.dat Figure 4. Noise vs. Frequency Figure 5. THD, SINDA, and SNR vs. Input Amplitude © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 6 FAN3850A — Microphone Pre-Amplifier with Digital Output Typical Performance Characteristics (Continued) Figure 6. THD, SINAD, and SNR vs. Output Level 4 Temp ( C) 40 30 20 10 0 10 20 25 30 40 50 60 70 80 85 Del ta (dB) 0.1971 0.1644 0.1260 0.0954 0.0657 0.0359 0.0139 0.0000 0.0097 0.0344 0.0514 0.0739 0.0998 0.1183 0.1271 3 2 Gain (dB) 1 0 1 2 3 4 40 30 20 10 0 10 20 30 40 50 60 70 80 Junction Temperature Tj C Figure 7. Gain vs. Temperature (Nominal Temperature= 25°C) © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 7 FAN3850A — Microphone Pre-Amplifier with Digital Output Applications Information VDD Audio Output SPEAKER CLOCK INPUT PreAmp ADC DATA SELECT CLK SDI SDO L/R Serial Port Low Pass Filter Noise Shaper Decimation Interpolation Applications Software Figure 8. Mono Microphone Application Circuit VDD Audio Output SPEAKER CLOCK INPUT PreAmp ADC DATA SELECT CLK SDI SDO L/R Serial Port Low Pass Filter Noise Shaper VDD Decimation Interpolation CLOCK INPUT Applications Software PreAmp ADC DATA SELECT Figure 9. Stereo Microphone Application Circuit © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 8 FAN3850A — Microphone Pre-Amplifier with Digital Output Applications Information (Continued) Diaphragm Airgap Electret INPUT Backplate FAN3850A VDD CLOCK DATA SELECT GND Figure 10. MIC Element Drawing A 0.1μF decoupling capacitor is required for VDD. It can be located inside the microphone or on the PCB very close to the VDD pin. Due to high input impedance, care should be taken to remove all flux used during the reflow soldering process. A 100 resistance is recommended on the clock output of the device driving the FAN3850A to minimize ringing and improve signal integrity. For optimal PSR, route a trace to the VDD pin. Do not place a VDD plane under the device. © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 9 FAN3850A — Microphone Pre-Amplifier with Digital Output Physical Dimensions 0.03 C F E A B A1 0.485 PIN A1 AREA D 0.03 C TOP VIEW (Ø0.220) SOLDER MASK RECOMMENDED LAND PATTERN (NSMD) 0.570 (Ø0.120) CU PAD 2X 2X 0.06 C 0.01 C 0.300 0.254 E 0.197±0.013 0.080±0.010 C SEATING D PLANE SIDE VIEWS NOTES: 0.005 0.570 C B A 1 2 (X) +/-0.018 BOTTOM VIEW F (Y) +/-0.018 Ø0.120±0.010 6X CAB A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. DATUM C, THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE TYPICAL HEIGHT IS 273 MICRONS ±23 MICRONS (254-300 MICRONS). F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILENAME: UC006AHrev3. 0.485 Figure 11. 6-Ball, Wafer-Level Chip-Scale Package (WLCSP) FAN3850A External Product Dimensions Product ID All options Ball Composition: SN97.5-Ag2.5 Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent version. Package specifications do not expand Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel specifications. http://www.fairchildsemi.com/packaging/. D 1.260mm E 0.860mm X 0.145mm Y 0.145mm © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 10 FAN3850A — Microphone Pre-Amplifier with Digital Output © 2010 Fairchild Semiconductor Corporation FAN3850A • Rev. 3.0.6 www.fairchildsemi.com 11