FAN4800_10

FAN4800 — Low Startup Current PFC/PWM Controller Combinations November 2010 FAN4800 Low Startup Current PFC/PWM Controller Combinations Features Low Startup Current (100µA Typical) Low Operating Current (2.5mA Typical) Low Total Harmonic Distortion, High Power Factor Pin-Compatible Upgrade for the ML4800 Average Current, Continuous or Discontinuous Boost, Leading-Edge PFC Slew Rate Enhanced Transconductance Error Amplifier for Ultra-Fast PFC Response Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM Reduction of Ripple Current in the Storage Capacitor between the PFC and PWM Sections PWM Configurable for Current Mode or Voltage Mode Additional Folded-Back Current Limit for PWM Section 20V BiCMOS Process VIN OK Guaranteed Turn-on PWM at 2.25V VCC OVP Comparator, Low-Power Detect Comparator Current-Fed Gain Modulator for Improved Noise Immunity Brownout Control, Over-Voltage Protection, UVLO, Soft-Start, and Reference OK Available in16-DIP Package Description The FAN4800 is a controller for power-factor-corrected, switched-mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower-cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC-1000-3-2 specifications. Intended as a BiCMOS version of the industry-standard ML4800, the FAN4800 includes circuits for the implementation of leading-edge, average-current, boost-type power factor correction and a trailing-edge Pulse Width Modulator (PWM). A gate driver with 1A capabilities minimizes the need for external driver circuits. Low-power requirements improve efficiency and reduce component costs. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. The FAN4800 includes a folded-back current limit for the PWM section to provide short-circuit protection. Applications Desktop PC Power Supply Internet Server Power Supply Uninterruptible Power Supply (UPS) Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power 16-PDIP Ordering Information Part Number FAN4800IN FAN4800IN_G Operating Temperature Range -40°C to +125°C -40°C to +125°C Package 16-PDIP 16-PDIP Packing Method Rail Rail Marking Code FAN4800 FAN4800 © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com FAN4800 — Low Startup Current PFC/PWM Controller Combinations Block Diagram 16 1 13 VCC 7.5V REFERENCE VEAO VFB IEAO POWER FACTOR CORRECTOR VCC 17.9V 0.5V -1V VCC OVP 2.78V TRI-FAULT S R PFC OVP VREF 14 15 0.3V 2.5V IAC VRMS ISENSE RAMP1 GAIN MODULATOR Low Power Detector 3.5k Q PFC OUT 2 4 3 7 3.5k PFC CMP PFC ILIMIT S R Q 12 OSCILLATOR CLK RAMP2 350 DUTY CYCLE LIMIT PWM DUTY 8 PFC OUT PWM OUT PWM CMP 6 VDC VCC 20μA 5 SS 350 VFB 2.25V VIN OK VREF DC ILIMIT PULSE WIDTH MODULATOR 0.9V SS CMP S 1.0V DC ILIMIT GND Q S R VCC UVLO FAN4800 Rev.02 PWM OUT Q 11 R 10 9 Figure 1. Internal Block Diagram © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 2 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Pin Configuration 1 IEAO VEAO 16 2 IAC VFB 15 3 ISENSE VREF 14 4 VRMS VCC 13 5 SS PFC OUT 12 6 VDC PWM OUT 11 7 RAMP1 GND 10 8 RAMP2 DC ILIMIT 9 FAN4800 Rev.03 Figure 2. Pin Configuration (Top View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name IEAO IAC ISENSE VRMS SS VDC RAMP1 (RtCt) RAMP2 (PWM RAMP) DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO Description PFC transconductance current error amplifier output PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft-start capacitor PWM voltage feedback input Oscillator timing node; timing set by RT, CT In current mode, this pin functions as the current-sense input. In voltage mode, it is the PWM input from the PFC output (feed forward ramp). PWM current-limit comparator input Ground PWM driver output PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 3 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IEAO VISENSE IREF IAC IPFC_OUT IPWM_OUT TJ TSTG TA TL θJA Parameter Positive Supply Voltage PFC Transconductance Current Error Amplifier Output ISENSE Voltage Voltage on Any Other Pin IREF Current IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy per Cycle Junction Temperature Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering,10 Seconds) Thermal Resistance Min. 0 -3.0 GND-0.3 Max. 20 5.5 0.7 VCC+0.3 10 1 1 1 1.5 +150 Unit V V V V mA mA A A µJ °C °C °C °C °C/W -65 -40 +150 +125 +260 80 © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 4 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3KΩ, CT = 470pF, and TA = -40°C to 125°C. Symbol VFB gm1 Vref(PFC) Ib(VEAO) VEAO(H) VEAO(L) Isink(V) Isource(V) GV PSRR1 Parameter Input Voltage Range(1) Transconductance Feedback Reference Voltage Input Bias Current(2) Output High-Voltage Output Low-Voltage Sink Current Source Current Open-Loop Gain(1)(3) Power Supply Rejection Input Voltage Range(1) Transconductance Input Offset Voltage Input Bias Current(1) TA = 25°C Ratio(1) TA = 25°C Condition Min. 0 50 2.45 -1.00 5.8 Typ. Max. 6 Unit V µmho V mA V VOLTAGE ERROR AMPLIFIER 70 2.50 -0.05 6.0 0.1 90 2.55 0.4 -20 V µA µA dB dB TA = 25°C, VFB = 3V, VEAO = 6.0V TA = 25°C, VFB = 1.5V VEAO = 1.5V 11V < VCC < 16.5V 30 50 50 -35 40 60 60 CURRENT ERROR AMPLIFIER VIEAO gm2 Voffset Ibeao IEAO(H) IEAO(L) Isink(I) Isource(I) Gi PSRR2 -1.5 50 85 0.7 100 25 -1 4.00 4.25 1.0 ISENSE = +0.5, IEAO = 4.0V ISENSE = -0.5, IEAO = 1.5V Ratio(1) 11V < VCC < 16.5V TA = 25°C TA = 25°C TA = 25°C TA = 25°C TA = 25°C VFB = VFault Detect LOW to VFB = Open. 470pF from VFB to GND 0.4 35 60 60 -65 75 70 75 1.2 -35 V µmho mV µA V V µA µA dB dB Output High-Voltage Output Low-Voltage Sink Current Source Current Open-Loop Gain(1) Power Supply Rejection PFC OVP COMPARATOR Vovp HY(ovp) Threshold Voltage Hysteresis 2.70 230 2.78 2.90 350 V mV LOW-POWER DETECT COMPARATOR Vth(lp) VCC_OVP Threshold Voltage 0.15 0.30 0.40 V VCC OVP COMPARATOR Threshold Voltage 17.5 1.40 17.9 1.50 18.5 1.65 V V HY(VCC_OVP) Hysteresis TRI-FAULT DETECT td(F) F(L) Time to Fault Detect HIGH(1) Fault Detect LOW 2 0.5 4 0.6 ms V © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 5 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3kΩ, CT = 470pF, and TA = -40°C to 125°C. Symbol Vth(cs) Vth(cs)-Vgm td(pfc_off) Vth(DC) td(pwm_off) Vth(OK) HY(OK) Parameter Threshold Voltage (PFC ILIMIT VTH – Gain Modulator Output) Delay to Output(1) Threshold Voltage Delay to Output(1) Condition Min. -1.10 5 Typ. -1.00 100 250 Max. -0.90 Unit V mV ns PFC ILIMIT COMPARATOR DC ILIMIT COMPARATOR 0.95 1.00 250 2.10 0.8 IAC = 100μA, VRMS = 0, VFB = 1V, TA = 25°C Gain(3) G3 G4 BW Vo(gm) Band Width(1) Output Voltage = 3.5kΩ x (ISENSE – IOFFSET) Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation (1) (1) (1) 1.05 V ns VIN OK COMPARATOR Threshold Voltage Hysteresis 2.45 1.0 1.2 V V GAIN MODULATOR G1 G2 0.70 1.80 0.90 0.25 0.84 2.00 1.00 0.32 10 0.80 1.00 1.20 0.95 2.20 Gain(3) 1.10 0.40 MHz V IAC = 100μA, VRMS = 1.1V, VFB = 1V, TA = 25°C IAC = 150μA, VRMS = 1.8V, VFB = 1V, TA = 25°C IAC = 300μA, VRMS = 3.3V, VFB = 1V, TA = 25°C IAC = 100μA IAC = 250μA, VRMS = 1.1V, VFB = 2V, TA = 25°C TA = 25°C 11V < VCC < 16.5V Line, Temp OSCILLATOR fosc1 Δfosc1 Δfosc2 fosc2 Vramp tdead Idis REFERENCE Vref1 ΔVref1 ΔVref2 ΔVref4 Vref2 ΔVref5 TA = 25°C, I(VREF) = 1mA 11V < VCC < 16.5V 0mA < I(VREF) < 7mA Line, Load, Temperature TJ = 125°C, 1000 hours 7.35 5 7.4 7.5 10 10 0.4 7.65 25 7.6 25 20 V mV mV % V mV 68 1 2 66 2.75 685 VRAMP2 = 0V, VRAMP1 = 2.5V 6.5 15.0 84 81 kHz % % kHz V ns mA Long Term Stability © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 6 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = -40°C to 125°C. Symbol PFC Dmin. Dmax. RON(low)1 RON(low)2 Vol1 RON(high)1 RON(high)2 tr(pfc) PWM D RON(low)3 RON(low)4 Vol2 RON(high)3 RON(high)4 tr(pwm) PWM(ls) SUPPLY Ist Iop Vth(start) Vth(hys) Parameter Minimum Duty Cycle Maximum Duty Cycle Output Low Rdson Output Low Voltage(1) Output High Rdson Rise/Fall Time(1) Condition VIEAO > 4.0V VIEAO < 1.2V IOUT = -20mA at TA = 25°C IOUT = -100mA at TA = 25°C IOUT = -10mA, VCC = 9V, TA = 25°C IOUT = 20mA at TA = 25°C IOUT = 100mA at TA = 25°C CL = 1000pF Min. Typ. Max. 0 Unit % % Ω Ω V Ω Ω ns 92 95 15 15 0.4 15 15 50 0.8 20 20 Duty Cycle Range Output Low Rdson Output Low Voltage Output High Rdson Rise/Fall Time PWM Comparator Level Shift Startup Current Operating Current Under-Voltage Lockout Threshold Under-Voltage Lockout Hysteresis VCC = 12V, CL = 0pF 14V, CL = 0pF IOUT = -20mA at TA = 25°C IOUT = -100mA at TA = 25°C IOUT = -10mA, VCC = 9V, TA = 25°C IOUT = 20mA at TA = 25°C IOUT = 100mA at TA = 25°C CL = 1000pF(1) 0-42 0-47 0-49 15 15 % Ω Ω V Ω Ω ns V µA mA V V 0.4 15 15 50 0.6 0.9 100 2.5 12.74 2.80 13.00 3.00 0.8 20 20 1.2 200 7.0 13.26 3.20 Notes: 1. This parameter, although guaranteed by design, is not 100% production tested. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K × 5.375V; K = (ISENSE – IOFFSET) × [IAC × (VEAO – 0.625)] -1; VEAO (MAX.) = 6V. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 7 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Typical Performance Characteristics 100 Transconductance ( mho) 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 VFB (V) 90 80 70 60 50 40 30 20 10 0 -10 -0.8 -0.6 -0.4 -0.2 0.0 0.2 ISENSE (V) 0.4 0.6 0.8 Transconductance ( mho) 126 119 112 105 98 91 84 77 70 63 56 Figure 3. Voltage Error Amplifier (gmv) Transconductance Figure 4. Current Error Amplifier (gmi) Transconductance Variable Gain Block Constant (K) 0.40 0.35 0.30 0.25 Gain 0.20 0.15 0.10 0.05 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRMS (V) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRMS (V) Figure 5. Gain Modulator Transfer Characteristic (K) Figure 6. Gain vs. VRMS K= IGAINMOD − IOFFSET mV −1 I AC × (6 − 0.625) (1) Gain = ISENSE − IOFFSET I AC (2) © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 8 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Functional Description The FAN4800 consists of an average-current controlled, continuous boost Power Factor Correction (PFC) frontend and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in either current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This proprietary leading/trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features are built into the FAN4800. These include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty-cycle limiting, and under-voltage lockout (UVLO). One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC rms. The second condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver, satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. To prevent ripple, which necessarily appears at the output of boost circuit (typically about 10VAC on a 385VDC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC section to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage. Since the boost converter in the FAN4800 PFC is current averaging, no slope compensation is required. Power Factor Correction Power Factor Correction treats a nonlinear load like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e., they cause significant current harmonics of the power line frequency to appear at the input). If the input current drawn by such a supply (or any nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it appears resistive to the supply. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, that device must be prevented from loading the line except in proportion to the instantaneous line voltage. To accomplish this, the PFC section of the FAN4800 uses a boost mode DC-DC converter. The input to the converter is the full-wave, rectified, AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line the frequency) from zero volts to a peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. 1. PFC Section 1.1 Gain Modulator Figure 1 shows a block diagram of the PFC section of the FAN4800. The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS2 (except at unusually low values of VRMS, where special gain contouring takes over to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K and is illustrated in Figure 5. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 9 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variation in VEAO. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is: IGAINMOD = I AC × VEAO V 2 RMS ×1 V The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin. 1.4 Cycle-By-Cycle Current Limiter and Selecting RS (3) As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is ever less than -1V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. RS is the sensing resistor of the PFC boost converter. During the steady state, line input current x RS equals IGAINMOD x 3.5K. Since the maximum output voltage of the gain modulator is IGAINMOD maximum x 3.5k = 0.8V during the steady state, RS x line input current is limited to below 0.8V as well. Therefore, to choose RS, use the following equation: RS = 0.8V × VINPEAK 2 × LineInput Power More precisely, the output current of the gain modulator is given by: IGAINMOD = K × (VEAO − 0.625) × I AC (4) where K is in units of V -1. The output current of the gain modulator is limited around 228.57µA and the maximum output voltage of the gain modulator is limited to 228.57µA x 3.5K = 0.8V. This 0.8V also determines the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD – IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60µA. (5) 1.2 Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC is also a current mirror input and requires current input. Selecting a proper resistor RAC provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. RAC = VIN peak x 7.9K. For example, if the minimum line voltage is 80VAC, the RAC = 80 x 1.414 x 7.9K = 894kΩ. For example, if the minimum input voltage is 80VAC and the maximum input RMS power is 200Watt, RS = (0.8V x 80V x 1.414) / (2 x 200) = 0.226Ω. 1.5 PFC OVP In the FAN4800, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the high-voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.78V, the PFC output driver is shut down. The PWM section continues to operate. The OVP comparator has 280mV of hysteresis and the PFC does not restart until the voltage at VFB drops below 2.50V. VCC OVP can also serve as a redundant PFC OVP protection. VCC OVP threshold is 17.9V with 1.5V hysteresis. 1.3 Current Error Amplifier, IEAO The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 10 FAN4800 — Low Startup Current PFC/PWM Controller Combinations VEAO VFB 16 IEAO 1 POWER FACTOR CORRECTOR VCC 17.9V 0.5V -1V VCC OVP 2.78V TRI-FAULT S R PFC OVP 13 VCC 7.5V REFERENCE VREF 14 15 0.3V 2.5V IAC VRMS ISENSE RAMP1 GAIN MODULATOR Low Power Detector 3.5k Q PFC OUT 2 4 3 7 3.5k PFC CMP PFC ILIMIT S R Q 12 OSCILLATOR CLK FAN4800 Rev.02 Figure 7. PFC Section Block Diagram 1.6 Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 8 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from 0V, it creates a differentiated voltage on IEAO, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. The voltage loop gain(s) is given by: = ≈ ΔVOUT ΔVFB ΔV × × EAO ΔVEAO ΔVOUT ΔVFB PIN × 2.5V V 2OUTDC × ΔVEAO × S × CDC × GMV × ZC (6) where: ZC: GMV: PIN: Compensation network for the voltage loop. Transconductance of VEAO . Average PFC input power. V2OUTDC: PFC boost output voltage (typical designed value is 380V). CDC: PFC boost output capacitor. 1.7 PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier (VEAO); stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency half that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the FAN4800’s voltage error amplifier (VEAO) has a specially shaped non-linearity, so that under steady-state operating conditions, the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions causes the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier increases significantly, as shown in the Figure 4. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with conventional linear gain characteristics. 1.8 PFC Current Loop The compensation of the current amplifier (IEAO) is similar to that of the voltage error amplifier (VEAO) with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least ten times that of the voltage amplifier to prevent interaction with the voltage loop. It should also be limited to less than one sixth of the switching frequency, e.g., 16.7kHz for a 100kHz switching frequency. The current loop gain(s) is given by: = ΔVISENSE ΔDOFF ΔIEAO × × ΔDOFF ΔIEAO ΔVISENSE ≈ VOUTDC × RS × GMI × ZCI S × L × 2.5V (7) © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 11 FAN4800 — Low Startup Current PFC/PWM Controller Combinations where: ZCI: GMI: Compensation network for the current loop. Transconductance of IEAO. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100Ω and 50Ω because IOFFSET x RS can generate an offset voltage of IEAO. Selecting an RFILTER equal to 50Ω keeps the offset of the IEAO less than 5mV. Design the pole of ISENSE filter at fpfc/6, one sixth of the PFC switching frequency, so the boost inductor can be reduced six times without disturbing the stability. The capacitor of the ISENSE filter, CFILTER, is approximately 283nF. VBIAS VOUTDC: PFC boost output voltage (typical designed value is 380V). The equation uses the worstcase condition to calculate the ZCI. RS: 2.5V: L: Sensing resistor of the boost converter. Amplitude of the PFC leading modulation ramp. Boost inductor. A modest degree of gain contouring is applied to the transfer characteristic of the current error amplifier to increase its response speed to current-loop perturbations. However, the boost inductor is usually the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in Figure 8. Vref RBIAS VCC 0.22μF Ceramic 15V Zener FAN4800 GND FAN4800 Rev.03 PFC Output VEAO VFB 2.5V 3.5k 2 4 3 IAC VRMS ISENSE Gain Modulator 3.5k 16 IEAO 1 Figure 9. External Component Connection to VCC 1.9 Oscillator (RAMP1) The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: PFC CMP fO S C = 1 tR A M P + tD E A D 15 (8) FAN4800 Rev.02 The dead time of the oscillator is derived from the following equation: Figure 8. Compensation Network Connection for the Voltage and Current Error Amplifiers There is an RC filter between RS and ISENSE pin. There are two reasons to add a filter at the ISENSE pin: 1) Protection: During startup or in-rush current conditions, there is a large voltage across RS, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2) To reduce L, the boost inductor: The ISENSE filter also can reduce the boost inductor value since the ISENSE filter behaves like an integrator before the ISENSE pin, which is the input of the current error amplifier, IEAO. ⎛V -1.00 ⎞ tRAMP = CT × RT × ln ⎜ REF ⎟ VREF -3.75 ⎠ ⎝ (9) at VREF = 7.5V and tRAMP = CT x RT x 0.55. The dead time of the oscillator may be determined using: t DEAD = 2.75V × CT = 227 × CT 12.11mA (10) The dead time is so small (tRAMP>>tDEAD) that the operating frequency can typically be approximated by: fOSC = 1 tRAMP (11) © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 12 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 1.10 Example For the application circuit shown in Figures 12 and 13, with the oscillator running at: fOSC = 100kHz = 1 tRAMP cycle current, it also softly discharges the voltage of the soft-start capacitor. It limits the PWM duty cycle mode and the power dissipation is reduced during the deadshort condition. 2.3 VIN OK Comparator The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on VFB is less than its nominal 2.25V. Once the voltage reaches 2.25V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. 2.4 PWM Control (RAMP2) When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage, representing the current in the primary of the PWM’s output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP2 is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2) that have a minimum value of 0V and a peak value of approximately 5V. In voltage mode, feed forward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage. 2.5 Soft-Start (SS) PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 20mA supplies the charging current for the capacitor and startup of the PWM begins at 0.9V. Startup delay can be programmed by the following equation: CSS = tDELAY × 20μA 0.9V (12) solving for CT x RT yields 1.96 x 10-4. CT is 390pF and RT is 51.1kΩ, selecting standard components values. The dead time of the oscillator adds to the maximum PWM duty cycle (it is an input to the duty cycle limiter). With zero oscillator dead time, the maximum PWM duty cycle is typically 47%. Take care not to make CT too large, which could extend the maximum duty cycle beyond 50%. This can be accomplished by using no greater than a 390pF capacitor for CT. 2. PWM Section 2.1 Pulse Width Modulator (PWM) The operation of the PWM section of the FAN4800 is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage. it is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycleby-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage-mode operation and certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC is compared. Under these conditions, the use of voltage feed-forward from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the DC ILIMIT input is used for output stage over-current protection. No voltage error amplifier is included in the PWM stage of the FAN4800, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input that allows VDC to command a 0% duty cycle for input voltages below typical 0.9V. 2.2 PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. When the DC ILIMIT triggers the cycle-by- (13) where CSS is the required soft-start capacitance and the tDELAY is the desired startup delay. It is important that the time constant of the PWM softstart allows the PFC time to generate sufficient output power for the PWM section. The PWM startup delay should be at least 5ms. Solving for the minimum value of CSS: CSS = 5ms × 20μA = 111nF 0.9V (14) Use caution when using this minimum soft-start capacitance value because it can cause premature charging of the SS capacitor and activation of the PWM section if VFB is in the hysteresis band of the VIN OK comparator at startup. The magnitude of VFB at startup is related both to line voltage and nominal PFC output voltage. Typically, a 1.0µF soft-start capacitor allows time for VFB and PFCOUT to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 13 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 2.6 Generating VCC After turning on the FAN4800 at 13V, the operating voltage can vary from 10V to 17.9V. The threshold voltage of the VCC OVP comparator is 17.9V and its hysteresis is 1.5V. When VCC reaches 17.9V, PFC OUT is LOW, and the PWM section is not disturbed. There are two ways to generate VCC: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800 system. The bootstrap winding can be either taped from the PFC boost choke or from the transformer of the DC-to-DC stage. The ratio of the bootstrap’s winding transformer should be set between 18V and 15V. A filter network is recommended between VCC (pin 13) and bootstrap winding. The resistor of the filter can be set as: RFILTER × IVCC ≈ 2V , = 2.5A (typ.) 2.8 Leading/Trailing Modulation Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. Figure 10 shows a typical trailing-edge control scheme. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch. Figure 11 shows a leading-edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and Switch 2 (SW2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using the leading-edge modulation method. IVCC = IOP + (QPFCFET +QPWMFET ) × fSW IOP (15) If VCC goes beyond 17.9V, the PFC gate (pin 12) drive goes LOW and the PWM gate drive (pin 11) remains working. The resistor’s value must be chosen to meet the operating current requirement of the FAN4800 itself (5mA, maximum) in addition to the current required by the two gate driver outputs. 2.7 Example To obtain a desired VBIAS voltage of 18V, a VCC of 15V, and the FAN4800 driving a total gate charge of 90nC at 100kHz (e.g. one IRF840 MOSFET and two IRF820 MOSFET), the gate driver current required is: IGATEDRIVE = 100kHz × 90nC = 9mA VBIAS − VCC ICC + IG 18V − 15V 5mA + 9mA (16) RBIAS = = (17) Choose RBIAS = 214Ω (18) Bypass the FAN4800 locally with a 1.0μF ceramic capacitor. In most applications, an electrolytic capacitor of between 47μF and 220μF is also required across the part both for filtering and as a part of the startup bootstrap circuitry. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 14 FAN4800 — Low Startup Current PFC/PWM Controller Combinations L1 I1 + VIN DC SW2 I2 I3 I4 RL RAMP C1 SW1 VEAO REF EA U3 VEAO CMP RAMP U1 R D U2 Q CLK DFF Q TIME OSC CLK U4 TIME FAN4800 Rev.02 Figure 10. Typical Trailing-Edge Control Scheme L1 I1 + VIN DC SW2 I2 I3 I4 RL RAMP C1 SW1 VEAO U3 EA REF RAMP VEAO CMP R U1 D U2 Q CLK DFF Q TIME OSC CLK U4 TIME FAN4800 Rev.02 Figure 11. Typical Leading-Edge Control Scheme © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 15 F1 3.15A BR1 4A, 600V KBL06 R2A 453k R27 75k D9 MBRS 140 C25 0.1uF D5 RGF1J R28 240 T1B C12 10uF 35V D11B MBR2545CT R7B 178k L2 D11A MBR2545CT D7 MMBZ5245B R30 4.7k C4 10nF R1A 500k Q1 FQPF9N50 C5 100uF 450V R7A 178k R17 33 Q2 FQPF 6N50 L1 D2 1N5406 D1 ISL9R460P2 D3 RGF1J VDC / +380V Q1G NOTE : Q2G AC INPUT C1 85 TO 265Vac 0.68uF L1; PREMIER MAGNETICS TDS-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 ISENSE R2B 453k R1B 500k R3 110k C30 330uF 25V R21 22 FAN4800 — Low Startup Current PFC/PWM Controller Combinations © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 12V 12V, 100W C24 1uF C21 2200uF 25V Typical Application Circuit R5D R5C 1.2 R5B 1.2 R5A 1.2 1.2 C3 0.1uF C2 0.47uF R4 15.4k T2 Q3 FQPF6N50 D6 RGF1J R6 41.7k R10 6.2k R15 3 R20A 2.2 T1A R19 220 R9 1.1k 16 Q4 MMBT3904 R20B 2.2 C20 1uF R14 33 Q3G R24 1.2k R18 220 RAMP2 / DC ILIMIT R23 1.5k U2 MOC8112 C22 4.7uF R22 8.66k Figure 12. Current-Mode Application 16 R12 71.5k U1 C7 NOT USED C6 1.5nF R31 100 FAN4800 1 IEAO VFB IAC ISENSE VRMS SS VDC PWM OUT GND DC ILIMIT 9 10 11 VEAO VFB VREF VCC PFC OUT 12 13 14 15 2 D4 MMBZ5245B R13 10k R26 10k C23 100nF 3 VREF U3 TL431A R25 2.26k 4 12V RET VCC 12V RETURN R11 845k C10 15uF 5 6 RAMP1 7 RAMP1 RAMP2 8 D8 MBRS 140 D10 MBRS 140 R8 2.37k C31 1nF C15 10nF R16 10k C16 1uF C13 0.1uF C14 1uF C8 68nF C9 10nF D12 1N5401 C19 1uF C18 470pF C11 10nF C17 220pF D13 1N5401 C26 100nF VDC www.fairchildsemi.com PRI GND F1 3.15A BR1 4A, 600V KBL06 R2A 453k R27 75k D9 MBRS 140 C25 0.1uF D5 RGF1J R28 240 T1B C12 10uF 35V D11B MBR2545CT C24 1uF C21 2200uF 25V R7B 178k L2 D11A MBR2545CT D7 MMBZ5245B R30 4.7k C4 10nF R1A 500k Q1 FQPF9N50 C5 100uF 450V R7A 178k R17 33 Q2 FQPF 6N50 L1 D2 1N5406 D1 ISL9R460P2 D3 RGF1J VDC / +380V Q1G NOTE : Q2G AC INPUT C1 85 TO 265Vac 0.68uF L1; PREMIER MAGNETICS TDS-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 ISENSE R2B 453k R1B 500k R3 110k C30 330uF 25V R21 22 FAN4800 — Low Startup Current PFC/PWM Controller Combinations © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 12V 12V, 100W C2 0.47uF R4 15.4k T2 Q3 FQPF6N50 D6 RGF1J R6 41.7k R10 6.2k R15 3 R20A 2.2 T1A R19 220 R9 1.1k 16 Q4 MMBT3904 R20B 2.2 C20 1uF R14 33 R5D R5C 1.2 R5B 1.2 R5A 1.2 1.2 C3 0.1uF Q3G Typical Application Circuit (Continued) R24 1.2k R18 220 RAMP2 / DC ILIMIT R23 1.5k U2 MOC8112 C22 4.7uF R22 8.66k R31 100 U1 R12 71.5k C7 NOT USED C6 1.5nF Figure 13. Voltage-Mode Application 17 FAN4800 1 IEAO VFB IAC ISENSE VRMS SS VDC PWM OUT GND DC ILIMIT 9 10 11 VEAO VFB VREF VCC PFC OUT 12 13 14 15 2 D4 MMBZ5245B R13 10k R26 10k C23 100nF 3 VREF U3 TL431A R25 2.26k 4 12V RET VCC 12V RETURN R11 845k C10 15uF R16 10k 5 6 RAMP1 7 RAMP1 RAMP2 8 D8 MBRS 140 D10 MBRS 140 R8 2.37k C31 1nF C15 10nF C16 1uF C13 0.1uF C14 1uF C8 68nF C9 10nF D12 1N5401 C19 1uF C18 470pF R29 61.9k C17 220pF D13 1N5401 C27 C11 10nF 470pF C26 100nF VDC www.fairchildsemi.com PRI GND FAN4800 — Low Startup Current PFC/PWM Controller Combinations Physical Dimensions A 19.68 18.66 16 9 6.60 6.09 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 3.42 3.17 3.81 2.92 2.54 0.58 A 0.35 1.78 1.14 17.78 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 8.13 7.62 0.35 0.20 8.69 15 0 Figure 14. 16-Lead Plastic Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 18 FAN4800 — Low Startup Current PFC/PWM Controller Combinations © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 19