FAN4810MX

www.fairchildsemi.com FAN4810 Power Factor Correction Controller Features • TriFault Detect™ for UL1950 compliance and enhanced safety • Slew rate enhanced transconductance error amplifier for ultra-fast PFC response • Low power: 200µA startup current, 5.5mA operating current • Low total harmonic distortion, high PF • Average current, continuous boost leading edge PFC • Current fed gain modulator for improved noise immunity • Overvoltage and brown-out protection, UVLO, and soft start • Synchronized clock output General Description The FAN4810 is a controller for power factor corrected, switched mode power supplies. The FAN4810 includes circuits for the implementation of leading edge, average current, “boost” type power factor correction and results in a power supply that fully complies with IEC1000-3-2 specification. It also includes a TriFault Detect™ function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate-driver with 1A capability minimizes the need for external driver circuit. Low power requirements improve efficiency and reduce component costs. The PFC also includes peak current limiting, input voltage brownout protection and a overvoltage comparator shuts down the PFC section in the event of a sudden decrease in load. The clock-out signal can be used to synchronize down-stream PWM stages in order to reduce system noise. Block Diagram 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 OSCILLATOR R Q GAIN MODULATOR 3.6kΩ VEA – + 1 IEAO POWER FACTOR CORRECTOR 0.5V 3.6kΩ - 13 VCC OVP + 2.75V – TRI-FAULT + – VCC 17V 7.5V REFERENCE S Q VREF 14 IEA + + – -1V + – R S Q PFC OUT Q 12 PFC ILIMIT 8 DUTY CYCLE LIMIT 6 1.25V VCC 25µA + – CLKOUT S VFB 2.45V – + Q VIN OK R Q 11 5 CLKSD 9 VREF 10 VCC UVLO REV. 1.0.12 9/24/03 FAN4810 PRODUCT SPECIFICATION Pin Configuration FAN4810 (Pin Out) IEAO 1 IAC 2 ISENSE 3 VRMS 4 CLKSD 5 NC 6 RAMP 1 7 NC 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 CLK OUT 10 GND 9 GND TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name IEAO IAC ISENSE VRMS CLKSD NC RAMP 1 NC GND GND CLK OUT PFC OUT VCC VREF VFB VEAO Ground Ground Clock signal synchronized to PFC frequency PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output Oscillator timing node; timing set by RTCT Function Slew rate enhanced PFC transconductance error amplifier output PFC AC line reference input to Gain Modulator Current sense input to the PFC Gain Modulator PFC Gain Modulator RMS line voltage compensation input Turn on/off PWM clock without disturbing PFC out 2 REV. 1.0.12 9/24/03 PRODUCT SPECIFICATION FAN4810 Abolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VCC ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink PFC OUT, CLK OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Plastic DIP Plastic SOIC -65 -5 GND - 0.3 Min. Max. 18 0.7 VCCZ + 0.3 10 10 1 1.5 150 150 260 80 105 Units V V V mA mA A µJ °C °C °C °C/W °C/W Operating Conditions Min. Temperature Range 0 Max. 70 Units °C Electrical Characteristics Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage Input Bias Current VNON INV = VINV, VEAO = 3.75V -1.5 50 0 100 4 -0.5 2 150 15 -1.0 V µ mV µA 11V < VCC < 16.5V VIN = ±0.5V, VOUT = 6V VIN = ±0.5V, VOUT = 1.5V -40 40 50 50 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V Conditions Min. 0 30 2.43 65 2.5 -0.5 6.7 0.1 -140 140 60 60 0.4 Typ. Max. Units 5 90 2.57 -1.0 V µ V µA V V µA µA dB dB Voltage Error Amplifier REV. 1.0.12 9/24/03 3 FAN4810 PRODUCT SPECIFICATION Electrical Characteristics(Continued) Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP Comparator Threshold Voltage Hysteresis Tri-Fault Detect Fault Detect HIGH Time to Fault Detect HIGH VFB = VFAULT DETECT LOW to VFB = OPEN. 470pF from VFB to GND 0.4 -0.9 120 2.65 2.75 2 2.85 4 V ms 2.65 175 2.75 250 2.85 325 V mV 11V < VCC < 16.5V VIN = ±0.5V, VOUT = 6V VIN = ±0.5V, VOUT = 1.5V -40 40 60 60 Conditions Min. 6.0 Typ. 6.7 0.65 -104 160 70 75 1.0 Max. Units V V µA µA dB dB Fault Detect LOW PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output GAIN Modulator Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V IAC = 50µA, VRMS = 1.2V, VFB = 0V IAC = 50µA, VRMS = 1.8V, VFB = 0V IAC = 100µA, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current Reference Output Voltage Line Regulation Load Regulation TA = 25°C, I(VREF) = 1mA 11V tDEADTIME) that the operating frequency can typically be approximated by: f OSC 1 = --------------t RAMP (5) The FAN4810 is a voltage-fed part. It requires an external 15V, ±10% (or better) shunt voltage regulator, or some other VCC regulator, to regulate the voltage supplied to the part at 15V nominal. This allows low power dissipation while at the same time delivering 13V nominal gate drive at the PFC OUT output. If using a Zener diode for this function, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the FAN4810 itself (7mA, max.) plus the current required by the gate driver output and zener diode. EXAMPLE: With a VBIAS of 20V, a VCC of 15V and the FAN4810 driving a total gate charge of 38nC at 100kHz (e.g., 1 IRF840 MOSFET ), the gate driver current required is: I GATEDRIVE = 100kHz × 38nC = 3.8mA V BIAS – V CC R BIAS = --------------------------------I CC + I G + I Z 20V – 15V R BIAS = ------------------------------------------------------ = 316 Ω 7mA + 3.8mA + 5mA Choose RBIAS = 330Ω. The FAN4810 should be locally bypassed with a 1.0µF ceramic capacitor. In most applications, an electrolytic capacitor of between 47µF and 220µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. (7) (8) EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: f OSC 1 = 100kHz = --------------t RAMP Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1kΩ. Clock Out (Pin 11) Clock output is a rail to rail CMOS driver. The PMOS can pull up within 15 ohms of the rail and the NMOS can pull down to within 7 ohms of ground. The clock turns on when the CLKSD pin is greater than 1.25V and the PFC output voltage is at rated operation value. The clock signal can be used to synchronize and provide on/ off control for downstream DC to DC PWM converters. CLKSD (Pin 5) Typical Applications Figure 4 is the application circuit for a complete 125W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 42046. A current source of 25µA supplies the charging current for a capacitor connected to this pin. Start-up delay can be programmed by the following equation: 25 µ A C dly = t DELAY × -------------1.25V (6) where Cdly is the required soft start capacitance, and tDELAY is the desired start-up delay. 10 REV. 1.0.12 9/24/03 PRODUCT SPECIFICATION FAN4810 IN5406 KBLD6 L F1 3.15A 3.1mH 15L9R482 D1 D2 ~ C1 .68µF + L1 Q1 IRF840 +385 V AC INPUT 85 TO 260 V N BR1 R27 75KΩ R2A 100µF C4 10nF + R7A ~ D12 C5 D9 MBR5140 (2) 453 KΩ R21 22Ω (2) 178 KΩ R1A R7B R2B R1B (2) 499 KΩ (2) IN5401 D13 R31 100Ω C3 100nF C2 470nF R28 330Ω + D3 L1 D6 C10µF C12 C19 1.0µF C20 1.0µF RAMP1 75KΩ 10KΩ R3 + 15V Zener 47µF R4 C30 (not used) C7 71.5KΩ R12 1.5nF C6 1 2 3 4 IEAO IAC ISENSE VRMS CLKSD VEAO FB REF VCC V01 16 15 14 13 C16 C15 C14 845KΩ R11 41.2KΩ R6 CLK OUT VCC REF ISENSE (4) 1.2 Ω R5D R5C R5B R5A 5 6 7 8 470pF C19 100nF C18 C26 12 11 CLK OUT RAMP1 GND 1nF 10nF C13 100nF 1µF 10 C31 2.37KΩ R8 C9 C8 68nF U1 GND 9 10nF 1nF FAN4810 D8 Figure 4. 125W Power Factor Corrected Power Supply Using AN42046 1µF MBR5140 D10 MBR5140 REV. 1.0.12 9/24/03 11 FAN4810 PRODUCT SPECIFICATION Package Dimensions 16-Lead Plastic Dual Inline Package (PDIP) 0.300" Body Width Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. D 8 1 Inches Min. Max. Millimeters Min. Max. Notes — .210 .015 — .115 .195 .014 .022 .045 .070 .008 .014 .745 .840 .005 — .300 .325 .240 .280 .100 BSC — .430 .115 .160 16 — 5.33 .38 — 2.93 4.95 .36 .56 1.14 1.78 .20 .36 18.92 21.33 .13 — 7.62 8.26 6.10 7.11 2.54 BSC — 10.92 2.92 4.06 16 4 2 2 5 E1 D1 9 16 E e A A1 L B1 B eB A2 C 12 REV. 1.0.12 9/24/03 PRODUCT SPECIFICATION FAN4810 Package Dimensions (Continued) 16-Lead Small Outline IC (SOIC) 0.150" Symbol A A1 B C D E e H h L N α ccc Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 16 9 6. Symbol "N" is the maximum number of terminals. Inches Min. Max. Millimeters Min. Max. Notes .053 .069 .004 .010 .013 .020 .0075 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0° — 8° .004 .244 .020 .050 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0° — 8° 0.10 6.20 0.50 1.27 5 2 2 3 6 E H 1 8 D A1 A SEATING PLANE –C– LEAD COPLANARITY ccc C α h x 45° C e B L REV. 1.0.12 9/24/03 13 FAN4810 PRODUCT SPECIFICATION Ordering Information Part Number FAN4810N FAN4810M FAN4810MX Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C Package 16-Pin MDIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin Narrow SOIC in Tape & Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/24/03 0.0m 001 Stock#DS30004800  2003 Fairchild Semiconductor Corporation