FAN5056MV85

www.fairchildsemi.com FAN5056MV85 High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms Features • Output programmable in 25mV steps from 1.05V to 1.825V using a dynamically programmable integrated 5-bit DAC • Controls adjustable linears for Vclock (2.5V), Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and Vadj (1.2V nominal) • Remote sense • Programmable Active Droop™ up to 200mV • Drives N-Channel MOSFETs • Overcurrent protection using MOSFET sensing • Overvoltage protection including startup • 85% efficiency typical at full load • Integrated Power Good and Enable/Soft Start functions • Meets Intel VRM8.5 specifications using minimum number of external components • 24 pin SOIC package Description The FAN5056 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Pentium III, and provides a complete solution for all Intel VRM8.5 CPU applications, and for other high-performance processors. The FAN5056 features remote voltage sensing, independently adjustable current limit, and a proprietary wide-range Programmable Active Droop™ for optimal converter transient response and VRM8.5 compliance. The FAN5056 uses a 5-bit D/A converter to dynamically program the output voltage during operation from 1.05V to 1.825V in 25mV steps. The FAN5056 uses a high level of integration to deliver load currents in excess of 28A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves 0.8% voltage regulation without expensive external components. The FAN5056 includes linear regulator controllers for Vclock (2.5V),Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), and Vadjustable (1.2V nominal) each adjustable with an external divider. The FAN5056 also offers integrated functions Applications • Power supply for Pentium® III Platforms • VRM for Pentium III processor • Programmable multi-output power supply Block Diagram +3.3V +5V VCCA 21 +1.2V/Adj 9 10 VCCP 11 + + REF PWRGD, OCL OCL REF +12V PWRGD, OCL OSC + 15 14 13 3.3/1.5V 5-Bit DAC 1.24V Reference Power Good 3 GNDA 16 ENABLE/SS + + 18 RS 20 24 VCCP 1 HIDRV +5V + 19 RD 12 +2.5V Digital Control 2 VCC V PWRGD, OCL + 23 LODRV 22 GNDP 17 PWRGD 8765 4 VID0 VID2 VID4 VID1 VID3 Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor. REV. 1.0.6 6/26/01 FAN5056MV85 PRODUCT SPECIFICATION including open-collector Power Good, Output Enable/Soft Start and current limiting, and is available in a 24 pin SOIC package. Pin Assignments HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VADJGATE VADJFB VCKGATE VCKFB 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE TYPEDET VAGPGATE VAGPFB FAN5056 Pin Definitions Pin Number 1 2 3 4-8 Pin Name HIDRV SW GNDA VID4-0 Pin Function Description High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8. Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The FAN5056 provides significant cost savings for the newer CPU systems that typically run at high supply current. FAN5056 Short Circuit Current Characteristics The FAN5056 protects against output short circuit on the core supply by latching off both the high-side and low-side MOSFETs. The FAN5056 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. The short circuit limit is set with the RS resistor, as given by the formula RS = ISC *RDS, on IDetect Inductor Selection Choosing the value of the inductor is a trade-off between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: (Vin – Vout) f Vout Vin ESR x Vripple with IDetect ≈ 50µA, ISC the desired current limit, and RDS,on the high-side MOSFET’s on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET’s RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 6, eliminates this source of inaccuracy in the current limit. As an example, Figure 3 shows the typical characteristic of the DC-DC converter circuit with two FDD6690A high-side MOSFETs (RDS = 17mΩ maximum at 25°C * 1.25 at 75°C = 21.25mΩ each for a total of 10.6mΩ) and a 6.19KΩ RS. Lmin = x where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: Lmax = 2CO (Vin – Vout) Dm Vtb Ipp2 VOUT (V) 0 10 20 30 40 50 Output Current (A) Figure 3. FAN5056 Short Circuit Characteristic where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50µA * 6.2KΩ = 310mV, which occurs at 310mV/10.6mΩ = 29A. [Note that this current limit level can be as high as 310mV/6.5mΩ = 48A, if the MOSFET has typical RDS,on rather than maximum, and is at 25°C. This is the reason for using the external sense resistor.] At this point, the internal comparator trips and signals the REV. 1.0.6 6/26/01 10 PRODUCT SPECIFICATION FAN5056MV85 controller to reduce the converter’s duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 4mΩ output short, the voltage is reduced to 29A * 4mΩ = 116mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter. deliver current when the high side MOSFET switches on. Figure 4 shows 3 x 1000µF, but the exact number required will vary with the speed and type of the processor. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15. 2.5µH 5V 0.1µF Vin 1000µF, 10V Electrolytic Schottky Diode Selection The application circuits of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET’s body diode. Figure 4. Input Filter Programmable Active Droop™ The FAN5056 includes Programmable Active Droop™: as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. This is done in order to allow maximum headroom for transient response of the converter. The current is typically sensed by measuring the voltage across the RDS,on of the high-side MOSFET during its on time, as shown in Figures 1 and 2. To program the amount of droop, use the formula RD 14.4KΩ *Imax *Rsense VDroop *3 Output Filter Capacitors The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1µF and 0.01µF are recommended values. where Imax is the current at which the droop occurs, and Rsense is the resistance of the current sensor, either the source resistor or the high-side MOSFET’s on-resistance. For example, to get 120mV of droop with a maximum output current of 30A and a 10mΩ sense resistor, use RD = 14.4KΩ * 30A * 10mΩ/(120mV *3) = 12KΩ. The value of the product Imax*Rsense must be < 600mV for proper functioning of the droop circuit. If this product is exceeded, a lower resistance MOSFET must be used. Further details on use of the Programmable Active Droop™ may be found in Applications Bulletin AB-24. Remote Sense Input Filter The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5µH is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors The FAN5056 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the FAN5056 may be found in Applications Bulletin AB-24. REV. 1.0.6 6/26/01 11 FAN5056MV85 PRODUCT SPECIFICATION Adjusting the Linear Regulators’ Output Voltages Any or all of the linear regulators’ outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 5. PCB Layout Guidelines • Placement of the MOSFETs relative to the FAN5056 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5056 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. • In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5056. That is, traces that connect to pins 1, 2, 23, and 24 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 20 and 21. • Place the 0.1µF decoupling capacitors as close to the FAN5056 pins as possible. Extra lead length on these reduces their ability to suppress noise. • Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. • Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. • Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. • A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. VGATE VOUT R VFB 10KΩ Figure 5. Adjusting the Output Voltage of the Linear Regulator The resistor value should be chosen as Vout Vnom R = 2KΩ* For example, to get the VADJ voltage to be 1.50V instead of 1.20V, use R = 2KΩ * [(1.50/1.20) – 1] = 500Ω. Using the FAN5056 for Vnorthbridge = 1.8V Similarly, the FAN5056 can also be used to generate Vnorthbridge = 1.8V by utilizing the AGP regulator as shown in Figure 5: tie the TYPEDET pin to ground, and use R = 399Ω. Coppermine/Tualatin VTT The adjustable regulator may be used for powering VTT in systems in which either a Coppermine or a Tualatin processor may be used, as shown in Figure 6. VGATE VTT 100Ω VFB 487Ω 10KΩ 10KΩ AF36 3.16KΩ Additional Information For additional information contact your local Fairchild Semiconductor representative, or visit us at our web site www.fairchildsemi.com. 2N7002 2N7002 Figure 6. Using VADJ to Generate VTT 12 REV. 1.0.6 6/26/01 PRODUCT SPECIFICATION FAN5056MV85 Appendix Worst-Case Formulae for the Calculation of Cin, Cout, R5, R7 and Roffset (Circuits similar to Figure 1 only) The following formulae design the FAN5056 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VS+, the value of the positive static voltage limit; |VS-|, the absolute value of the negative static voltage limit; VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; Number of capacitors needed for COUT = the greater of: X= VTESR * IO + VS+ – .024 * Vnom or ESR * IO VT+ – VS+ + 14400 * IO * RD 18 * R5 * 1.1 Y= Example: Suppose that the static limits are +89mV/-79mV, transient limits are ±134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing. We have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and ∆RD = 1.67. We calculate: 2 2.000 14.2 * 5 Cin = 2 – 2.000 5 IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this data sheet); RD, the resistance of the current sensor (usually the MOSFET); ∆RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and ESR, the ESR of the output capacitors, per cap (44mΩ for the Sanyo parts shown in this data sheet). 2 IO * Cin = Vnom Vin Irms – Vnom Vin = 3.47 ⇒ 4 caps Roffset = 0.089 – .014 * 2.000 – .029 *1000 = 15.8Ω 0.29 + 2.000 14.2 * 0.020 * (1 + 0.67) 45 * 10-6 = 10.5KΩ R7 = R5 = 14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 18 * (0.089 + 0.079 – .024 * 2.000) = 3.48KΩ X= 0.044 * 14.2 0.134 + 0.089 – .024 * 2.00 0.044 * 14.2 = 3.57 Y= 0.134 – 0.089 + 14400 * 14.2 * 0.020 18 * 3640 * 1.1 = 6.14 Roffset = VS+ – .014 * Vnom – .029 .029 * Vnom IO * R D * ( 1 + ∆ R D ) 45 * 10-6 Since Y > X, we choose Y, and round up to find we need 7 capacitors for COUT. * 1KΩ A detailed explanation of this calculation may be found in Applications Bulletin AB-24. R7 = 14400 * IO* RD * (1 + ∆RD) *1.1 R5 = 18 * (VS+ + VS- – .024 * Vnom) REV. 1.0.6 6/26/01 13 PRODUCT SPECIFICATION FAN5056MV85 Mechanical Dimensions 24 Lead SOIC Symbol A A1 B C D E e H h L N α ccc Inches Min. .093 .004 .013 .009 .599 Max. .104 .012 .020 .013 .614 Millimeters Min. 2.35 0.10 0.33 0.23 15.20 Max. 2.65 0.30 0.51 0.32 15.60 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. .290 .299 .050 BSC .394 .419 .010 .016 24 0° — 8° .004 .020 .050 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0° — 8° 0.10 0.51 1.27 3 6 24 13 E H 1 12 D A e B A1 SEATING PLANE –C– LEAD COPLANARITY ccc C α L h x 45° C REV. 1.0.6 6/26/01 14 FAN5056MV85 PRODUCT SPECIFICATION Ordering Information Product Number FAN5056MV85 Description VRM8.5 Package 24 pin SOIC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 6/26/01 0.0m 005 Stock#DS30005056MV85  2001 Fairchild Semiconductor Corporation