FAN5231

www.fairchildsemi.com FAN5231 Precision Dual PWM Controller And Linear Regulator for Notebook CPUs Features • Provides 3 Regulated Voltages – Microprocessor core (SpeedStep™-enabled) – Microprocessor I/O – Microprocessor Clock Generator • High Efficiency Over Wide Load Range • Not Dissipative Current-Sense Scheme – Uses MOSFET’s R DS(ON) – Optional Current-Sense Resistor for Precision Overcurrent • Adaptive Dead Time Drivers for N-Channel MOSFETs • Operates from +5V, +3.3V and Battery (5.6-24V) Inputs • Precision Core Voltage Control: – Remote “Kelvin” Sensing – Summing Current-Mode Control – On-Chip Mode-Compensated “Droop” for Optimum Transient Response and Lower Processor Power Dissipation • TTL-Compatible 5-Bit Digital Output Voltage Selection – Wide Range - 0.925VDC to 1.3VDC in 25mV Steps, and from 1.3VDC to 2.0VDC in 50mV Steps – Programmable “On-the-Fly” VID code change with customer programmable slew rate and 100ms settling time • Power-Good Output Voltage Monitor • No negative Core and I/O voltage on turn-off • Over-Voltage, Under-Voltage and Over-Current Fault Monitors • 300kHz Fixed Switching Frequency • Thermal Shut-Down Applications • Converters for Mobile Dual-Mode CPUs • Web Tablets • Internet Appliances +V IN PWM 2 V OUT2 I/ O CONTROLLER PWM 1 CONTRO LLER V OUT 1 CORE +V IN 3.3V V OUT3 CPU CLK LI NEAR REGULATOR VI D CODE FAN5231 Figure 1. Simplified Power System Diagram REV. 1.1.1 8/15/01 FAN5231 Description The FAN5231 is a highly integrated power controller, which provides a complete power management solution for mobile CPUs. The IC integrates two PWM controllers and a linear regulator as well as monitoring and protection circuitry into a single 28-lead plastic SSOP package. The two PWM controllers regulate the microprocessor core and I/O voltages with synchronous-rectified buck converters, while the linear regulator powers the CPU clock. The FAN5231 includes 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925VDC to 2.0VDC and conforms to the Intel Mobile VID specification. The DAC setting may be changed during operation to accommodate Dual-Mode processors. Special measures are taken to provide such a transition with controlled rate in a specified 100 µs. A precision reference, remote sensing, and a proprietary architecture with integrated processor mode-compensated "droop" provide excellent static and dynamic core voltage regulation. The second PWM controller has a fixed 1.5V output voltage and powers the I/O circuitry. Both PWM controllers have integrated feedback-loop compensation that dramatically reduces the number of external components. At nominal loads PWM controllers operate at fixed frequency 300kHz. At light loads when the filter inductor current becomes discontinuous, controllers operate in a hysteretic mode. The out-of-phase operation of two PWM controllers reduces input current ripple in both modes of operation. The linear regulator uses an internal pass device to provide 2.5V for the CPU clock generator. The FAN5231 monitors all the output voltages. A single Power-Good signal is issued when soft start is completed and all outputs are within ±10% of their respective set points. A built-in over-voltage protection for the core and I/O outputs forces the lower MOSFETs on to prevent output voltages from going above 115% of their settings. Under-voltage protection latches the chip off when any of the three outputs drops below 75% of the set value. The PWM controller's overcurrent circuitry monitors the output current by sensing the voltage drop across the lower MOSFETs. If precision overcurrent protection is required, an external current-sense resistor may be used. Block Diagram VBATT LI NEAR REGULA TOR V3I N FL OGON -+ VOUT3 0.9V + FFBK 1 RAM P 2 CLK RAMP 1 POWER-ON RESET (POR) GATE L OGI C 1 CLK 2 CLK1 FCCM DEADT PWM /HYST BOOT2 UGATE2 PHASE2 PWM ON HYST ON HGDR2 HI FL OGON SHUTOFF VCC PWM LATCH 1 QD R Q< + DYNAM I C DUTY CYCLE CLAMP OC LOGI C1 OC COMP1 + +HY ST COM P1 + CLK 1 DAC OUT LGDR1 LO OVP1 LG ATE1 PGND1 GATE CONTROL VCC SHUTOFF HI EN VCC GND BOOT1 HGDR1 UGATE1 PHASE1 GATE CONTROL VCC LG ATE2 PGND2 LG DR2 OVP2 HY ST COM P2 CLK2 + GATE LOGI C 2 DEADT PWM /HYST LO PWM ON HYST ON PRE AM P EA1 + FFBK 1 LG ATE1 R1= 20k + ∑ + - VSEN1 VRET1 FAST FEEDBACK COMP 1 + LG ATE1 ISEN1 OC COM P2 + 2.8V OC LOGI C2 VCC PWM LATCH 2 DQ R