FAN5236QSC

www.fairchildsemi.com FAN5236 Dual Mobile-Friendly DDR / Dual-output PWM Controller Features • Highly flexible dual synchronous switching PWM controller includes modes for: – DDR mode with in-phase operation for reduced channel interference – 90˚ phase shifted two-stage DDR Mode for reduced input ripple – Dual Independent regulators 180° phase shifted • Complete DDR Memory power solution – VTT Tracks VDDQ/2 – VDDQ/2 Buffered Reference Output • Lossless current sensing on low-side MOSFET or precision over-current using sense resistor • VCC Under-voltage Lockout • Converters can operate from +5V or 3.3V or Battery power input (5 to 24V) • Excellent dynamic response with Voltage Feed-Forward and Average Current Mode control • Power-Good Signal • Also supports DDR-II and HSTL • Light load Hysteretic mode maximizes efficiency • QSOP28, TSSOP28 General Description The FAN5236 PWM controller provides high efficiency and regulation for two output voltages adjustable in the range from 0.9V to 5.5V that are required to power I/O, chip-sets, and memory banks in high-performance notebook computers, PDAs and Internet appliances. Synchronous rectification and hysteretic operation at light loads contribute to a high efficiency over a wide range of loads. The hysteretic mode of operation can be disabled separately on each PWM converter if PWM mode is desired for all load levels. Efficiency is even further enhanced by using MOSFET’s RDS(ON) as a current sense component. Feed-forward ramp modulation, average current mode control scheme, and internal feedback compensation provide fast response to load transients. Out-of-phase operation with 180 degree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR mode of operation one of the channels tracks the output voltage of another channel and provides output current sink and source capability — features essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5236 monitors these outputs and generates separate PGx (power good) signals when the soft-start is completed and the output is within ±10% of its set point. A built-in over-voltage protection prevents the output voltage from going above 120% of the set point. Normal operation is automatically restored when the over-voltage conditions go away. Under-voltage protection latches the chip off when either output drops below 75% of its set value after the softstart sequence for this output is completed. An adjustable over-current function monitors the output current by sensing the voltage drop across the lower MOSFET. If precision current-sensing is required, an external current-sense resistor may optionally be used. Applications • • • • DDR VDDQ and VTT voltage generation Mobile PC dual regulator Server DDR power Hand-Held PC power REV. 1.1.9 7/12/04 PRODUCT SPECIFICATION FAN5236 Generic Block Diagrams +5 VCC FAN5236 VIN (BATTERY) = 5 to 24V Q1 ILIM1 L OUT1 VOUT1 = 2.5V COUT1 PWM 1 Q2 DDR Q3 ILIM2/ REF2 L OUT2 VOUT2 = 1.8V COUT2 PWM 2 Q4 Figure 1. Dual output regulator +5 VCC FAN5236 VIN (BATTERY) = 5 to 24V Q1 ILIM1 L OUT1 VDDQ = 2.5V COUT1 R PWM 1 Q2 +5 DDR Q3 R VTT = VDDQ/2 COUT2 PG2/REF 1.25V L OUT2 Q4 PWM 2 ILIM2/REF2 Figure 2. Complete DDR Memory Power Supply 2 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Pin Configurations AGND LDRV1 PGND1 SW1 HDRV1 BOOT1 ISNS1 EN1 FPWM1 VSEN1 ILIM1 SS1 DDR VIN 1 2 3 4 5 6 28 27 26 25 24 23 VCC LDRV2 PGND2 SW2 HDRV2 BOOT2 ISNS2 EN2 FPWM2 VSEN2 ILIM2/REF2 SS2 PG2/REF2OUT PG1 7 22 FAN5236 8 21 9 10 11 12 13 14 20 19 18 17 16 15 QSOP-28 or TSSOP-28 θJA = 90°C/W Pin Definitions Pin Number 1 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 Pin Name AGND LDRV1 LDRV2 PGND1 PGND2 SW1 SW2 HDRV1 BOOT1 BOOT2 ISNS1 ISNS2 EN1 EN2 FPWM1 FPWM2 Pin Function Description Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side MOSFET. Power Ground. The return for the low-side MOSFET driver. Connect to source of lowside MOSFET. Switching node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and low-side MOSFET drain. High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side MOSFET. BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 3. Current Sense input. Monitors the voltage drop across the lower MOSFET or external sense resistor for current feedback. Enable. Enables operation when pulled to logic high. Toggling EN will also reset the regulator after a latched fault condition. These are CMOS inputs whose state is indeterminate if left open. Forced PWM mode. When logic low, inhibits the regulator from entering hysteretic mode. Otherwise tie to VOUT. The regulator uses VOUT on this pin to ensure a smooth transition from Hysteretic mode to PWM mode. When VOUT is expected to exceed VCC, tie to VCC. Output Voltage Sense. The feedback from the outputs. Used for regulation as well as PG, under-voltage and over-voltage protection and monitoring. Current Limit 1. A resistor from this pin to GND sets the current limit. Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during initialization. During initialization, this pin is charged with a 5µA current source. DDR Mode Control. High = DDR mode. Low = 2 separate regulators operating 180° out of phase. 3 10 19 11 12 17 13 VSEN1 VSEN2 ILIM1 SS1 SS2 DDR REV. 1.1.9 7/12/04 PRODUCT SPECIFICATION FAN5236 Pin Definitions Pin Number 14 Pin Name VIN (continued) Pin Function Description Input Voltage. Normally connected to battery, providing voltage feed-forward to set the amplitude of the internal oscillator ramp. When using the IC for 2-step conversion from 5V input, connect through 100K to ground, which will set the appropriate ramp gain and synchronize the channels 90˚ out of phase. Power Good Flag. An open-drain output that will pull LOW when VSEN is outside of a ±10% range of the 0.9V reference. Power Good 2. When not in DDR Mode: Open-drain output that pulls LOW when the VOUT is out of regulation or in a fault condition Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as the VDDQ/2 reference. Current Limit 2. When not in DDR Mode, A resistor from this pin to GND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1 / 2. VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V (UVLO falling). 15 16 PG1 PG2 / REF2OUT 18 ILIM2 / REF2 VCC 28 Absolute Maximum Ratings Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter VCC Supply Voltage: VIN BOOT, SW, ISNS, HDRV BOOTx to SWx All Other Pins Junction Temperature (TJ ) Storage Temperature Lead Soldering Temperature, 10 seconds –0.3 –40 –65 Min. Typ. Max. 6.5 27 33 6.5 VCC+0.3 150 150 300 Units V V V V V °C °C °C Recommended Operating Conditions Parameter Supply Voltage VCC Supply Voltage VIN Ambient Temperature (TA ) Note 1 –10 Conditions Min. 4.75 Typ. 5 Max. 5.25 24 85 Units V V °C Note 1: Industrial temperature range (–40 to + 85°C) may be special ordered from Fairchild. Please contact your authorized Fairchild representative for more information. 4 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Electrical Specifications Recommended operating conditions, unless otherwise noted. Parameter Power Supplies VCC Current LDRV, HDRV Open, VSEN forced above regulation point Shut-down (EN=0) VIN Current – Sinking VIN Current – Sourcing VIN Current – Shut-down UVLO Threshold UVLO Hysteresis Oscillator Frequency Ramp Amplitude, pk–pk Ramp Amplitude, pk–pk Ramp Offset Ramp / VIN Gain Ramp / VIN Gain Reference and Soft Start Internal Reference Voltage Soft Start current (ISS) Soft Start Complete Threshold PWM Converters Load Regulation VSEN Bias Current VOUT pin input impedance Under-voltage Shutdown Over-voltage threshold ISNS Over-Current threshold Output Drivers HDRV Output Resistance LDRV Output Resistance Sourcing Sinking Sourcing Sinking PG (Power Good Output) and Control pins Lower Threshold Upper Threshold PG Output Low Leakage Current PG2/REF2OUT Voltage as % of set point, 2µS noise filter as % of set point, 2µS noise filter IPG = 4mA VPULLUP = 5V DDR = 1, 0 mA < IREF2OUT ≤10mA 99 –86 108 –94 116 0.5 1 1.01 % % V µA % VREF2 12 2.4 12 1.2 15 4 15 2 Ω Ω Ω Ω as % of set point. 2µS noise filter as % of set point. 2µS noise filter RILIM= 68.5KΩ see Figure 11. IOUTX from 0 to 5A, VIN from 5 to 24V -2 50 45 70 115 112 80 55 75 120 140 +2 120 65 80 125 168 % nA KΩ % % µA at start-up 0.891 0.9 5 1.5 0.909 V µA V VIN ≥ 3V 1V < VIN < 3V VIN = 16V VIN = 5V 255 300 2 1.25 0.5 125 250 345 KHz V V V mV/V mV/V Rising VCC Falling 4.3 4.1 4.55 4.25 300 VIN = 24V VIN = 0V 10 –15 2.2 3.0 30 30 –30 1 4.75 4.45 mA µA µA µA µA V V mV Conditions Min. Typ. Max. Units REV. 1.1.9 7/12/04 5 PRODUCT SPECIFICATION FAN5236 Electrical Specifications Recommended operating conditions, unless otherwise noted. (continued) Parameter DDR, EN Inputs Input High Input Low FPWM Inputs FPWM Low FPWM High FPWM connected to output 0.9 0.1 V V 2 0.8 V V Conditions Min. Typ. Max. Units 5V VDD EN BOOT CBOOT VIN Q1 FPWM/VOUT SS HYST OVP HYST SW Q2 VDD LDRV PGND Q S R PWM RAMP ILIM det. VSEN EA DUTY CYCLE CLAMP MODE ISNS PWM PWM/HYST RSENSE S/H L OU T POR/UVLO FPWM DDR HDRV VOUT COU T DDR ADAPTIVE GATE CONTROL LOGIC OSC RAMP CLK VIN CURRENT PROCESSING Σ IOU T FPWM/VOUT SS VREF PGOOD REF2 ILIM R ILIM Reference and Soft Start PWM/HYST DDR Figure 3. IC Block Diagram 6 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Typical Applications VIN (BATTERY) = 5 to 24 V 14 VIN BOOT1 C1 D1 +5 C5 L1 6 C9 +5 C4 VCC 28 Q1 A 5 ILIM1 EN1 SS1 11 8 4 HDRV1 SW 1 R3 VDDQ = 2.5V C6A R5 C6B Q1B PWM 1 12 C2 +5 R4 PG1 2 3 7 9 LDRV1 R7 PGND2 ISNS1 FPWM1 (VOUT1) VSEN1 15 10 R1 +5 DDR EN2 SS2 13 23 21 17 24 25 BOOT2 R6 D2 +5 C7 L2 VTT = VDDQ/2 C8A Q2 A HDRV2 SW 2 C3 1.25V@10mA PG2/REF AGND 16 1 R2 Q2B PWM 2 27 26 22 LDRV2 PGND2 ISNS2 VSEN2 ILIM2/REF2 R8 C8B FPWM2 20 19 18 Figure 4. DDR Regulator Application Table 1. DDR Regulator BOM Description Capacitor 68µf, Tantalum, 25V, ESR 150mΩ Capacitor 10nf, Ceramic Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω Capacitor 150nF, Ceramic Capacitor 180µf, Specialty Polymer 4V, ESR 15mΩ Capacitor 1000µf, Specialty Polymer 4V, ESR 10mΩ Capacitor 0.1µF, Ceramic 18.2KΩ, 1% Resistor 1.82KΩ, 1% Resistor 56.2KΩ, 1% Resistor 10KΩ, 5% Resistor 3.24KΩ, 1% Resistor 1.5KΩ, 1% Resistor Schottky Diode 30V Inductor 6.4µH, 6A, 8.64mΩ Inductor 0.8µH, 6A, 2.24mΩ Dual MOSFET with Schottky DDR Controller Qty Ref. 1 2 1 2 2 1 2 3 1 2 2 1 2 2 1 1 1 1 C1 C2, C3 C4 C5, C7 C6A, C6B C8 C9 R1, R2 R6 R3 R4 R5 R7, R8 D1, D2 L1, L2 Q1, Q2 U1 Vendor AVX Any AVX Any Panasonic Kemet Any Any Any Any Any Any Any Fairchild Panasonic Panasonic Fairchild Fairchild Part Number TPSV686*025#0150 TAJB686*006 EEFUE0G181R T510E108(1)004AS4115 BAT54 ETQ-P6F6R4HFA ETQ-P6F0R8LFA FDS6986S (note 1) FAN5236 Note 1: Suitable for typical notebook computer application of 4A continuous, 6A peak for VDDQ. If continuous operation above 6A is required use single SO-8 packages for Q1A (FDS6612A) and Q1B (FDS6690S) respectively. Using FDS6690S, change R7 to 1200Ω. Refer to Power MOSFET Selection, page 15 for more information. REV. 1.1.9 7/12/04 7 PRODUCT SPECIFICATION FAN5236 Typical Applications (continued) VIN (BATTERY) = 5 to 24V 14 VIN BOOT1 C1 D1 +5 C5 L1 6 C9 +5 C4 R2 VCC 28 Q1A 5 ILIM1 EN1 SS1 11 8 12 4 HDRV1 SW 1 2.5V@6A C6 Q1B PWM 1 2 3 LDRV1 C2 +5 R3 PG1 R6 PGND2 ISNS1 FPWM1 (VOUT1) VSEN1 7 9 15 10 DDR 13 23 R4 VIN BOOT2 R5 D2 +5 C7 L2 1.8V@6A C8 R7 Q2A EN2 21 24 25 HDRV2 SW 2 PG2 SS2 16 17 Q2B C3 AGND 1 PWM 2 27 26 22 LDRV2 PGND2 ISNS2 VSEN2 ILIM2 R8 R9 R1 FPWM2 20 19 18 Figure 5. Dual Regulator Application Table 2. Dual Regulator BOM Item 1 2 3 4 5 5 11 12 13 14 15 27 28 29 30 Description Capacitor 68µf, Tantalum, 25V, ESR 95mΩ Capacitor 10nf, Ceramic Capacitor 68µf, Tantalum, 6V, ESR 1.8Ω Capacitor 150nF, Ceramic Capacitor 330µf, Poscap, 4V, ESR 40mΩ Capacitor 0.1µF, Ceramic 56.2KΩ, 1% Resistor 10KΩ, 5% Resistor 3.24KΩ, 1% Resistor 1.82KΩ, 1% Resistor 1.5KΩ, 1% Resistor Schottky Diode 30V Inductor 6.4µH, 6A, 8.64mΩ Dual MOSFET with Schottky DDR Controller Qty 1 2 1 2 2 2 2 2 1 3 2 2 1 1 1 Ref. C1 C2, C3 C4 C5, C7 C6, C8 C9 R1, R2 R3 R4 R5, R8, R9 R6, R7 D1, D2 L1, L2 Q1 U1 Vendor AVX Any AVX Any Sanyo Any Any Any Any Any Any Fairchild Panasonic Fairchild Fairchild Part Number TPSV686*025#095 TAJB686*006 4TPB330ML BAT54 ETQ-P6F6R4HFA FDS6986S (note 1) FAN5236 Note 1: If currents above 4A continuous required, use single SO-8 packages for Q1A/Q2A (FDS6612A) and Q1B/Q2B (FDS6690S) respectively. Using FDS6690S, change R6/R7 as required. Refer to Power MOSFET Selection, page 15 for more information. 8 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Circuit Description Overview The FAN5236 is a multi-mode, dual channel PWM controller intended for graphic chipset, SDRAM, DDR DRAM or other low voltage power applications in modern notebook, desktop, and sub-notebook PCs. The IC integrates a control circuitry for two synchronous buck converters. The output voltage of each controller can be set in the range of 0.9V to 5.5V by an external resistor divider. The two synchronous buck converters can operate from either an unregulated DC source (such as a notebook battery) with voltage ranging from 5.0V to 24V, or from a regulated system rail of 3.3V to 5V. In either mode of operation the IC is biased from a +5V source. The PWM modulators use an average current mode control with input voltage feed-forward for simplified feedback loop compensation and improved line regulation. Both PWM controllers have integrated feedback loop compensation that dramatically reduces the number of external components. Depending on the load level, the converters can operate either in fixed frequency PWM mode or in a hysteretic mode. Switch-over from PWM to hysteretic mode improves the converters’ efficiency at light loads and prolongs battery run time. In hysteretic mode, comparators are synchronized to the main clock that allows seamless transition between the operational modes and reduced channel-to-channel interaction. The hysteretic mode of operation can be inhibited independently for each channel if variable frequency operation is not desired. The FAN5236 can be configured to operate as a complete DDR solution. When the DDR pin is set high, the second channel can provide the capability to track the output voltage of the first channel. The PWM2 converter is prevented from going into hysteretic mode if the DDR pin is set high. In DDR mode, a buffered reference voltage (buffered voltage of the REF2 pin), required by DDR memory chips, is provided by the PG2 pin. When used as a dual converter (as in Figure 5), out-of-phase operation with 180 degree phase shift reduces input current ripple. For the “2-step” conversion (where the VTT is converted from VDDQ as in Figure 4) used in DDR mode, the duty cycle of the second converter is nominally 50% and the optimal phasing depends on VIN. The objective is to keep noise generated from the switching transition in one converter from influencing the "decision" to switch in the other converter. When VIN is from the battery, it’s typically higher than 7.5V. As shown in Figure 6, 180° operation is undesirable since the turn-on of the VDDQ converter occurs very near the decision point of the VTT converter. CLK VDDQ VTT Figure 6. Noise-susceptible 180° phasing for DDR1 In-phase operation is optimal to reduce inter-converter interference when VIN is higher than 5V, (when VIN is from a battery), as can be seen in Figure 7. Since the duty cycle of PWM1 (generating VDDQ) is short, it’s switching point occurs far away from the decision point for the VTT regulator, whose duty cycle is nominally 50%. CLK VDDQ VTT Figure 7. Optimal In-Phase operation for DDR1 Converter Modes and Synchronization Table 3. Converter modes and Synchronization Mode DDR1 DDR2 DUAL VIN Battery +5V ANY VIN Pin VIN R to GND VIN DDR Pin HIGH HIGH LOW PWM 2 w.r.t. PWM1 IN PHASE + 90° + 180° When VIN ≈ 5V, 180° phase shifted operation can be rejected for the same reasons demonstrated Figure 6. In-phase operation with VIN ≈ 5V is even worse, since the switch point of either converter occurs near the switch point of the other converter as seen in Figure 8. In this case, as VIN is a little higher than 5V it will tend to cause early termination of the VTT pulse width. Conversely, VTT’s switch point can cause early termination of the VDDQ pulse width when VIN is slightly lower than 5V. REV. 1.1.9 7/12/04 9 PRODUCT SPECIFICATION FAN5236 CLK When SS reaches 1.5V, the Power Good outputs are enabled and hysteretic mode is allowed. The converter is forced into PWM mode during soft start. VDDQ Operation Mode Control VTT Figure 8. Noise-susceptible In-Phase operation for DDR2 These problems are nicely solved by delaying the 2nd converter’s clock by 90° as shown in Figure 9. In this way, all switching transitions in one converter take place far away from the decision points of the other converter. CLK VDDQ The mode-control circuit changes the converter’s mode of operation from PWM to Hysteretic and visa versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed-frequency PWM mode as shown in Figure 10. This mode of operation achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive, and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. To prevent accidental mode change or "mode chatter" the transition from PWM to Hysteretic mode occurs when the SW node is positive for eight consecutive clock cycles (see Figure 10). The polarity of the SW node is sampled at the end of the lower MOSFET’s conduction time. At the transition between PWM and hysteretic mode both the upper and lower MOSFETs are turned off. The phase node will ‘ring’ based on the output inductor and the parasitic capacitance on the phase node and settle out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression. ( V IN – V OUT ) V OUT I LOAD ( DIS ) = -------------------------------------------------2F SW L OUT V IN (2) VTT Figure 9. Optimal 90° phasing for DDR2 Initialization and Soft Start Assuming EN is high, FAN5236 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal Power-On Reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin which is charged with a 5µA current source. Once CSS has charged to VREF (0.9V) the output voltage will be in regulation. The time it takes SS to reach 0.9V is: T 0.9 0.9 × C SS = ---------------------5 (1) where T0.9 is in seconds if CSS is in µF. VCORE IL 0 PWM Mode Hysteretic Mode yste e 1 2 3 4 5 6 7 8 VCORE IL Hy Hysteretic Mode ys y de 0 PWM Mode 4 5 6 7 8 1 2 3 Figure 10. Transitioning between PWM and Hysteretic Mode 10 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Hysteretic Mode Conversely, the transition from Hysteretic mode to PWM mode occurs when the SW node is negative for 8 consecutive cycles. A sudden increase in the output current will also cause a change from hysteretic to PWM mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSNS) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. In hysteretic mode, the PWM comparator and the error amplifier that provide control in PWM mode are inhibited and the hysteretic comparator is activated. In hysteretic mode the low side MOSFET is operated as a synchronous rectifier, where the voltage across ( VDS(ON) ) it is monitored, and it is switched off when VDS(ON) goes positive (current flowing back from the load) allowing the diode to block reverse conduction. The hysteretic comparator initiates a PFM signal to turn on HDRV at the rising edge of the next oscillator clock, when the output voltage (at VSNS) falls below the lower threshold (10mV below VREF) and terminates the PFM signal when VSNS rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: 1. 2. 3. Spread between the two hysteretic thresholds ILOAD Output Inductor and Capacitor ESR A transition back to PWM (Continuous Conduction Mode or CCM) mode occurs when the inductor current rises sufficiently to stay positive for 8 consecutive cycles. This occurs when: ∆ V HYSTERESIS I LOAD ( CCM ) = -------------------------------------2 ESR (3) where ∆VHYSTERESIS = 15mV and ESR is the equivalent series resistance of COUT. Because of the different control mechanisms, the value of the load current where transition into CCM operation takes place is typically higher compared to the load level at which transition into hysteretic mode occurs. Hysteretic mode can be disabled by setting the FPWM pin low. 0.17pf 1.5M 300K VSEN 4.14K V to I in + ISNS TO PWM COMP in – PGND ISNS LDRV ISNS RSENSE 17pf S/H CSS SS Reference and Soft Start I2 = ILIM*11.2 2.5V 0.9V ILIM R ILIM ILIM ILIM det. Figure 11. Current Limit / Summing Circuits REV. 1.1.9 7/12/04 11 PRODUCT SPECIFICATION FAN5236 Current Processing Section The following discussion refers to Figure 11. The current through RSENSE resistor (ISNS) is sampled shortly after Q2 is turned on. That current is held, and summed with the output of the error amplifier. This effectively creates a current mode control loop. The resistor connected to ISNSx pin (RSENSE) sets the gain in the current feedback loop. For stable operation, the voltage induced by the current feedback at the PWM comparator input should be set to 30% of the ramp amplitude at maximum load currrent and line voltage. The following expression estimates the recommended value of RSENSE as a function of the maximum load current (ILOAD(MAX)) and the value of the MOSFET’s RDS(ON): R SENSE I LOAD ( MAX ) • R DS ( ON ) • 4.1K = ---------------------------------------------------------------------------- – 100 0.30 • 0.125 • V IN ( MAX ) (4a) More accurate sensing can be achieved by using a resistor (R1) instead of the RDS(ON) of the FET as shown in Figure 12. This approach causes higher losses, but yields greater accuracy in both VDROOP and ILIMIT . R1 is a low value (e.g. 10mΩ) resistor. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.2 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (we’ll use 25%). For example, in Figure 5 the target for ILIMIT would be: ILIMIT > 1.2 × 1.25 × 1.6 × 6A ≈14A (6) Duty Cycle Clamp During severe load increase, the error amplifier output can go to its upper limit pushing a duty cycle to almost 100% for significant amount of time. This could cause a large increase of the inductor current and lead to a long recovery from a transient, over-current condition, or even to a failure especially at high input voltages. To prevent this, the output of the error amplifier is clamped to a fixed value after two clock cycles if severe output voltage excursion is detected, limiting the maximum duty cycle to V OUT 2.4 DC MAX = -------------- + --------V IN V IN RSENSE must, however, be kept higher than: I LOAD ( MAX ) • R DS ( ON R SENSE ( MIN ) = ----------------------------------------------------------) – 100 150 µ A (4b) Setting the Current Limit A ratio of ISNS is also compared to the current established when a 0.9 V internal reference drives the ILIM pin: ( 100 + R SENSE ) 11.2 R ILIM = --------------- × --------------------------------------R DS ( ON ) I LIMIT (5) This circuit is designed to not interfere with normal PWM operation. When FPWM is grounded, the duty cycle clamp is disabled and the maximum duty cycle is 87%. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current. When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4% / °C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease propotional to increasing MOSFET die temperature. A factor of 1.6 in the current limit setpoint should compensate for all MOSFET RDS(ON) variations, assuming the MOSFET’s heat sinking will keep its operating die temperature below 125°C. Gate Driver section The Adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-tosource voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the gate-tosource voltage of the upper MOSFET has decreased to less than approximately 1 volt. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1 volt. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circit and shoot-through may occur. REV. 1.1.9 7/12/04 Q2 LDRV ISNS RSENSE R1 PGND Figure 12. Improving current sensing accuracy 12 FAN5236 PRODUCT SPECIFICATION Frequency Loop Compensation Due to the implemented current mode control, the modulator has a single pole response with -1 slope at frequency determined by load 1 F PO = --------------------2 π RO CO (7) Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 10kHz...50kHz range gives some additional phase ‘boost’. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible. If a larger inductor value or low ESR values are called for by the application, additional phase margin can be achieved by putting a zero at the LC crossover frequency. This can be achieved with a capacitor across across the feedback resistor (e.g. R5 from Figure 5) as shown below. L(OUT) R5 VSEN R6 C(Z) VOUT C(OUT) where RO is load resistance, CO is load capacitance. For this type of modulator, Type 2 compensation circuit is usually sufficient. To reduce the number of external components and simplify the design task, the PWM controller has an internally compensated error amplifier. Figure 13 shows a Type 2 amplifier and its response along with the responses of a current mode modulator and of the converter. The Type 2 amplifier, in addition to the pole at the origin, has a zero-pole pair that causes a flat gain region at frequencies between the zero and the pole. FZ 1 = ------------------- = 6kHz 2 π R2 C1 (8a) (8b) 1 F P = ------------------- = 600kHz 2 π R2 C2 Figure 14. Improving Phase Margin This region is also associated with phase ‘bump’ or reduced phase shift. The amount of phase shift reduction depends the width of the region of flat gain and has a maximum value of 90°. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp. The zero frequency, the amplifier high frequency gain and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. C2 R2 C1 R1 VIN REF EA Out The optimal value of C(Z) is: L ( OUT ) × C ( OUT ) C ( Z ) = ----------------------------------------------------R (9) Protection The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. A sustained overload on an output sets the PGx pin low and latches-off the regulator on which the fault occurs. Operation can be restored by cycling the VCC voltage or by toggling the EN pin. If VOUT drops below the under-voltage threshold, the regulator shuts down immediately. Over-Current sensing If the circuit’s current limit signal (“ILIM det” as shown in Figure 11) is high at the beginning of a clock cycle, a pulseskipping circuit is activated and HDRV is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the “ILIM det” is again reached, the over-current protection latch is set, disabling the regulator. If “ILIM det” does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. FP C on err or a mp ve rte r 18 14 0 modulator F P0 FZ Figure 13. Compensation REV. 1.1.9 7/12/04 13 PRODUCT SPECIFICATION FAN5236 Design and Component Selection Guidelines PGOOD 1 IL SHUTDOWN 2 VOUT 8 CLK As an initial step, define operating input voltage range, output voltage, minimum and maximum load currents for the controller. Setting the Output Voltage The interal reference is 0.9V. The output is divided down by a voltage divider to the VSEN pin (for example, R5 and R6 in Figure 4). The output voltage therefore is: 3 CH1 5.0V CH2 2.0AΩ CH2 100mV M 10.0µs V OUT – 0.9V 0.9V ----------- = -------------------------------R5 R6 (10a) Figure 15. Over-Current protection waveforms Over-Voltage / Under-voltage Protection Should the VSNS voltage exceed 120% of VREF (0.9V) due to an upper MOSFET failure, or for other reasons, the overvoltage protection comparator will force LDRV high. This action actively pulls down the output voltage and, in the event of the upper MOSFET failure, will eventually blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output short-circuit or severe load transient causes the output to droop to less than 75% of its regulation set point, the regulator will shut down. To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K. We selected R6 at 1.82K. Then choose R5: ( 1.82K ) ( V OUT – 0.9 ) R5 = ---------------------------------------------------- = 3.24K 0.9 (10b) For DDR applications converting from 3.3V to 2.5V, or other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter’s FPWM to GND. When converter’s FPWM is GND, the converter’s maximum duty cycle will be greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for In-Phase synchronization by tying the VIN pin to +5V. Output Inductor Selection The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light load, the controller can automatically switch to hysteretic mode of operation to sustain high efficiency. The following equations help to choose the proper value of the output filter inductor. ∆ V OUT ∆ I = 2 × I MIN = -----------------ESR (11) Over-Temperature Protection The chip incorporates an over temperature protection circuit that shuts the chip down when a die temperature of about 150°C is reached. Normal operation is restored at die temperature below 125°C with internal Power On Reset asserted, resulting in a full soft-start cycle. where ∆I is the inductor ripple current and ∆VOUT is the maximum ripple allowed. V IN – V OUT V OUT L = ----------------------------- × -------------F SW × ∆ I V IN (12) for this example we’ll use: VIN = 20V, VOUT = 2.5V ∆I = 20% * 6A = 1.2A FSW = 300KHz. therefore L ≈ 6µH 14 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor it filters the sequence of pulses produced by the switcher, and it supplies the load transient currents. The output capacitor requirements are usually dictated by ESR, Inductor ripple current (∆I) and the allowable ripple voltage (∆V). ∆V ESR < ------∆I (13) therefore: 2.5 2.5 2 I RMS = 3.5 ------ –  ------  = 1.49A 16  16  (17) Dual Converter 180° phased In Dual mode (Figure 5), both converters contribute to the capacitor input ripple current. With each converter operating 180° out of phase, the RMS currents add in the following fashion: I RMS = I RMS = I RMS ( 1 ) + I RMS ( 2 ) or ( I1 ) ( D1 – D1 ) + ( I2 ) ( D2 – D2 ) 2 2 2 2 2 2 In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the converter in Figure 5 is 120mV P-P. Some additional ripple will appear due to the capacitance value itself: ∆I ∆ V = ---------------------------------------C OUT × 8 × F SW (14) (18a) (18b) which for the dual 3A converters of Figure 5, calculates to: I RMS = 1.4A which is only about 1.5mV for the converter in Figure 5 and can be ignored. The capacitor must also be rated to withstand the RMS current which is approximately 0.3 X (∆I), or about 400mA for the converter in Figure 5. High frequency decoupling capacitors should be placed as close to the loads as physically possible. Power MOSFET Selection Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN5236 converter’s output voltage is low with respect to its input voltage, therefore the Lower MOSFET (Q2) is conducting the full load current for most of the cycle. Q2 should therefore be selected to minimize conduction losses, thereby selecting a MOSFET with low RDS(ON). In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and it’s conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1’s primary selection criteria should be gate charge. Input Capacitor Selection The input capacitor should be selected by its ripple current rating. Two-Stage Converter Case In DDR mode (Figure 4), the VTT power input is powered by the VDDQ output, therefore all of the input capacitor ripple current is produced by the VDDQ converter. A conservative estimate of the output current required for the 2.5V regulator is: I VTT I REG1 = I VDDQ + ----------2 High-Side Losses: Figure 15 shows a MOSFET’s switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis therefore is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from MOSFET datasheets. Assuming switching losses are about the same for both the rising edge and falling edge, Q1’s switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. As an example, if average IVDDQ is 3A, and average IVTT is 1A, IVDDQ current will be about 3.5A. If average input voltage is 16V, RMS input ripple current will be: I RMS = I OUT ( MAX ) D – D 2 (15) where D is the duty cycle of the PWM1 converter: V OUT 2.5 D < -------------- = -----V IN 16 (16) REV. 1.1.9 7/12/04 15 PRODUCT SPECIFICATION FAN5236 These losses are given by: PUPPER = PSW + PCOND P SW V DS × I L =  --------------------- × 2 × t S F SW   2 V OUT 2 = -------------- × I OUT × R DS ( ON ) V IN (19a) Q G ( SW ) Q G ( SW ) t S = -------------------- ≈ ---------------------------------------------------I DRIVER  VCC – V SP ----------------------------------------------   R DRIVER + R GATE (20) P COND (19b) PUPPER is the upper MOSFET’s total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 Figure 15. The driver’s impedance and CISS determine t2 while t3’s period is controlled by the driver’s impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS: C ISS CRSS CISS Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the the gate charge required to get the MOSFET to it’s threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET’s gate power (PGATE ) in calculating the power dissipation required for the FAN5236: PGATE = QG × VCC × FSW (21) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS , Q2’s switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by: P COND = ( 1 – D ) × I OUT × R DS ( ON ) 2 VDS (22) ID VGS VSP VTH QGS QGD 4.5V where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and V OUT D = -------------- is the minimum duty cycle for the converter. V IN QG(SW) t1 t2 t3 t4 t5 Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the low-side MOSFET, the θJ-A, and the maximum allowable ambient temperature rise: CISS = CGS || CGD Figure 16. Switching losses and QG 5V C GD RD HDRV RGATE G CGS SW VIN T J ( MAX ) – T A ( MAX P D ( MAX ) = -------------------------------------------------) θJ – A (23) θJ-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see FSC app note AN-1029 for SO-8 MOSFET thermal information). Figure 17. Drive Equivalent Circuit 16 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Layout Considerations Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI if layout constrains are not observed. There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and are noise generators. The low power components responsible for bias and feedback functions are sensitive to noise. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing such as SW, HDRV and LDRV, for example. All surrounding circuitry will tend to couple the signals from these nodes through stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. It is not recommended to use High Density Interconnect Systems, or micro-vias on these signals. The use of blind or buried vias should be limited to the low current signals only. The use of normal thermal vias is left to the discretion of the designer. Keep the wiring traces from the IC to the MOSFET gate and source as short as possible and capable of handling peak currents of 2A. Minimize the area within the gate-source path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close as possible to the respective pins of the IC. The FAN5236 utilizes advanced packaging technologies with lead pitches of 0.6mm. High performance analog semiconductors utilizing narrow lead spacing may require special considerations in PWB design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices. REV. 1.1.9 7/12/04 17 PRODUCT SPECIFICATION FAN5236 Mechanical Dimensions 28-Pin QSOP Symbol A A1 A2 B C D E e H h L N α Inches Min. 0.053 0.004 0.008 0.007 Max. 0.069 0.010 0.061 0.012 0.010 Millimeters Min. 1.35 0.10 0.20 0.18 Max. 1.75 0.25 1.54 0.30 0.25 9 4. 3 4 Notes: Notes 1. 2. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. Dimensioning and tolerancing per ANSI Y14.5M-1982. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions shall not exceed 0.25mm (0.010 inch) per side. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. The chamber on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. "L" is the length of terminal for soldering to a substrate. "N" is the maximum number of terminals. Terminal numbers are shown for reference only. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 0.386 0.394 0.150 0.157 0.025 BSC 0.228 0.0099 0.016 28 0° 8° 0.244 0.0196 0.050 9.81 10.00 3.81 3.98 0.635 BSC 5.80 0.26 0.41 28 0° 8° 6.19 0.49 1.27 5. 5 6 7 6. 7. 8. 9. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. D E H A A2 B e A1 SEATING PLANE –C– LEAD COPLANARITY ccc C α L C 18 REV. 1.1.9 7/12/04 FAN5236 PRODUCT SPECIFICATION Mechanical Dimensions 28-Pin TSSOP –A– 9.7 ± 0.1 0.51 TYP 28 15 –B– 4.16 4.4 ± 0.1 6.4 3.2 14 PIN # 1 IDENT LAND PATTERN RECOMMENDATION 1.2 MAX 0.1 C ALL LEAD TIPS 0.90 –0.10 +0.15 BA 0.2 ALL Lead Tips 1.78 0.65 0.42 See Detail A 0.09–0.20 –C– 0.65 0.19–0.30 0.13 0.10 ± 0.05 AB C 12.00° Top & Botom R0.16 GAGE PLANE DIMENSIONS ARE IN MILLIMETERS 0°–8° R0.31 .025 NOTES: 0.61 ± 0.1 1.00 SEATING PLANE A. Conforms to JEDEC registration MO-153, variation AB, Ref. Note 6, dated 7/93. B. Dimensions are in millimeters. C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions. D Dimensions and Tolerances per ANsI Y14.5M, 1982 DETAIL A 7.72 REV. 1.1.9 7/12/04 19 PRODUCT SPECIFICATION FAN5236 Ordering Information Part Number FAN5236QSC FAN5236QSCX FAN5236MTC FAN5236MTCX Temperature Range -10°C to 85°C -10°C to 85°C -10°C to 85°C -10°C to 85°C Package QSOP-28 QSOP-28 TSSOP-28 TSSOP-28 Packing Rails Tape and Reel Rails Tape and Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/12/04 0.0m 004 Stock#DS30005236  2004 Fairchild Semiconductor Corporation