FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
September 2011
FAN5400 / FAN5401 / FAN5402 / FAN5403 / FAN5404 / FAN5405 USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Features
Fully Integrated, High-Efficiency Charger for Single-Cell Li-Ion and Li-Polymer Battery Packs Faster Charging than Linear Charge Voltage Accuracy: 0.5% at 25°C 1% from 0 to 125°C
Description
The FAN5400 family (FAN540X) combines a highly integrated switch-mode charger, to minimize single-cell Lithium-ion (Li-ion) charging time from a USB power source, and a boost regulator to power a USB peripheral from the battery. The charging parameters and operating modes are 2 programmable through an I C Interface that operates up to 3.4Mbps. The charger and boost regulator circuits switch at 3MHz to minimize the size of external passive components. The FAN540X provides battery charging in three phases: conditioning, constant current, and constant voltage. To ensure USB compliance and minimize charging time, the 2 input current is limited to the value set through the I C host. Charge termination is determined by a programmable minimum current level. A safety timer with reset control provides a safety backup for the I2C host. The integrated circuit (IC) automatically restarts the charge cycle when the battery falls below an internal threshold. If the input source is removed, the IC enters a high-impedance mode with leakage from the battery to the input prevented. Charge status is reported back to the host through the I2C port. Charge current is reduced when the die temperature reaches 120°C. The FAN540X can operate as a boost regulator on command from the system. The boost regulator includes a soft-start that limits inrush current from the battery. The FAN540X is available in a 1.96 x 1.87mm, 20-bump, 0.4mm pitch WLCSP package.
L1 1H 0.1F
5% Input Current Regulation Accuracy 5% Charge Current Regulation Accuracy 20V Absolute Maximum Input Voltage 6V Maximum Input Operating Voltage 1.25A Maximum Charge Rate Programmable through High-Speed I2C Interface (3.4Mb/s) with Fast Mode Plus Compatibility
– – – –
Input Current Fast-Charge / Termination Current Charger Voltage Termination Enable
3MHz Synchronous Buck PWM Controller with Wide Duty Cycle Range Small Footprint 1H External Inductor Safety Timer with Reset Control 1.8V Regulated Output from VBUS for Auxiliary Circuits Weak Input Sources Accommodated by Reducing Charging Current to Maintain Minimum VBUS Voltage Low Reverse Leakage to Prevent Battery Drain to VBUS 5V, 300mA Boost Mode for USB OTG for 2.5 to 4.5V Battery Input
VBUS CBUS
1F
SW PGND CSIN FAN540X VBAT
COUT
RSENSE
68m
PMID CMID
4.7F
+ Battery
Applications
Cell Phones, Smart Phones, PDAs Tablet, Portable Media Players Gaming Device, Digital Cameras
SDA SCL DISABLE OTG/USB# STAT
VREG CREG
1F
SYSTEM LOAD
CBAT
10F
All trademarks are the property of their respective owners.
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
Figure 1. Typical Application (FAN5403-05 Pin Out)
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Ordering Information
Part Number
FAN5400UCX FAN5401UCX FAN5402UCX FAN5403UCX FAN5404UCX FAN5405UCX
Temperature Range
-40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C -40 to 85°C
Package
20- Bump, WaferLevel Chip-Scale Package (WLCSP), 0.4mm Pitch, Estimated Size: 1.96 x 1.87mm
PN Bits: IC_INFO[4:3]
01 00 01 10 11 10
Packing Method
Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel Tape and Reel
Table 1. Feature Comparison Summary Part Number
FAN5400 FAN5401 FAN5402 FAN5403 FAN5404 FAN5405
PN Bits:
REG3[4:3] 01 00 01 10 11 10
Slave Address
1101011 1101011 1101011 1101011 1101011 1101010
Automatic Charge
Yes No Yes Yes No Yes
Special Charger(1)
No No No Yes Yes Yes
Safety Limits
No No No Yes Yes Yes
Battery Absent Behavior
OFF OFF ON OFF OFF ON
E2 Pin
AUXPWR (Connect to VBAT)
VREG (E3 Pin)
PMID
DISABLE
1.8V
Note: 1. Special charger is a current limited charger that is not a USB compliant source.
Table 2. Recommended External Components Component
L1 CBAT CMID CBUS
Description
1H, 20%, 1.3A, 2016 10F, 20%, 6.3V, X5R, 0603 4.7F, 10%, 6.3V, X5R, 0603 1.0F, 10%, 25V, X5R, 0603
Vendor
Murata: LQM2MPN1R0M or Equivalent Murata: GRM188R60J106M TDK: C1608X5R0J106M Murata: GRM188R60J475K TDK: C1608X5R0J475K Murata GRM188R61E105K TDK:C1608X5R1E105M
Parameter
L DCR (Series R) C C(2) C
Typ.
1.0 85 10 4.7 1.0
Unit
H m F F F
Note: 2. 6.3V rating is sufficient for CMID since PMID is protected from over-voltage surges on VBUS by Q3 (Figure 3).
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Block Diagram
Figure 2. IC and System Block Diagram
VBUS CIN1
Q3
PMID CIN2
Q1
CHARGE PUMP
Q1A Q1B
CSIN SW
L1 1 H
PMID Greater than VBAT Less than VBAT
Q1A ON OFF
Q1B OFF ON
Q2
COUT PGND VBAT SYSTEM LOAD
RSENSE
68m
+ Battery CBAT
Figure 3. Power Stage
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Pin Configuration
A1 A2 A3 A4 A4 A3 A2 A1
B1
B2
B3
B4
B4
B3
B2
B1
C1
C2
C3
C4
C4
C3
C2
C1
D1
D2
D3
D4
D4
D3
D2
D1
E1
E2
E3
E4
E4
E3
E2
E1
Top View Figure 4. WLCSP-20 Pin Assignments
Bottom View
Pin Definitions
Pin #
A1, A2 A3 A4 B1-B3 B4 C1-C3 C4 D1-D3 D4 E1 E2
Name
VBUS NC SCL PMID SDA SW STAT PGND OTG CSIN
Part #
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
Description
Charger Input Voltage and USB-OTG output voltage. Bypass with a 1F capacitor to PGND. No Connect. No external connection is made between this pin and the IC’s internal circuitry. I2C Interface Serial Clock. This pin should not be left floating. Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and high-voltage input switch. Bypass with a minimum of 4.7F, 6.3V capacitor to PGND. I2C Interface Serial Data. This pin should not be left floating. Switching Node. Connect to output inductor. Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in process. Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of CMID should be as short as possible. On-The-Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table 16). On VBUS Power-On Reset (POR), this pin sets the input current limit for t15MIN charging. Current-Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to sense current into the battery. Bypass this pin with a 0.1F capacitor to PGND.
FAN5400, Auxiliary Power. Connect to the battery pack to provide IC power during High-Impedance AUXPWR FAN5401, Mode. Bypass with a 1F capacitor to PGND. FAN5402 FAN5403, Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is 2 DISABLE FAN5404, controlled by the I C registers. When this pin is HIGH, the 15-minute timer is reset. This pin FAN5405 does not affect the 32-second timer. VREG VBAT ALL ALL Regulator Output. Connect to a 1F capacitor to PGND. This pin can supply up to 2mA of DC load current. For FAN5400-FAN5402, the output voltage is PMID, which is limited to 6.5V. For FAN5403-FAN5405, the output voltage is regulated to 1.8V. Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1F capacitor to PGND if the battery is connected through long leads.
E2
E3 E4
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VBUS VSTAT VI VO
dVBUS dt
Parameter
VBUS Voltage STAT Voltage PMID Voltage SW, CSIN, VBAT, AUXPWR, DISABLE Voltage Voltage on Other Pins Maximum VBUS Slope above 5.5V when Boost or Charger are Active Electrostatic Discharge Protection Level Junction Temperature Storage Temperature Lead Soldering Temperature, 10 Seconds Human Body Model per JESD22-A114 Charged Device Model per JESD22-C101 Continuous Pulsed, 100ms Maximum Non-Repetitive
Min.
–1.4 –2.0 –0.3 –0.3 –0.3
Max.
20.0 16.0 7.0 7.0 6.5(3) 4 2000 500
Unit
V V V V V/s V
ESD TJ TSTG TL
–40 –65
+150 +150 +260
°C °C °C
Note: 3. Lesser of 6.5V or VI + 0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VBUS VBAT(MAX)
dVBUS dt
Parameter
Supply Voltage Maximum Battery Voltage when Boost enabled Negative VBUS Slew Rate during VBUS Short Circuit, CMID < 4.7F, see VBUS Short While Charging Ambient Temperature Junction Temperature (see Thermal Regulation and Protection section) TA < 60°C TA > 60°C
Min.
4
Max.
6 4.5 4 2
Units
V V V/s °C °C
TA TJ
–30 –30
+85 +120
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperature TA. For measured data, see Table 11.
Symbol Parameter
JA JB Junction-to-Ambient Thermal Resistance Junction-to-PCB Thermal Resistance
Typical
60 20
Units
°C/W °C/W
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
Power Supplies
Parameter
Conditions
VBUS > VBUS(min), PWM Switching
Min.
Typ.
10 2.5 63 0.2
Max.
Units
mA mA
IVBUS
VBUS Current
VBUS > VBUS(min); PWM Enabled, Not Switching (Battery OVP Condition); I_IN Setting=100mA 0°C < TJ < 85°C, HZ_MODE=1 VBAT < VLOWV, 32S Mode
90 5.0 20
A A
ILKG
VBAT to VBUS Leakage Current
0°C < TJ < 85°C, HZ_MODE=1, VBAT=4.2V, VBUS=0V 0°C < TJ < 85°C, HZ_MODE=1, VBAT=4.2V FAN5403-05, DISABLE=1, 0°C < TJ < 85°C, VBAT=4.2V 3.5 TA=25°C TJ=0 to 125°C VLOWV < VBAT < VOREG VBUS > VSLP, RSENSE=68m 20mV < VIREG < 40mV VIREG > 40mV FAN5400-02 FAN5403-05 FAN5400-02 FAN5403-05 –0.5% –1%
IBAT
Battery Discharge Current in HighImpedance Mode
A 10
Charger Voltage Regulation Charge Voltage Range VOREG Charge Voltage Accuracy 4.4 +0.5% +1% V
Charging Current Regulation Output Charge Current Range IOCHRG 550 95 92 97 94 3.4 –5 Rising Voltage, 2mV Overdrive 1.05 0.4 Input Tied to GND or VIN VBAT > VOREG – VRCH, VBUS > VSLP, RSENSE=68m [VCSIN – VBAT] from 3mV to 20mV [VCSIN – VBAT] from 20mV to 40mV 2mV Overdrive IREG from 0 to 2mA, FAN5403-05 1.7 0.01 1.00 30 100 97 100 97 1250 105 102 103 100 3.7 +5 V % ms V V A % mA
Charge Current Accuracy Across RSENSE
Weak Battery Detection Weak Battery Threshold Range VLOWV Weak Battery Threshold Accuracy Weak Battery Deglitch Time Logic Levels: DISABLE, SDA, SCL, OTG VIH VIL IIN High-Level Input Voltage Low-Level Input Voltage Input Bias Current
Charge Termination Detection Termination Current Range I(TERM) Termination Current Accuracy Termination Current Deglitch Time 1.8V Linear Regulator VREG 1.8V Regulator Output 1.8 1.9 V 50 –25 –5 30 400 +25 +5 mA % ms
Continued on the following page…
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
VIN(MIN)1 VIN(MIN)2 tVBUS_VALID VSP
Parameter
VBUS Input Voltage Rising Minimum VBUS during Charge VBUS Validation Time Special Charger Setpoint Accuracy
Conditions
To Initiate and Pass VBUS Validation During Charging
Min.
Typ.
4.29 3.71 30
Max.
4.42 3.94
Units
V V ms
Input Power Source Detection
Special Charger (VBUS) (FAN5403 – FAN5405)
–3 +3 %
Input Current Limit IINLIM Input Current Limit Threshold IIN Set to 100mA IIN Set to 500mA VBUS > VIN(MIN) or VBAT > VBAT(MIN) 20 Below V(OREG) VBAT Falling Below VRCH Threshold ISTAT=10mA VSTAT=5V 100 120 130 0.4 1 150 88 450 93 475 98 500 6.5 mA
VREF Bias Generator VREF Bias Regulator Voltage Short-Circuit Current Limit Recharge Threshold Deglitch Time STAT Output Low STAT High Leakage Current Battery Detection Current before Charge Done (Sink Current)(4) Battery Detection Time Sleep-Mode Entry Threshold, VBUS – VBAT Deglitch Time for VBUS Rising Above VSLP + VSLP_EXIT Q3 On Resistance (VBUS to PMID) RDS(ON) Q1 On Resistance (PMID to SW) Q2 On Resistance (SW to GND) Charger PWM Modulator fSW DMAX DMIN ISYNC Oscillator Frequency Maximum Duty Cycle Minimum Duty Cycle Synchronous to Non-Synchronous Current Cut-Off Threshold(5) Low-Side MOSFET (Q2) Cycle-byCycle Current Limit 0 140 2.7 3.0 3.3 100 MHz % % mA V mA mV ms V A
Battery Recharge Threshold VRCH STAT Output VSTAT(OL) ISTAT(OH)
Battery Detection IDETECT tDETECT Begins after Termination Detected and VBAT < VOREG –VRCH –0.80 262 mA ms
Sleep Comparator VSLP VSLP_EXIT 2.3V < VBAT < VOREG, VBUS Falling Rising Voltage 0 0.04 30 0.10 V ms
Power Switches (see Figure 3) IIN(LIMIT)=500mA 180 130 150 250 225 225 mΩ
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Electrical Specifications
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
2.5V < VBAT < 4.5V, ILOAD from 0 to 200mA 2.7V < VBAT < 4.5V, ILOAD from 0 to 200mA PFM Mode, VBAT=3.6V, IOUT=0
Min.
Typ.
Max.
Units
Boost Mode Operation (OPA_MODE=1, HZ_MODE=0) 4.80 4.85 5.07 5.07 140 1100 While Boost Active To Start Boost Regulator Normal Operation Charger Validation VBUS Rising VBUS Falling Charge Mode VBAT Rising VBAT Falling VBAT < VSHORT
(6)
5.17 V 5.17 300 1660 2.70 A mA V
VBOOST
Boost Output Voltage at VBUS
IBAT(BOOST) ILIMPK(BST) UVLOBST
Boost Mode Quiescent Current Q2 Peak Current Limit Minimum Battery Voltage for Boost Operation
1380 2.42 2.58 1500 100
VBUS Load Resistance RVBUS VBUS to PGND Resistance K 6.49 V mV A 2.05 40 V mA °C °C s 28.0 34.0 15.0 25 s min %
Protection and Timers VBUSOVP ILIMPK(CHG) VSHORT ISHORT TSHUTDWN TCF tINT t32S t15MIN ∆tLF VBUS Over-Voltage Shutdown Hysteresis Q1 Cycle-by-Cycle Peak Current Limit Battery Short-Circuit Threshold Hysteresis Linear Charging Current Thermal Shutdown Threshold Hysteresis(6) Thermal Regulation Threshold(6) Detection Interval 32-Second Timer(7) 15-Minute Timer Low-Frequency Timer Accuracy Charger Enabled Charger Disabled 15-Minute Mode (FAN5400, FAN5402, FAN5404, FAN5405) Charger Inactive 20.5 18.0 12.0 –25 6.09 6.29 100 2.3 1.95 20 2.00 100 30 145 10 120 2.1 25.2 25.2 13.5
TJ Rising TJ Falling Charge Current Reduction Begins
Notes: 4. Negative current is current flowing from the battery to VBUS (discharging the battery). 5. Q2 always turns on for 60ns, then turns off if current is below ISYNC. 6. Guaranteed by design; not tested in production. 7. This tolerance (%) applies to all timers on the IC, including soft-start and deglitching timers.
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Standard Mode Fast Mode
Conditions
Min.
Typ.
Max. Units
100 400 3400 1700 kHz
fSCL
SCL Clock Frequency
High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode Standard Mode Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode 4.7 1.3 4 600 160 4.7 1.3 160 320 4 600 60 120 4.7 600 160 250 100 10 0 0 0 0 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20 20+0.1CB 20+0.1CB 10 20
tBUF
Bus-Free Time between STOP and START Conditions START or Repeated START Hold Time
s s ns ns s s ns ns s ns ns ns s ns ns ns 3.45 900 70 150 1000 300 80 160 300 300 40 80 1000 300 80 160 ns ns ns s ns ns ns
tHD;STA
tLOW
SCL LOW Period
tHIGH
SCL HIGH Period
tSU;STA
Repeated START Setup Time
Fast Mode High-Speed Mode Standard Mode
tSU;DAT
Data Setup Time
Fast Mode High-Speed Mode Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode Fast Mode High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF
tHD;DAT
Data Hold Time
tRCL
SCL Rise Time
tFCL
SCL Fall Time
tRDA tRCL1
SDA Rise Time Rise Time of SCL after a Repeated START Condition and after ACK Bit
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7 www.fairchildsemi.com 9
FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Timing Specifications
Guaranteed by design.
Symbol
Parameter
Standard Mode Fast Mode
Conditions
Min.
Typ.
Max. Units
300 300 80 160 s ns ns 400 pF ns
20+0.1CB 20+0.1CB 10 20 4 600 160
tFDA
SDA Fall Time
High-Speed Mode, CB < 100pF High-Speed Mode, CB < 400pF Standard Mode
tSU;STO CB
Stop Condition Setup Time Capacitive Load for SDA, SCL
Fast Mode High-Speed Mode
Timing Diagrams
tF tSU;STA
tBUF
SDA
tR TSU;DAT tHIGH tHD;DAT tHD;STA REPEATED START STOP START tHD;STO
SCL
tHD;STA
tLOW
START
Figure 5. I2C Interface Timing for Fast and Slow Modes
tFDA
tRDA
tSU;DAT
REPEATED START
STOP
SDAH
tSU;STA tRCL1 tLOW tHD;STA REPEATED START tFCL tHIGH tHD;DAT note A tRCL tSU;STO
SCLH
= MCS Current Source Pull-up = RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
180 160 900 800
Battery Charge Current (mA)
120 100 80 60 40 20 2.5 3 3.5 Battery Voltage, VBAT (V) 4 4.5
5.5VBUS 5.0VBUS 4.5VBUS
Battery Charge Current (mA)
140
700 600 500 400 300 200 100 2.5 3 3.5 Battery Voltage, VBAT (V) 4 4.5
5.5VBUS 5.0VBUS 4.5VBUS
Figure 7. Battery Charge Current vs. VBUS with IINLIM=100mA
94%
Figure 8. Battery Charge Current vs. VBUS with IINLIM=500mA
94%
92%
92%
88%
4.20VBAT, 4.5VBUS
Efficiency
Efficiency
90%
90%
88%
86%
4.20VBAT, 5.0VBUS 3.54VBAT, 5.0VBUS 3.54VBAT, 4.5VBUS
86%
4.5VBUS 5.0VBUS 5.5VBUS
84% 550 650 750 850 950 1050 1150 1250
84% 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
VBAT Load Current (mA)
Battery Voltage, VBAT (V)
Figure 9. Charger Efficiency, No IINLIM, IOCHARGE=1,250mA
Figure 10. Charger Efficiency vs. VBUS, IINLIM=500mA
Figure 11. Auto-Charge Startup at VBUS Plug-in, IINLIM=100mA, OTG=1, VBAT=3.4V
Figure 12. Auto-Charge Startup at VBUS Plug-in, IINLIM=500mA, OTG=1, VBAT=3.4V
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
Figure 13. AutoCharge Startup with 300mA Limited Charger / Adaptor, IINLIM=500mA, OTG=1, VBAT=3.4V
Figure 14. Charger Startup with HZ_MODE Bit Reset, IINLIM=500mA, IOCHARGE=950mA, OREG=4.2V, VBAT=3.6V
Figure 15. Battery Removal / Insertion during Charging, VBAT=3.9V, IOCHARGE=950mA, No IINLIM, TE=0
Figure 16. Battery Removal / Insertion during Charging, VBAT=3.9V, IOCHARGE=950mA, No IINLIM, TE=1
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Mode Typical Characteristics
Unless otherwise specified, circuit of Figure 1, VOREG=4.2V, VBUS=5.0V, and TA=25°C.
Figure 17. No Battery at VBUS Power-up; FAN5400, FAN5403 Figure 18. No Battery at VBUS Power-up; FAN5402, FAN5405
200
1.82
High-Z Mode Current ( A)
150
1.81
-30C +25C
1.80
100
+85C
VREG (V)
1.79
-10C, 5.0VBUS
50
1.78
+25C, 5.0VBUS +85C, 5.0VBUS
0 4.0 4.5 5.0 Input Voltage, VBUS (V) 5.5 6.0
1.77 0 1 2 3 4 5 1.8V Regulator Load Current (mA)
Figure 19. VBUS Current in High-Impedance Mode with Battery Open
Figure 20. VREG 1.8V Output Regulation
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
100 100
95
95
Efficiency (%)
85
Efficiency (%)
90
90
85
80
2.7VBAT 3.6VBAT 4.2VBAT
80
-10C, 3.6VBAT +25C, 3.6VBAT +85C, 3.6VBAT
75 0 50 100 150 200 250 300
75 0 50 100 150 200 250 300
VBUS Load Current (mA)
VBUS Load Current (mA)
Figure 21. Efficiency vs. VBAT
5.12
2.7VBAT
Figure 22. Efficiency Over Temperature
5.12
-10C, 3.6VBAT
5.09
3.6VBAT 4.2VBAT
5.09
+25C, 3.6VBAT +85C, 3.6VBAT
5.06
5.06
VBUS (V)
5.03
VBUS (V)
5.03
5.00
5.00
4.97
4.97
4.94 0 50 100 150 200 250 300 VBUS Load Current (mA)
4.94 0 50 100 150 200 250 300 VBUS Load Current (mA)
Figure 23. Output Regulation vs. VBAT
250
-30C
Figure 24. Output Regulation Over Temperature
20
Quiescent Current (µA)
+85C
150
High-Z Mode Current (µA)
200
+25C
15
10
100
5
-30C +25C +85C
50 2 2.5 3 3.5 4 4.5 5 Battery Voltage, VBAT (V)
0 2 2.5 3 3.5 4 4.5 5 Battery Voltage, VBAT (V)
Figure 25. Quiescent Current
Figure 26. High-Impedance Mode Battery Current
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
Figure 27. Boost PWM Waveform
30
2.7VBAT 3.6VBAT 4.2VBAT 4.5VBAT
Figure 28. Boost PFM Waveform
30
-30C, 3.6VBAT
25
25
+25C, 3.6VBAT +85C, 3.6VBAT
VBUS Ripple (mVpp)
15
VBUS Ripple (mVpp)
20
20
15
10
10
5
5
0 0 50 100 150 200 250 300 VBUS Load Current (mA)
0 0 50 100 150 200 250 300 VBUS Load Current (mA)
Figure 29. Output Ripple vs. VBAT
Figure 30. Output Ripple vs. Temperature
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode Typical Characteristics
Unless otherwise specified, using circuit of Figure 1, VBAT=3.6V, TA=25°C.
Figure 31. Startup, 3.6VBAT, 44 Load, Additional 10µF, X5R Across VBUS
Figure 32. VBUS Fault Response, 3.6VBAT
Figure 33. Load Transient, 5-155-5mA, tR=tF=100ns
Figure 34. Load Transient, 5-255-5mA, tR=tF=100ns
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Circuit Description / Overview
When charging batteries with a current-limited input source, such as USB, a switching charger’s high efficiency over a wide range of output voltages minimizes charging time. FAN540X combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5V to USB On-The-Go (OTG) peripherals. The regulator employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. The FAN540X has three operating modes: 1. 2. Charge Mode: Charges a single-cell Li-ion or Li-polymer battery. Boost Mode: Provides 5V power to USB-OTG with an integrated synchronous rectification boost regulator using the battery as input. High-Impedance Mode: Both the boost and charging circuits are OFF in this mode. Current flow from VBUS to the battery or from the battery to VBUS is blocked in this mode. This mode consumes very little current from VBUS or the battery. with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. The FAN540X is designed to work with a current-limited input source at VBUS. During the current regulation phase of charging, IINLIM or the programmed charging current limits the amount of current available to charge the battery and power the system. The effect of IINLIM on ICHARGE can be seen in Figure 36.
VOREG
IOCHARGE
ICHARGE
V BA
T
VSHORT
ITERM
3.
ISHORT
PRECHARGE
CURRENT REGULATION
VOLTAGE REGULATION
Note: Default settings are denoted by bold typeface. Figure 35. Charge Curve, ICHARGE Not Limited by IINLIM
Charge Mode
In Charge Mode, FAN540X employs four regulation loops: 1. Input Current: Limits the amount of current drawn from VBUS. This current is sensed internally and can be programmed through the I2C interface. Charging Current: Limits the maximum charging current. This current is sensed using an external RSENSE resistor. Charge Voltage: The regulator is restricted from exceeding this voltage. As the internal battery voltage rises, the battery’s internal impedance and RSENSE work in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery. Battery charging is completed when the voltage across RSENSE drops below the ITERM threshold. Temperature: If the IC’s junction temperature reaches 120°C, charge current is continuously reduced until the IC’s temperature stabilizes at 120°C.
VOREG
V BA
T
IC
H AR GE
2. 3.
VSHORT
ITERM
ISHORT
PRECHARGE
CURRENT REGULATION
VOLTAGE REGULATION
4.
Figure 36. Charge Curve, IINLIM Limits ICHARGE Assuming that VOREG is programmed to the cell’s fully charged “float” voltage, the current that the battery accepts with the PWM regulator limiting its output (sensed at VBAT) to VOREG declines, and the charger enters the voltage regulation phase of charging. When the current declines to the programmed ITERM value, the charge cycle is complete. Charge current termination can be disabled by resetting the TE bit (REG1[3]). The charger output or “float” voltage can be programmed by the OREG bits from 3.5V to 4.44V in 20mV increments, as shown in Table 3.
In addition, the FAN5403-05 employ an additional loop to limit the amount of drop on VBUS to a programmable voltage (VSP) to accommodate “special chargers” that limit current to a lower current than might be available from a “normal” USB wall charger.
Battery Charging Curve
If the battery voltage is below VSHORT, a linear current source pre-charges the battery until VBAT reaches VSHORT. The PWM charging circuit is then started and the battery is charged
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 3. OREG Bits (OREG[7:2]) vs. Charger VOUT (VOREG) Float Voltage Decimal Hex VOREG
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 3.50 3.52 3.54 3.56 3.58 3.60 3.62 3.64 3.66 3.68 3.70 3.72 3.74 3.76 3.78 3.80 3.82 3.84 3.86 3.88 3.90 3.92 3.94 3.96 3.98 4.00 4.02 4.04 4.06 4.08 4.10
A new charge cycle begins when one of the following occurs: The battery voltage falls below VOREG - VRCH VBUS Power On Reset (POR) clears and the battery voltage is below the weak battery threshold (VLOWV). This occurs for all versions except the FAN5401.
Decimal Hex VOREG
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 4.14 4.16 4.18 4.20 4.22 4.24 4.26 4.28 4.30 4.32 4.34 4.36 4.38 4.40 4.42 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44 4.44
CE or HZ_MODE is reset through I2C write to CONTROL1 (R1) register.
Charge Current Limit (IOCHARGE)
Table 5. IOCHARGE (REG4 [6:4]) Current as Function of IOCHARGE Bits and RSENSE Resistor Values DEC
0 1 2 3 4 5 6 7
BIN
000 001 010 011 100 101 110 111
HEX
00 01 02 03 04 05 06 07
VRSENSE (mV)
37.4 44.2 51.0 57.8 64.6 71.4 78.2 85.0
IOCHARGE (mA) 68m
550 650 750 850 950 1050 1150 1250
100m
374 442 510 578 646 714 782 850
Termination Current Limit
Current charge termination is enabled when TE (REG1[3])=1. Typical termination current values are given in Table 6.
Table 6. ITERM Current as Function of ITERM Bits (REG4[2:0]) and RSENSE Resistor Values FAN5400 - FAN5402 ITERM
0 1 2 3 4 5 6 7
FAN5403 - FAN5405
ITERM (mA) ITERM (mA) VRSENSE VRSENSE (mV) 68m 100m (mV) 68m 100m
3.4 6.8 10.2 13.6 17.0 20.4 23.8 27.2 50 100 150 200 250 300 350 400 34 68 102 136 170 204 238 272 3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 49 97 146 194 243 291 340 388 33 66 99 132 165 198 231 264
The following charging parameters can be programmed by the host through I2C:
Table 4. Programmable Charging Parameters Parameter
Output Voltage Regulation Battery Charging Current Limit Input Current Limit Charge Termination Limit Weak Battery Voltage
Name
VOREG IOCHRG IINLIM ITERM VLOWV
Register
REG2[7:2] REG4[6:4] REG1[7:6] REG4[2:0] REG1[5:4]
When the charge current falls below ITERM, PWM charging stops and the STAT bits change to READY (00) for about 500ms while the IC determines whether the battery and charging source are still connected. STAT then changes to CHARGE DONE (10), provided the battery and charger are still connected.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
PWM Controller in Charge Mode
The IC uses a current-mode PWM controller to regulate the output voltage and battery charge currents. The synchronous rectifier (Q2) has a negative current limit that turns off Q2 at 140mA to prevent current flow from the battery.
USB-Friendly Boot Sequence
For all versions except FAN5401, FAN5404 At VBUS POR, when the battery voltage is above the weak battery threshold (VLOWV), the IC operates in accordance with its I2C register settings. If VBAT < VLOWV, the IC sets all registers to their default values and enables the charger using an input current limit controlled by the OTG pin (100mA if OTG is LOW and 500mA if OTG is HIGH). This feature can revive a battery whose voltage is too low to ensure reliable host operation. Charging continues in the absence of host communication even after the battery has reached VOREG, whose default value is 3.54V, and the charger remains active until t15MIN times out. Once the host processor begins writing to the IC, charging parameters are set by the host, which must continually reset the t32S timer to continue charging using the programmed charging parameters. If t32S.times out, the register defaults are loaded, the FAULT bits are set to 110, STAT is pulsed HIGH, and charging continues with default charge parameters. The FAN5401 and FAN5404 do not automatically initiate charging at VBUS POR. Instead, they wait for the host to initiate charging through I2C commands.
Safety Timer
This section references Figure 41 and Figure 42. At the beginning of charging, the IC starts a 15-minute timer (t15MIN ). When this timer times out, charging is terminated. 2 Writing to any register through I C stops and resets the t15MIN timer, which in turn starts a 32-second timer (t32S). Setting the TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S timer times out, charging is terminated, the registers are set to their default values, and charging resumes using the default values with the t15MIN timer running. Normal charging is controlled by the host with the t32S timer running to ensure that the host is alive. Charging with the t15MIN timer running is used for charging that is unattended by the host. If the t15MIN timer expires, the IC turns off the charger, sets the CE bit, and indicates a timer fault (110) on the FAULT bits (REG0[2:0]). This sequence prevents overcharge if the host fails to reset the t32S timer.
Input Current Limiting
To minimize charging time without overloading VBUS current limitations, the IC’s input current limit can be programmed by the IINLIM bits (REG1[7:6]).
VBUS POR / Non-Compliant Charger Rejection
When the IC detects that VBUS has risen above VIN(MIN)1 (4.4V), the IC applies a 110 load from VBUS to GND. To clear the VBUS POR (Power-On-Reset) and begin charging, VBUS must remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID (30ms) before the IC initiates charging. The VBUS validation sequence always occurs before charging is initiated or re-initiated (for example, after a VBUS OVP fault or a VRCH recharge initiation). tVBUS_VALID ensures that unfiltered 50/60hz chargers and other non-compliant chargers are rejected.
Table 7. Input Current Limit IINLIM REG1[7:6]
00 01 10 11
Input Current Limit
100mA 500mA 800mA No limit
For all versions except the FAN5401 and FAN5404, the OTG pin establishes the input current limit when t15MIN is running. For the FAN5401 and FAN5404, no charging occurs automatically at VBUS POR, so the input current limit is established by the IINLIM bits.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Flow Charts
Figure 37. Charger VBUS POR
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
CHARGE STATE
Disable Charging Indicate VBUS Fault Enable ISHORT , Reset Safety reg Indicate Charging NO NO
VBAT < VSHORT
YES
VBUS OK?
NO
YES
PWM Charging VBUS OK? YES Indicate Charging
T15MIN Timeout?
NO Disable Charging Indicate VBUS Fault
YES Indicate timer fault YES Set CE Charge Configuration State
T15MIN Timeout?
NO
NO
HIGHZ mode NO IOUT < ITERM Termination enabled VBAT > VOREG–VRCH Indicate Charge Complete VBAT < VOREG–VRCH YES
NO YES Battery Removed VBAT < VOREG–VRCH Enable IDET for TDETECT YES Reset charge parameters
Reset Safety reg Delay tINT
Stop Charging
Figure 38. Charge Mode
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Figure 39. Charge Configuration
Figure 40. HZ-State
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Charge Start
Start T15MIN
Reset Registers
YES T32SEC Expired?
NO Start T32SEC Stop T15MIN T15MIN Active? YES
YES
NO I2C Write received? T15MIN Expired?
NO
NO
Continue Charging
Timer Fault : Set CE CE
YES
Figure 41. Timer Flow Chart for FAN5400, FAN5402, FAN5403, FAN5405
Charge Start from Host control
Reset T32SEC
Charge
T32SEC Expired?
YES
Timer Fault Stop Charging and Reset Registers
NO NO YES TMR_RST bit Set?
Figure 42. Timer Flow Chart for FAN5401, FAN5404
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Special Charger
FAN5403-05 Only The FAN5403, FAN5404, and FAN5405 have additional functionality to limit input current in case a current-limited “special charger” is supplying VBUS. The FAN5403-05 slowly increases the charging current until either: or VBUS=VSP. IINLIM or IOCHARGE is reached
Table 9. ISAFE (IOCHARGE Limit) as Function of ISAFE Bits (REG6[6:4]) ISAFE (REG6[6:4]) DEC
0 1 2 3 4 5 6 7
BIN
000 001 010 011 100 101 110 111
HEX
00 01 02 03 04 05 06 07
VRSENSE (mV)
37.4 44.2 51.0 57.8 64.6 71.4 78.2 85.0
ISAFE (mA) 68m
550 650 750 850 950 1050 1150 1250
100m
374 442 510 578 646 714 782 850
If VBUS collapses to VSP when the current is ramping up, the FAN5403-05 charge with an input current that keeps VBUS=VSP. When the VSP control loop is limiting the charge current, the SP bit (REG5[4]) is set.
Table 8. VSP as Function of SP Bits (REG5[2:0]) SP (REG5[2:0]) DEC
0 1 2 3 4 5 6 7
BIN
000 001 010 011 100 101 110 111
HEX
00 01 02 03 04 05 06 07
VSP
4.213 4.293 4.373 4.453 4.533 4.613 4.693 4.773
Table 10. VSAFE (VOREG Limit) as Function of VSAFE Bits (REG6[3:0]) VSAFE (REG6[3:0]) DEC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BIN
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
HEX
00 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Max. OREG (REG2[7:2])
100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010
VOREG Max.
4.20 4.22 4.24 4.26 4.28 4.30 4.32 4.34 4.36 4.38 4.40 4.42 4.44 4.44 4.44 4.44
Safety Settings
FAN5403-FAN5405 Only The FAN5403-05 contain a SAFETY register (REG6) that prevents the values in OREG (REG2[7:2]) and IOCHARGE (REG4[6:4]) from exceeding the values of the VSAFE and ISAFE values. After VBAT exceeds VSHORT, the SAFETY register is loaded with its default value and may be written only before any other register is written. After writing to any other register, the SAFETY register is locked until VBAT falls below VSHORT. The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0]) registers establish values that limit the maximum values of IOCHARGE and VOREG used by the control logic. If the host attempts to write a value higher than VSAFE or ISAFE to OREG or IOCHARGE, respectively; the VSAFE, ISAFE value appears as the OREG, IOCHARGE register value, respectively.
Thermal Regulation and Protection
When the IC’s junction temperature reaches TCF (about 120°C), the charger reduces its output current to 550mA to prevent overheating. If the temperature increases beyond TSHUTDOWN; charging is suspended, the FAULT bits are set to 101, and STAT is pulsed HIGH. In Suspend Mode, all timers stop and the state of the IC’s logic is preserved. Charging resumes at programmed current after the die cools to about 120°C.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Additional JA data points, measured using the FAN540X evaluation board, are given in Table 11 (measured with TA=25°C). Note that as power dissipation increases, the effective JA decreases due to the larger difference between the die temperature and its ambient.
Table 11. FAN5400 Evaluation Board Measured JA
Power (W) 0.504 0.844 1.506 JA 54°C/W 50°C/W 46°C/W
Battery Detection During Charging The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set. During normal charging, once VBAT is close to VOREG and the termination charge current is detected, the IC terminates charging and sets the STAT bits to 10. It then turns on a discharge current, IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH, the battery is present and the IC sets the FAULT bits to 000. If VBAT is below VOREG – VRCH, the battery is absent and the IC: 1. 2. 3. Sets the registers to their default values. Sets the FAULT bits to 111. Resumes charging with default values after tINT.
Charge Mode Input Supply Protection
Sleep Mode When VBUS falls below VBAT + VSLP, and VBUS is above VIN(MIN), the IC enters Sleep Mode to prevent the battery from draining into VBUS. During Sleep Mode, reverse current is disabled by body switching Q1. Input Supply Low-Voltage Detection The IC continuously monitors VBUS during charging. If VBUS falls below VIN(MIN), the IC: 1. 2. Terminates charging Pulses the STAT pin, sets the STAT bits to 11, and sets the FAULT bits to 011.
Battery Short-Circuit Protection If the battery voltage is below the short-circuit threshold (VSHORT); a linear current source, ISHORT, supplies VBAT until VBAT > VSHORT. Battery Detection During Power-up For FAN5400 and FAN5403 At VBUS POR, a 5K load is applied to VBAT for 500ms to discharge any residual system capacitance in case the battery is absent. If VBAT < VSHORT, linear charging commences. When VBAT rises above VSHORT, PWM charging proceeds with the float voltage (OREG) temporarily set to 4V. If the battery voltage exceeds 3.7V within 32ms of the beginning of PWM charging, the battery is absent. If battery absent is detected: 1. 2. High-Impedance Mode is entered. FAULT bits are set to 111.
If VBUS recovers above the VIN(MIN) rising threshold after time tINT (about two seconds), the charging process is repeated. This function prevents the USB power bus from collapsing or oscillating when the IC is connected to a suspended USB port or a low-current-capable OTG device. Input Over-Voltage Detection When the VBUS exceeds VBUSOVP, the IC: 1. 2. 3. Turns off Q3 Suspends charging Sets the FAULT bits to 001, sets the STAT bits to 11, and pulses the STAT pin.
3. The t15MIN timer is disabled until VBUS is removed. If VBAT remains below 3.7V during the initial 32ms period, the float voltage returns to the OREG register setting and PWM charging continues.
System Operation with No Battery
The FAN5402 and FAN5405 continue charging after VBUS POR with the default parameters, regulating the VBAT line to 3.54V until the host processor issues commands or the 15minute timer expires. In this way, the FAN5402 and FAN5405 can start the system without a battery. The FAN540X soft-start function can interfere with the system supply with battery absent. The soft-start activates whenever VOREG, IINLIM, or IOCHARGE are set from a lower to higher value. During soft-start, the IIN limit drops to 100mA for about 1ms unless IINLIM is set to 11 (no limit). This could cause the system processor to fail to start. To avoid this behavior, use the following sequence. 1. Set the OTG pin HIGH. When VBUS is plugged in, IINLIM is set to 500mA until the system processor powers up and can set parameters through I2C. 2. Program the Safety Register. 3. Set IINLIM to 11 (no limit). 4. Set OREG to the desired value (typically 4.18). 5. Reset the IOLEVEL bit, then set IOCHARGE. 6. Set IINLIM to 500mA if a USB source is connected.
When VBUS falls about 150mV below VBUSOVP, the fault is cleared and charging resumes after VBUS is revalidated (see VBUS POR / Non-Compliant Charger Rejection). VBUS Short While Charging If VBUS is shorted with a very low impedance while the IC is charging with IINLIMIT=100mA, the IC may not meet datasheet specifications until power is removed. To trigger this condition, VBUS must be driven from 5V to GND with a high slew rate. Achieving this slew rate requires a 0 short to the USB cable less than 10cm from the connector.
Charge Mode Battery Detection & Protection
VBAT Over-Voltage Protection The OREG voltage regulation loop prevents VBAT from overshooting the OREG voltage by more than 50mV when the battery is removed. When the PWM charger runs with no battery, the TE bit is not set and a battery is inserted that is charged to a voltage higher than VOREG; PWM pulses stop. If no further pulses occur for 30ms, the IC sets the FAULT bits to 100, sets the STAT bits to 11, and pulses the STAT pin.
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
During the initial system startup, while the charger IC is being programmed, the system current is limited to 325mA for 1ms during steps 4 and 5. This is the value of the softstart ICHARGE current used when IINLIM is set to No Limit. If the system is powered up without a battery present, the CV bit should be set. When a battery is inserted, the CV bit is cleared. Charger Status / Fault Status The STAT pin indicates the operating condition of the IC and provides a fault indicator for interrupt driven systems.
Charge Mode Control Bits
Setting either HZ_MODE or CE through I2C disables the charger and puts the IC into High-Impedance Mode and resets t32S. If VBAT < VLOWV while in High-Impedance Mode, t32S begins running and, when it overflows, all registers (except SAFETY) reset, which enables t15MIN charging on versions with the 15-minute timer. When t15MIN overflows, the IC sets the CE bit and the IC enters High-Impedance Mode. If CE was set by t15MIN overflow, a new charge cycle can only be initiated through I2C or VBUS POR. Setting the RESET bit clears all registers. If HZ_MODE or
Table 12. STAT Pin Function EN_STAT
0 X 1 X
Charge State
X Normal Conditions Charging Fault (Charging or Boost)
STAT Pin
OPEN OPEN LOW 128s Pulse, then OPEN
CE bits were set when the RESET bit is set, these bits are also cleared, but the t32S timer is not started, and the IC remains in High-Impedance Mode.
Table 14. FAN5403–FAN5405 DISABLE Pin and CE Bit Functionality Charging
ENABLE DISABLE DISABLE DISABLE
The FAULT bits (R0[2:0]) indicate the type of fault in Charge Mode (see Table 13).
DISABLE Pin
0 X X 1
CE
0 1 X X
HZ_MODE
0 X 1 X
Table 13. Fault Status Bits During Charge Mode Fault Bit B2
0 0 0 0 1 1 1 1
B1
0 0 1 1 0 0 1 1
B0
0 1 0 1 0 1 0 1
Fault Description
Normal (No Fault) VBUS OVP Sleep Mode Poor Input Source Battery OVP Thermal Shutdown Timer Fault No Battery
Raising the DISABLE pin stops t32S from advancing, but does not reset it. If the DISABLE pin is raised during t15MIN charging, the t15MIN timer is reset. Operational Mode Control OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1]) bits in conjunction with the FAULT state define the operational mode of the charger.
Table 15. Operation Mode Control HZ_MODE OPA_MODE FAULT Operation Mode
0 0 0 1 0 X 1 X 0 1 0 X Charge Charge Configure Boost High Impedance
The IC resets the OPA_MODE bit whenever the boost is deactivated, whether due to a fault or being disabled by setting the HZ_MODE bit.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Boost Mode
Boost Mode can be enabled if the IC is in 32-Second Mode with the OTG pin and OPA_MODE bits as indicated in Table 16. The OTG pin ACTIVE state is 1 if OTG_PL=1 and 0 when OTG_PL=0. If boost is active using the OTG pin, Boost Mode is initiated even if the HZ_MODE=1. The HZ_MODE bit overrides the OPA_MODE bit.
VBUS as a function of ILOAD can be computed when the regulator is in PWM Mode (continuous conduction) as:
VOUT 5.07 ROUT ILOAD
At VBAT=3.3V, and ILOAD=200mA, VBUS would drop to:
EQ. 1
VOUT 5.07 0.26 0.2 5.018V
EQ. 1A
At VBAT=2.7V, and ILOAD=200mA, VBUS would drop to:
Table 16. Enabling Boost OTG_EN
1 X X 0 1 0
OTG Pin
ACTIVE
X
HZ_ MODE
X 0 X 1 1 0
OPA_ MODE
X 1 0 X 1 0
VOUT 5.07 0.327 0.2 5.005V
BOOST
Enabled Enabled Disabled Disabled Disabled Disabled
EQ. 1B
PFM Mode
If VBUS > VREFBOOST (nominally 5.07V) when the minimum off-time has ended, the regulator enters PFM Mode. Boost pulses are inhibited until VBUS < VREFBOOST. The minimum on-time is increased to enable the output to pump up sufficiently with each PFM boost pulse. Therefore the regulator behaves like a constant on-time regulator, with the bottom of its output voltage ripple at 5.07V in PFM Mode.
ACTIVE
X
ACTIVE
ACTIVE
Table 17. Boost PWM Operating States Mode
LIN SS BST
To remain in Boost Mode, the TMR_RST must be set by the host before the t32S timer times out. If t32S times out in Boost Mode; the IC resets all registers, pulses the STAT pin, sets the FAULT bits to 110, and resets the BOOST bit. VBUS POR or reading R0 clears the fault condition.
Description
Linear Startup Boost Soft-Start Boost Operating Mode
Invoked When
VBAT > VBUS VBUS < VBST VBAT > UVLOBST and SS Completed
Boost PWM Control
The IC uses a minimum on-time and computed minimum offtime to regulate VBUS. The regulator achieves excellent transient response by employing current-mode modulation. This technique causes the regulator to exhibit a load line. During PWM Mode, the output voltage drops slightly as the input current rises. With a constant VBAT, this appears as a constant output resistance. The “droop” caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. This can be seen in Figure 33 and Figure 43.
350 325 Output Resistance (m) 300 275 250 225 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Startup
When the boost regulator is shut down, current flow is prevented from VBAT to VBUS, as well as reverse flow from VBUS to VBAT.
LIN State
When EN rises, if VBAT > UVLOBST, the regulator first attempts to bring PMID within 400mV of VBAT using an internal 450mA current source from VBAT (LIN State). If PMID has not achieved VBAT – 400mV after 560s, a FAULT state is initiated.
SS State
When PMID > VBAT – 400mV, the boost regulator begins switching with a reduced peak current limit of about 50% of its normal current limit. The output slews up until VBUS is within 5% of its set point; at which time, the regulation loop is closed and the current limit is set to 100%. If the output fails to achieve 95% of its set point (VBST) within 128s, the current limit is increased to 100%. If the output fails to achieve 95% of its set point after this second 384s period, a fault state is initiated.
Battery Voltage, VBAT (V)
Figure 43. Output Resistance (ROUT)
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
BST State
This is the normal operating mode of the regulator. The regulator uses a minimum tOFF-minimum tON modulation scheme. The minimum tOFF is proportional to
VIN , which VOUT
VREG Pin
The VREG pin on FAN5400 - FAN5402 provides a voltage protected from over-voltage surges on VBUS, which can be used to run auxiliary circuits. This voltage is essentially a current-limited replica of PMID. The maximum voltage on this node is 5.9V. FAN5403-FAN5405 provide a 1.8V regulated output on this 2 pin, which can be disabled through I C by setting the DIS_VREG bit (REG5[6]). VREG can supply up to 2mA. This circuit, which is powered from PMID, is enabled only when PMID > VBAT and does not drain current from the battery. During boost, VREG is off. It is also off when the HZ_MODE bit (REG1[1])=1.
keeps the regulator’s switching frequency reasonably constant in CCM. tON(MIN) is proportional to VBAT and is a higher value if the inductor current reached 0 before tOFF(MIN) in the prior cycle. To ensure the VBUS does not pump significantly above the regulation point, the boost switch remains off as long as FB > VREF.
Boost Faults
If a BOOST fault occurs: 1. The STAT pin pulses. 2. OPA_MODE bit is reset. 3. The power stage is in High-Impedance Mode. 4. The FAULT bits (REG0[2:0]) are set per Table 18.
Monitor Register (Reg10H)
Additional status monitoring bits enable the host processor to have more visibility into the status of the IC. The monitor bits are real-time status indicators and are not internally debounced or otherwise time qualified. The state of the MONITOR register bits listed in HighImpedance Mode are only valid when VBUS is valid.
Restart After Boost Faults
If boost was enabled with the OPA_MODE bit and OTG_EN=0, Boost Mode can only be enabled through subsequent I2C commands since OPA_MODE is reset on boost faults. If OTG_EN=1 and the OTG pin is still ACTIVE (see Table 16), the boost restarts after a 5.2ms delay, as shown in Figure 44. If the fault condition persists, restart is attempted every 5ms until the fault clears or an I2C command disables the boost.
Table 18. Fault Bits During Boost Mode Fault Bit B2 B1 B0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Fault Description
Normal (no fault) VBUS > VBUSOVP VBUS fails to achieve the voltage required to advance to the next state during soft-start or sustained (>50s) current limit during the BST state. VBAT < UVLOBST N/A: This code does not appear. Thermal shutdown Timer fault; all registers reset. N/A: This code does not appear.
VBUS 0 BATTERY CURRENT BOOST ENABLED
450mA 0 560 5200
64
Figure 44. Boost Response Attempting to Start into VBUS Short Circuit (Times in s)
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 19. MONITOR Register Bit Definitions BIT#
MONITOR 7
NAME
0 Address 10H VCSIN – VBAT < VITERM VCSIN – VBAT < 1mV VBAT < VSHORT VBAT < VLOWV VBAT < UVLOBST Linear Charging Not Enabled TJ < 120° Charging Current Controlled by ICHARGE Control Loop IBUS Limiting Charging Current VBUS Not Valid Constant Current Charging
STATE
1 VCSIN – VBAT > VITERM VCSIN – VBAT > 1mV VBAT > VSHORT VBAT > VLOWV VBAT > UVLOBST Linear Charging Enabled TJ > 120° Charging Current Not Controlled by ICHARGE Control Loop Charge Current Not Limited by IBUS VBUS is Valid Constant Voltage Charging
Active When
ITERM_CMP
Charging with TE=1 Charging with TE=0 Charging High-Impedance Mode Boosting Charging
6 5 4 3 2 1 0
VBAT_CMP LINCHG T_120 ICHG IBUS VBUS_VALID CV
Charging Charging VBUS > VBAT Charging
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
I2C Interface
The FAN540X’s serial interface is compatible with Standard, Fast, Fast Plus, and High-Speed Mode I2C-Bus® specifications. The FAN540X’s SCL line is an input and its SDA line is a bi-directional open-drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and when signaling ACK. All data is shifted in MSB (bit 7) first.
Slave Releases Master Drives tHD;STO ACK(0) or NACK(1)
SDA
SCL
Slave Address
Table 20. I C Slave Address Byte Part Types
FAN5400–FAN5404 FAN5405
2
Figure 47. Stop Bit During a read from the FAN540X (Figure 50), the master issues a Repeated Start after sending the register address and before resending the slave address. The Repeated Start is a 1-to-0 transition on SDA while SCL is HIGH, as shown in Figure 48.
7654321
1 1 1 1 0 0 1 1 0 0 1 1 1 0
0
R/ W
R/ W
In hex notation, the slave address assumes a 0 LSB. The hex slave address for the FAN5405 is D4H and is D6H for all other parts in the family.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and Fast-Speed (FS) Modes are identical except the bus speed for HS Mode is 3.4MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus Mode (less than 1MHz clock); slaves do not ACK this transmission. The master then generates a repeated start condition (Figure 48) that causes all slaves on the bus to switch to HS 2 Mode. The master then sends I C packets, as described above, using the HS Mode clock rate and timing. The bus remains in HS Mode until a stop bit (Figure 47) is sent by the master. While in HS Mode, packets are separated by repeated start conditions (Figure 48).
Slave Releases tSU;STA tHD;STA SLADDR MS Bit ACK(0) or NACK(1)
Bus Timing
As shown in Figure 45, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the next SCL rising edge.
Data change allowed
SDA
TH
SCL
TSU
SDA
Figure 45. Data Transfer Timing Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 46.
SDA
THD;STA Slave Address MS Bit
SCL
Figure 48. Repeated Start Timing
SCL
Figure 46. Start Bit A transaction ends with a STOP condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 47.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Read and Write Transactions
The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined as All addresses
M aster Drives Bus
Table 21. Bit Definitions for Figure 49, Figure 50 Symbol
S A
A
and
and data are
S lave Drives Bus
MSB
. first.
Definition
START, see Figure 46. ACK. The slave drives SDA to 0 to acknowledge the preceding packet. NACK. The slave sends a 1 to NACK the preceding packet. Repeated START, see Figure 48 STOP, see Figure 47
R P
7 bits
S Slave Address 0
0 A
8 bits
Reg Addr
0 A
8 bits
Data
0 A P
Figure 49. Write Transaction
7 bits
S Slave Address 0
0 A
8 bits
Reg Addr
0 A R
7 bits
Slave Address 1
0 A
8 bits
Data
1 A P
Figure 50. Read Transaction
© 2009 Fairchild Semiconductor Corporation FAN5400 Family • Rev. 1.0.7
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Register Descriptions
The FAN5400-FAN5402 have seven user-accessible registers; the FAN5403-05 have an additional two registers, as defined in Table 22.
Table 22. I2C Register Address
IC Register Name CONTROL0 CONTROL1 OREG ALL IC_INFO IBAT FAN5403-FAN5405 ALL SP_CHARGER SAFETY MONITOR REG# 0 1 2 03 or 3BH 4 5 6 10H 7 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 Address Bits 4 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 1 2 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0
Table 23. Register Bit Definitions
This table defines the operation of each register bit for all IC versions. Default values are in bold text.
Bit
Name
TMR_RST OTG EN_STAT
Value
Type
Register Address: 00 W R R/W
Description
Default Value=X1XX 0XXX Writing a 1 resets the t32S timer; writing a 0 has no effect Returns the OTG pin level (1=HIGH) Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults Enables STAT pin LOW when IC is charging Ready Charge in progress Charge done Fault
CONTROL0 7 1 0 1 00 5:4 STAT 01 10 11 3 2:0 BOOST FAULT 0 1 R R R
6
IC is not in Boost Mode IC is in Boost Mode Fault status bits: for Charge Mode, see Table 13; for Boost Mode: see Table 18
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 23. Register Bit Definitions (Continued) Bit
7:6
Name
IINLIM
Value
Type
Register Address: 01 R/W Input current limit, see Table 7 3.4V 3.5V 3.6V 3.7V R/W R/W R/W R/W
Description
Default Value=0011 0000 (30H)
CONTROL1 00 5:4 VLOWV 01 10 11 3 2 1 0 OREG 7:2 1 0 IC_INFO 7:5 4:3 2:0 IBAT 7 6:4 3 2:0 RESET IOCHARGE Reserved ITERM 1 Table 5 1 Table 6 W R/W R R/W Vendor Code PN REV 100 R R R OREG OTG_PL OTG_EN 0 1 0 1 R/W R/W R/W TE
CE
R/W
Weak battery voltage threshold
0 1 0 1 0 1 0 1
Disable charge current termination Enable charge current termination Charger enabled Charger disabled Not High-Impedance Mode High-Impedance Mode Charge Mode Boost Mode Register Address: 02 Default Value=0000 1010 (0AH) Charger output “float” voltage; programmable from 3.5 to 4.44V in 20mV increments; defaults to 000010 (3.54V), see Table 3 OTG pin active LOW OTG pin active HIGH Disables OTG pin Enables OTG pin Register Address: 03 or 3B Default Value=100X XXXX Identifies Fairchild Semiconductor as the IC supplier Part number bits, see the Ordering Info on page 1 IC Revision, revision 1.X, where X is the decimal of these three bits Register Address: 04 Default Value=1000 1001 (89H) Writing a 1 resets charge parameters, except the Safety register (Reg6), to their defaults: writing a 0 has no effect; read returns 1 Programs the maximum charge current, see Table 5 Unused Sets the current used for charging termination, see Table 6 See Table 16
HZ_MODE OPA_MODE
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Table 23. Register Bit Definitions (Continued)
SP_CHARGER (FAN5403 – FAN5405) 7 6 Reserved DIS_VREG 0 0 1 0 5 IO_LEVEL 1 0 1 0 1 Table 8 0 Table 9 Table 10 R/W R R/W R/W R R R See Table 19 R R R R R R R R/W R R/W Register Address: 05 Unused 1.8V regulator is ON 1.8V regulator is OFF Output current is controlled by IOCHARGE bits Voltage across RSENSE for output current control is set to 22.1mV (325mA for RSENSE=68m, 221mA for 100m) Special charger is not active (VBUS is able to stay above VSP) Special charger has been detected and VBUS is being regulated to VSP DISABLE pin is LOW DISABLE pin is HIGH Special charger input regulation voltage, see Table 8 Register Address: 06 Default Value=0100 0000 (40H) Bit disabled and always returns 0 when read back Sets the maximum IOCHARGE value used by the control circuit, see Table 9 Sets the maximum VOREG used by the control circuit, see Table 10 Register Address: 10H (16) Output of VBAT comparator 30mA linear charger ON Thermal regulation comparator; when=1 and T_145=0, the charge current is limited to 22.1mV across RSENSE 0 indicates the ICHARGE loop is controlling the battery charge current 0 indicates the IBUS (input current) loop is controlling the battery charge current 1 indicates VBUS has passed validation and is capable of charging 1 indicates the constant-voltage loop (OREG) is controlling the charger and all current limiting loops have released See Table 19 ITERM comparator output, 1 when VRSENSE > ITERM reference Default Value=001X X100
4 3 2:0 7 6:4 3:0 MONITOR 7 6 5 4 3 2 1 0
SP EN_LEVEL VSP Reserved ISAFE VSAFE ITERM_CMP VBAT_CMP LINCHG T_120 ICHG IBUS VBUS_VALID CV
SAFETY (FAN5403 – FAN5405)
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
PCB Layout Recommendations
Bypass capacitors should be placed as close to the IC as possible. In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. All power and ground pins must be routed to their bypass capacitors using top copper if possible. Copper area connecting to the IC should be maximized to improve thermal performance.
Figure 51. PCB Layout Recommendations
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
Physical Dimensions
BALL A1 INDEX AREA 0.03 C 2X D 1.60 0.40 E A F B A1 1.20 Ø0.20 Cu Pad
Ø0.30 Solder Mask Opening 0.40
0.03 C 2X
TOP VIEW
RECOMMENDED LAND PATTERN (NSMD TYPE)
0.06 C
0.05 C
0.625 0.547
E
0.378±0.018 0.208±0.021
C D
SEATING PLANE
SIDE VIEWS
NOTES:
1.20 0.40 E D C B A 1234 F (X) ±0.018 0.005 Ø0.260±0.02 20X CAB
A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 1994. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS ±39 MICRONS (547-625 MICRONS). F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. G. DRAWING FILNAME: MKT-UC020AArev2.
1.60 0.40
(Y) ±0.018
BOTTOM VIEW
Figure 52. 20-Ball WLCSP, 4X5 Array, 0.4mm Pitch, 250µm Ball
Product-Specific Dimensions
Product
FAN540XUCX
D
1.960 +0.030
E
1.870 +0.030
X
0.335
Y
0.180
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
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FAN5400 Family — USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator
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