FAN6204

FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification November 2010 FAN6204 Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Features SR Controller Suited for Flyback Converter in QR, DCM, and CCM Operation Suited for Forward Freewheeling Rectification Internal Green Mode for Lower No-Load Power Consumption and Higher Light-Load Efficiency PWM Frequency Tracking with Secondary-Side Winding Voltage Detection Ultra-Low VDD Operating Voltage for Various Output Voltage Applications (5V~24V) Ultra-Low Green Mode Operating Current: 1.1mA Typical VDD Pin Over-Voltage Protection (OVP) 12V (Typical) Gate Driver Clamp 8-Pin SOP Package Description FAN6204 is a secondary-side synchronous rectification (SR) controller to drive SR MOSFET for improving efficiency. The IC is suitable for flyback converters and forward free-wheeling rectification. FAN6204 can be applied in continuous or discontinuous conduction mode (CCM and DCM) and quasi-resonant (QR) flyback converters based on the proprietary innovative linear-predict timing-control technique. The benefits of this technique include a simple control method without current-sense circuitry to accomplish noise immunity. With PWM frequency tracking and secondary-side winding voltage detection, FAN6204 can operate in both fixed- and variable-frequency systems. In Green Mode, the SR controller stops all SR switching operation to reduce the operating current. Power consumption is maintained at minimum level in lightload condition. Applications AC/DC NB Adapters Open-Frame SMPS Battery Charger Ordering Information Part Number FAN6204MY Operating Temperature Range -40°C to +105°C Package 8-Pin, Small Outline Package (SOP) Packing Method Tape & Reel © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Application Diagrams Figure 1. Typical Application Circuit for Flyback Converter Figure 2. Typical Application Circuit for Forward Freewheeling Rectification Internal Block Diagram GATE 3 VDD 5 950K 0.05VDD 50K 4.8V/4.5V Internal Bias + + OVP Green Mode tDIS Q PWM Block Drive Calculate VLPC-EN VLPC-EN 2V 27.5V/25.4V 1 AGND 2 AGND 6 AGND S LPC 8 Rising Edge Frequency Tracking Detector tSR-MAX Causal Function RESET + 0.05VDD 1µs Blanking + RQ Enable - VCT iCHR iDISCHR CT RESET 1µA/V 5µA/V 7 RES 4 GND Figure 3. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 2 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Marking Information : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (N = DIP, M = SOP) P: Y = Green Package M: Manufacturing Flow Code ZXYTT 6204 TPM Figure 4. Marking Diagram Pin Configuration LPC RES AGND VDD 8 7 6 5 1 2 3 GATE 4 GND AGND AGND Figure 5. Pin Assignments Pin Definitions Pin # 1 2 3 4 5 6 7 8 Name AGND AGND GATE GND VDD AGND RES LPC Signal Ground Signal Ground Description Driver Output. The totem-pole output driver for driving the power MOSFET. Ground. MOSFET source connection. Power Supply. The threshold voltages for startup and turn-off are 4.8V and 4.5V, respectively. Signal Ground Reset Control of linear predict. The RES pin is used to detect the output voltage level through a voltage divider. An internal current source, IDISCHR, is modulated by the voltage level on the RES pin. Winding Detection. This pin is used to detect the voltage on the winding during the on-time period of the primary GATE. © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 3 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VL PD ΘJA ΘJC TSTG TL ESD DC Supply Voltage LPC, RES Parameter Min. -0.3 Max. 30 7 45 151 58 Unit V V W °C/W °C/W °C °C KV Power Dissipation(TA=25°C) Thermal Resistance (Junction-to-Air) Thermal Resistance (Junction-to-Case) Storage Temperature Range Lead Temperature (Soldering 10 Seconds) Human Body Model Charged Device Model -55 +150 +260 5 2 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -40 Max. +105 Unit °C © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 4 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Electrical Characteristics Unless otherwise specified, VDD=4.5V~25V and TA=-40°C ~ 105°C. Symbol VOP VDD-ON VDD-OFF IDD-OP IDD-GREEN IDD-ST VDD-OVP tVDD-OVP VZ VOL VOH tR tF tPD_HIGH_LPC tPD_LOW_LPC tMAX-PERIOD VPMOS-ON VPMOS-ONHYS Parameter Continuously Operating Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Operating Current Operating Current in Green Mode Startup Current VDD Over-Voltage Protection VDD OVP Debounce Time Gate Output Clamp Voltage Output Voltage Low Output Voltage High Rising Time Falling Time Propagation Delay to OUT HIGH (LPC Trigger) Propagation Delay to OUT LOW (3) (LPC Trigger) Conditions Min. VDDOFF Typ. Max. 28.5 Unit V V V mA mA μA V V μs V V V ns ns ns ns ns ns 4.3 4.0 VDD=15V, LPC=50KHz, MOSFET CISS=6000pF VDD=15V VDD< VDD-ON 26 1.8 40 10 VDD=6V, IO=50mA VDD=6V, IO=50mA VDD=12V, CL=6nF, OUT=2V~9V VDD=6V, CL=6nF, OUT=0.4V~4V VDD=12V, CL=6nF, OUT=9V~2V VDD=6V, CL=6nF, OUT=4V~0.4V tR: 0V~2V, VDD = 12V tF: 100%~90%, VDD = 12V 22.5 4 30 70 20 20 4.8 4.5 7 1.1 150 27.5 2.1 70 12 5.3 5.0 8 1.3 200 28.5 2.4 100 14 0.5 VDD-OVP-HYST Hysteresis Voltage for VDD OVP Output Driver Section 70 120 50 90 250 180 25.0 8.3 0.9 120 170 100 130 Limitation between LPC Rising Edge to Gate Falling Edge Internal PMOS Turn-On to Pull-HIGH Gate Hysteresis Voltage On Gate Inhibit Time Gate Pull-HIGH Voltage (3) (3) 28.0 μs V V tINHIBIT VGATE-PULLHIGH M2 Option (Enable) VDD = 5V 1.6 4.5 2.2 2.8 μs V LPC Section tBNK Blanking Time for Charging CT (3) 400 Source ILPC=5µA VLPC=0V VLPC-EN = VLPC-HIGH x 0.83 at VLPCHIGH x 0.83< 2V, VO=15V, VO=VDD, VLPC-HIGH = 1.2V VLPC-EN =2V at VLPC-HIGH x 0.83 > 2V 0.05Vo+0.05, VO=15V, VO=VDD Prevent LPC Spike to Turn-Off Gate 5 500 1 0.2 80 1.00 2 600 0.3 120 1.15 ns μs V μA V V tDELAY-COMP Sampling Continuous Time for tBNK Compensation VLPC-SOURCE LPC Lower Clamp Voltage ILPC-SOURCE LPC Source Current VLPC-EN VEN-CLAMP VLPC-TH-HIGH tBNK-DIS SR Enabled Threshold Voltage SR Enable Threshold Clamp Voltage Threshold Voltage on LPC Rising Edge Blanking Time LPC is HIGH During SR Gate Turn-On Period 0.1 40 0.85 0.7 0.8 350 0.9 V ns © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Electrical Characteristics Unless otherwise specified, VDD=4.5V~25V and TA=-40°C ~ 105°C. Symbol Parameter (3) Conditions Min. Typ. 6 Max. Unit V LPC Section (Continued) VLPC-CLAMP-H Higher Clamp Voltage VLPC-DIS tLPC-HIGH tLPC-EN-RES RES Section VRES-EN tRES-LOW KRES-DROP tRES-DROP tCT VLPC VDD-RES Threshold Voltage of VRES to Enable SR MOS Debounce Time for Disable RES Function (3) LPC Voltage to Disable SR Gate Debounce Time for Disable SR Gate No LPC Signal, Reset VLPC-EN 4.0 4.2 1 100 4.4 V μs μs 0.60 0.75 1 6 90 1.5 0.90 2 V µs V % µs VRES-CLAMP-H Higher Clamp Voltage RES Dropping Protection Ratio within One Cycle Debounce Time for RES Dropping Protection Linear Operation Range of CT VLPC=1.5V 27 0.8 0.8 0.8 0.8 4.65 0.9 105 Internal Timing Section 30 33 3.4 4.0 3.4 4.0 5.00 1.1 5.35 1.3 120 µs % μs V V V V Linear Operation Range of LPC for VDD5V Linear Operation Range of VDD-RES VDD5V Minimum LPC Time to Enable SR_Gate, VDET>VDET_TH_HIGH ton-SR(n+1)< tgate-limitx ton-SR(n) CT Capacitor tDIS Time to Leave Green Mode CT Capacitor tDIS Time to Enter Green Mode Cycle Time to Enter Green Mode Cycle Time to Leave Green Mode RatioLPC-RES Ratio Between LPC and RES tLPC-EN tgate-limit Green Section tGREEN-OFF tGREEN-ON tGREEN-TIMEenter fS=65KHz fS=65KHz CT Discharge Time < tGREEN-ON CT Discharge Time > tGREEN-OFF (3) 4.60 4.25 5.35 4.80 3 7 75 6.10 5.35 µs µs Times Times µs tGREEN-TIMEleave tGREEN-ENTER No Gate Signal to Enter Green Mode Causal Function Section tCAUSAL tDEAD-CAUSAL tDEAD-CFR If tS-PWM(n+1) > tCAUSALxtS-PWM(n) SR Stops Switching, Enter Green Mode SR Turn-off Dead Time by Causal Function fS =65KHz fS=65KHz 40KHz 380 120 580 150 1.5 140 20 780 % ns ns μs °C °C CFR Start to Shrink Timing (Last Time from SR Gate Falling to LPC CFR (Causal Function Regulator) Rising) tDEAD-RE-CFR SR Gate Narrowed Down Width when tDEAD-CFR Triggered Internal Over-Temperature Protection Section TOTP TOTP-HYST Internal Threshold Temperature for OTP (3) (3) Hysteresis Temperature for Internal OTP Note: 3. Guaranteed by design. © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 6 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Typical Performance Characteristics These characteristic graphs are normalized at TA=25°C. Figure 6. Turn-On Threshold Voltage Figure 7. Turn-Off Threshold Voltage Figure 8. Startup Current Figure 9. Operating Current Figure 10. Operating Current in Green Mode Figure 11. Gate Output Clamping Voltage © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 7 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Typical Performance Characteristics (Continued) These characteristic graphs are normalized at TA=25°C. Figure 12. LPC Source Current Figure 13. LPC Lower Clamp Voltage Figure 14. Threshold Voltage of VRES Figure 15. Ratio between LPC and RES Figure 16. Minimum LPC Enable Time Figure 17. Maximum Time between LPC Rising Edge to Gate Falling Edge © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 8 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Functional Description Figure 18. Typical Waveforms of Linear-Predict Timing Control in CCM and DCM/QR Flyback Linear Predict Timing Control The SR MOSFET turn-off timing is determined by linear-predict timing control and the operation principle is based on the volt-second balance theorem. The voltsecond balance theorem states that the inductor average voltage is zero during a switching period in steady state, so the charge voltage and charge time product is equal to the discharge voltage and discharge time product. In flyback converters, the charge voltage on the magnetizing inductor is input voltage (VIN), while the discharge voltage is nVOUT, as the typical waveforms show in Figure 18. The following equation can be drawn: FAN6204 uses the LPC and RES pins with two sets of voltage dividers to sense DET voltage (VDET) and output voltage (VOUT), respectively; so VIN/n, tPM.ON, and VOUT can be obtained. As a result, tL,DIS , which is the on-time of SR MOSFET, can be predicted by Equation 1. As shown in Figure 18, the SR MOSFET is turned on when the SR MOSFET body diode starts conducting and DET voltage drops to zero. The SR MOSFET is turned off by linear-predict timing control. Circuit Realization The linear-predict timing-control circuit generates a replica (VCT) of magnetizing current of flyback transformer using internal timing capacitor (CT), as shown in Figure 19. Using the internal capacitor voltage, the inductor discharge time (tL.DIS) can be detected indirectly, as shown in Figure 18 When CT is discharged to zero, the SR controller turns off the SR MOSFET. VIN ⋅ t PM .ON = n ⋅ VOUT ⋅ t L. DIS (1) where tPM,ON is inductor charge time and tL,DIS is inductor discharge time. © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 9 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification CCM Operation The typical waveforms of CCM operation in steady state are shown as Figure 18. When the primary-side MOSFET is turned on, the energy is stored in Lm. During the on-time of the primary-side MOSFET (tPM.ON), the magnetizing current (IM) increases linearly from IM,min to IM,max. Meanwhile, internal timing capacitor (CT) is charged by current source (iCHR-iDICHR) proportional to VIN, so VCT also increases linearly. When the primary-side MOSFET is turned off, the energy stored in Lm is released to the output. During the inductor discharge time (tL.DIS), the magnetizing current (IM) decreases linearly from IM,max to IM,min. At the same time, the internal timing capacitor (CT) is discharged by current source (iDISCHR) proportional to VOUT, so VCT also decreases linearly. To guarantee the proper operation of SR, it is important to turn off SR MOSFET just before SR current reaches IM,min so that the body diode of SR MOSFET is naturally turned off. Figure 19. Simplified Linear-Predict Block The voltage-second balance equation for the primaryside inductance of the flyback converter is given in Equation 1. Inductor current discharge time is given as: t L.DIS = VIN ⋅ t PM .ON n ⋅ VOUT (2) The voltage scale-down ratio between RES and LPC is defined as K below: K= R4 / ( R3 + R4 ) R2 / ( R1 + R2 ) (3) DCM / QR Operation In DCM / QR operation, when primary-side MOSFET is turned off, the energy stored in Lm is fully released to the output at the turn-off timing of primary-side MOSFET. Therefore, the DET voltage continues resonating until the primary-side MOSFET is turned on, as depicted in Figure 18. While DET voltage is resonating, DET voltage and LPC voltage drop to zero by resonance, which can trigger the turn-on of the SR MOSFET. To prevent fault triggering of the SR MOSFET in DCM operation, blanking time is introduced to LPC voltage. The SR MOSFET is not turned on even when LPC voltage drops below 0.05VOUT unless LPC voltage stays above 0.83VLPC-HIGH longer than the blanking time (tLPC-EN). The turn-on timing of the SR MOFET is inhibited by gate inhibit time (tINHIBIT), once the SR MOSFET turns off, to prevent fault triggering. During tPM.ON, the charge current of CT is iCHR-iDICHR, while during tL.DIS, the discharge current is iDICHR. As a result, the current-second balance equation for internal timing capacitor (CT) can be derived from: ( 5 VIN ⋅( + VOUT ) − VOUT ) ⋅ tPM .ON = VOUT ⋅ tCT .DIS Kn (4) Therefore, the discharge time of CT is given as: tCT .DIS 5 VIN ⋅( + VOUT ) − VOUT ) ⋅ t PM .ON Kn = VOUT ( (5) When the voltage scale-down ratio between RES and LPC (K) is five (5), the discharge time of CT (tCT.DIS) is the same as inductor current discharge time (tL.DIS). However, considering the tolerance of voltage divider resistors and internal circuit, the scale-down ratio (K) should be larger than five (5) to guarantee that tCT.DIS is shorter than tL.DIS. It is typical to set K around 5~5.5. Referring to Figure 18; when LPC voltage is higher than VLPC-EN over a blanking time (tLPC-EN) and lower than VLPC-TH-HIGH (0.05VOUT), then SR MOSFET can be triggered. Therefore, VLPC-EN must be lager than VLPC-THHIGH or the SR MOSFET cannot be turned on. When designing the voltage divider of LPC, R1 and R2 should be considered as: Green-Mode Operation To minimize the power consumption at light-load condition, the SR circuit is disabled when the load decreases. As illustrated in Figure 20, the discharge times of inductor and internal timing capacitor decrease as load decreases. If the discharge time of the internal timing capacitor is shorter than tGREEN-ON (around 4.8µs) for more than three cycles, the SR circuit enters Green Mode. Once FAN6204 enters Green Mode, the SR MOSFET stops switching and the major internal block is shut down to further reduce operating current of the SR controller. In Green Mode, the operating current reduces to 800µA. This allows power supplies to meet the most stringent power conservation requirements. When the discharge time of the internal capacitor is longer than tGREEN-OFF (around 5.35µs) for more than seven cycles, the SR circuit is enabled and resumes the normal operation, as shown in Figure 21. 0.83 ⋅ V R2 ⋅ ( IN .MIN + VOUT ) > 0.05VOUT + 0.3 R1 + R2 n (6) On the other hand, the linear operation range of LPC and RES (1~4V) should be considered as: V R2 ⋅ ( IN .MAX + VOUT ) < 4 R1 + R2 n (7) (8) R4 ⋅ VOUT < 4 R3 + R4 © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 10 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification SR Gate Normal Mode 3 Times 4.8µs 4.8µs 4.8µs Green Mode periods (tS-PWM) is tracked for causal function, the accuracy of switching period is important. Therefore, if the detected switching period has a serious variation under some abnormal conditions, the SR gate should be terminated to prevent fault trigger. IM Figure 23. Fault Causal Timing Protection Figure 20. Entering Green Mode Gate Expand Limit Protection Gate expand limit protection controls on-time expansion of the SR MOSFET. Once the discharge time of the internal timing capacitor (tDIS.CT) is longer than 115% of previous on time of the SR MOSFET (ton-SR(n-1)); ton-SR(n) is limited to 115% of ton-SR(n-1), as shown in Figure 24. When output load changes rapidly from light load to heavy load, voltage-second balance theorem may not be applied. In this transient state, gate expand limit protection is activated to prevent overlap between SR gate and PWM gate. Figure 21. Resuming Normal Operation Causal Function Causal function is utilized to limit the time interval (tSRMAX) from the rising edge of VLPC to the falling edge of the SR gate. tSR-MAX is limited to 97% of previous switching period, as shown in Figure 22. When the system operates at fixed frequency, whether voltagesecond balance theorem can be applied or not, causal function can guarantee reliable operation. Figure 24. Gate Expand Limit Protection RES Dropping Protection RES dropping protection prevents VRES dropping too much within a cycle. The VRES is sampled as a reference voltage, VRES’, on VLPC rising edge. Once VRES drops below 90% of VRES’ for longer than a debounce time (tRES-DROP), the SR gate is turned off immediately, as shown in Figure 25. When output voltage drops rapidly within a switching cycle, voltage-second balance may not be applied, RES dropping protection is activated to prevent overlap. Figure 22. Causal Function Operation Fault Causal Timing Protection Fault causal timing protection is utilized to disable the SR gate under some abnormal conditions. Once the switching period (tS-PWM(n)) is longer than 120% of previous switching period (tS-PWM(n-1)), SR gate is disabled and enters Green Mode, as shown in Figure 23. Since the rising edge of VLPC among switching © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 11 Figure 25. VRES Dropping Protection www.fairchildsemi.com FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification LPC Pin Open / Short Protection LPC-Open Protection: If VLPC is higher than VLPC-DIS (4.2V) for longer than debounce time tLPC-HIGH, FAN6204 stops switching immediately and enters Green Mode. VLPC is clamped at 6V to avoid LPC pin damage. LPC-Short Protection: If VLPC is pulled to ground and the charging current of timing capacitor (CT) is near zero, SR gate is not output. Under-Voltage Lockout (UVLO) The power ON and OFF VDD threshold voltages are fixed at 4.8V and 4.5V, respectively. With an ultra-low VDD threshold voltage, the FAN6204 can be used in various output voltage applications. VDD Pin Over-Voltage Protection (OVP) Over-voltage conditions are usually caused by an open feedback loop. VDD over-voltage protection prevents damage on the SR MOSFET. When the voltage on VDD pin exceeds 27.5V, the SR controller stops switching the SR MOSFET. RES Pin Open / Short Protection RES-Open Protection: If VRES is pulled to HIGH level, the gate signal is extremely small and FAN6204 enters Green Mode. In addition, VRES is clamped at 6V to avoid RES pin damage. RES-Short Protection: If VRES is lower than VRES-EN (0.7V) for longer than debounce time tRES-LOW, FAN6204 stops switching immediately and enters Green Mode. Over-Temperature Protection (OTP) To prevent SR gate from fault triggering in high temperatures, internal over-temperature protection is integrated in FAN6204. Once the temperature is over 140°C, SR gate is disabled until the temperature drops below 120°C. © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 12 FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 26. 8-Pin, Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 www.fairchildsemi.com 13 www.fairchildsemi.com FAN6204 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification © 2010 Fairchild Semiconductor Corporation FAN6204 • Rev. 1.0.0 14