FAN6555

www.fairchildsemi.com FAN6555 2A DDR Bus Termination Regulator Features • • • • • • • • • • • • • Can source and sink up to 2A continous, 3A peak No heatsink required Integrated Power MOSFETs Generates termination voltages for DDR SDRAM VREF input available for external voltage divider Separate voltages for VCCQ and PVDD Buffered VREF output VOUT of ±3% or less at 2A Minimum external components 16-pin SOIC package -40°C to +85°C operating temperature range Shutdown for standby or suspend mode operation Thermal Shutdown ≈ 130ºC Description The FAN6555 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6555 can be implemented to produce regulated output voltages in two different modes. In the default mode, when the VREF pin is open, the FAN6555 output voltage is 50% of the voltage applied to VCCQ. The FAN6555 can also be used to produce various user-defined voltages by forcing a voltage on the VREFIN pin. In this case, the output voltage follows the input VREFIN voltage. The switching regulator is capable of sourcing or sinking up to 2A of current while regulating an output VTT voltage to within 3% or less. Transient output currents of ±3A can also be accommodated. The FAN6555 can also be used in conjunction with series termination resisitors to provide an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. Block Diagram 15 16 14 1 9 VDD VDD 12 2 7 VCCQ AVCC VREFOUT SHDN PVDD1 PVDD2 VL1 (VOUT) 3 OSCILLATOR/ RAMP GENERATOR 200kΩ – + VREF BUFFER VREFIN 11 200kΩ AGND 13 + – – R + ERROR AMP RAMP COMPARATOR Q S Q 6 VL2 (VOUT) VFB 10 8 DGND 4 PGND1 5 PGND2 REV. 1.1.3 8/4/03 FAN6555 PRODUCT SPECIFICATION Pin Configuration FAN6555 16-Pin SOIC (M16) VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND VDD VFB VREFIN SHDN AGND VREFOUT VCCQ AVCC Digital supply voltage Voltage supply for internal power transistors Output voltage/ inductor connection Ground for output power transistors Ground for output power transistors Output voltage/inductor connection Voltage supply for internal power transistors Digital ground Digital supply voltage Input for external compensation feedback Input for external reference voltage Shutdown active low. CMOS input level Ground for internal reference voltage divider Reference voltage output Voltage reference for internal voltage divider Analog voltage supply Function 2 REV. 1.1.3 8/4/03 PRODUCT SPECIFICATION FAN6555 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter PVDD Voltage on Any Other Pin Average Switch Current (IAVG) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance: Junction to Case (θJC) Junction to Ambient (θJA) Output Current, Source or Sink (peak) Min. GND – 0.3 Max. 4.5 VIN + 0.3 2.0 150 150 300 30 88 3.0 Units V V A °C °C °C °C/W A -65 Operating Conditions Parameter Temperature Range PVDD Operating Range VCCQ Operating Range Min. -40 2.0 1.4 Max. +85 4.0 4.0 Units °C V V Electrical Characteristics Unless otherwise specified, AVCC = VDD = PVDD = 3.3V ±10%, TA = Operating Temperature Range (Note 1) Symbol Parameter Switching Regulator Output Voltage, VTT VTT (See Figure 1) Conditions IOUT = 0, VREF = open Note 2 IOUT = ±2A, VREF = open TA = 25°C Note 2 VREFOUT Internal Resistor Divider IOUT = 0 Note 2 Note 2 Min. VCCQ = 2.3V 1.12 VCCQ = 2.5V 1.22 VCCQ = 2.7V 1.32 VCCQ = 2.3V 1.09 VCCQ = 2.5V 1.19 VCCQ = 2.7V 1.28 Typ. 1.15 1.25 1.35 1.15 1.25 1.35 Max. Units 1.18 1.28 1.38 1.21 1.31 1.42 V V V V V V V V V kΩ kHz mV µA mA mA mA mA µA mA ZIN ∆VOFFSET Supply IQ VREF Reference Pin Input Impedance Switching Frequency Offset Voltage VTT – VREFOUT Quiescent Current VCCQ = 2.3V 1.139 1.15 1.162 VCCQ = 2.5V 1.238 1.25 1.263 VCCQ = 2.7V 1.337 1.35 1.364 VCCQ = 0 100 650 AVCC = 2.5V No Load VCCQ = 2.5 IOUT = 0, no load VCCQ = 2.5V IVCCQ IAVCC IAVCC SD IVDD IVDD SD IPVDD –20 6 0.5 0.2 0.25 0.2 100 3 20 10 1.0 0.5 1.0 1.0 250 Buffer IREF Output Current Capability Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. AVCC, PVDD = 3.3V ±10% REV. 1.1.3 8/4/03 3 FAN6555 PRODUCT SPECIFICATION Functional Description The FAN6555 integrates two power MOSFETs that can be used to source and sink 2A of current while maintaining a tight voltage regulation. Using the external feedback, the output can be regulated well within 3% or less, depending on the external components chosen. Separate voltage supply inputs have been added to accommodate applications with various power supplies for the databus and power buses. VREF Input and Output The VREFIN input can be used to force a voltage at the outputs (Inputs section, above). The VREFOUT pin is an output pin that is driven by a small output buffer to provide the VREF signal to other devices in the system. The output buffer is capable of driving several output loads. The output buffer can handle 3mA. Other Supply Voltages Several inputs are provide for the supply voltages: PVDD1, PVDD2, AVCC, and VDD. The PVDD1 and PVDD2 provide the power supply to the power MOSFETs. VDD provides the voltage supply to the digital sections, while AVCC supplies the voltage for the analog sections. Again, see the Applications section for recommendations. Outputs The output voltage pins (VL1, VL2) are tied to the databus, address, or clock lines via an external inductor. See the Applications section for recommendations. Output voltage is determined by the VCCQ or VREFIN inputs. Inputs The input voltage pins (VCCQ or VREFIN) determine the output voltages (VL1 or VL2) . In the default mode, where the VREFIN pin is floating, the output voltage is 50% of the VCCQ input. VCCQ can be the reference voltage for the databus. Output voltage can also be selected by forcing a voltage at the VREFIN pin. In this case, the output voltage follows the voltage at the VREFIN input. Simple voltage dividers can be used in this case to produce a wide variety of output voltages between 0.7V and VDD–0.7V. Feedback Input The VFB pin is an input that can be used for closed loop compensation. This input is derived from the voltage output. See Application section for recommendation. 2.5V TO 4V R2 100Ω R1 100Ω C9 0.1µF C8 0.1µF R3 100kΩ U1 FAN6555 TPI L1 3.3µH C3 0.1µF C1 820µF F2V OS-CON TO SDRAMS 1 2 VTT 3 4 C2 0.1µF 5 C4 0.1µF 6 7 8 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD 16 15 14 13 12 11 10 9 SHDN VREFIN VCCQ VREFOUT C5 470µF R4 100kΩ C7 1nF GND R5 1kΩ GND Figure 1. 4 REV. 1.1.3 8/4/03 PRODUCT SPECIFICATION FAN6555 Applications Using the FAN6555 for DDR Bus Termination The circuit schematic in Figure 1 shows a recommended approach for constructing a bus terminating solution for a DDR bus. This circuit can be used in PC memory and Graphics memory applications as shown in Figures 3 and 4. Note that the FAN6555 can provide the voltage reference (VREF) and terminating voltages (VTT). Using the layout as shown in Figures 5, 6, and 7, and measuring the VTT performance using the test setup as described in Figure 8, the FAN6555 delivered a VTT ± 20mV for 1A to 2A loads (see Figure 9). Table 1 provides a recommended parts list. An alternate application circuit for the FAN6555 is shown in Figure 2. The number of external components is reduced compared to the circuit in Figure 1. This is achieved by replacing four, 0.1µF bypass capacitors with one, low ESR, 10µF ceramic capacitor placed right next to U1. Two 100 Ω resistors are also eliminated. High value, surface-mount MLC capacitors were not available when the original application circuit (Figure 1) was developed. Both application circuits offer the same electrical performance but the circuit shown in Figure 2 has a reduced bill-of-materials. Table 2 shows the recommended parts list for the circuit of Figure 2. Bus Termination Solutions for Others Buses Table 3 provides a summary of various bus termination VREF & VTT requirements. The FAN6555 can be used for those applications. 2.5V TO 4V C5 470µF U1 FAN6555 1 C3 10µF VTT C1 820µF F2V OS-CON TO SDRAMS L1 3.3µH 2 3 4 C2 0.1µF 5 6 7 8 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD 16 15 14 13 12 11 10 9 R3 100kΩ VCCQ VREFOUT SHDN VREFIN R1 100kΩ C4 1nF GND R2 1kΩ GND Figure 2. Alternate Application Circuit REV. 1.1.3 8/4/03 5 FAN6555 PRODUCT SPECIFICATION 168/184/208-PIN DIMM CONNECTORS AND SDRAM/SGRAM MODULES TERMINATION RESISTORS PC CHIP SET NORTHBRIDGE DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES TERMINATION RESISTORS VTT FAN6555 VREF Figure 3. Complete Termination Solution PC Main Memory (PC Motherboard) TERMINATION RESISTORS SGRAM SO DIMM AND MODULES 3D GRAPHIC CHIP DATA LINE, CLOCK LINES, ADDRESS LINES, CONTROL LINES TERMINATION RESISTORS 2.5V VOLTAGE REGULATOR 5V OR 3.3V VREF FAN6555 VTT AGP/PCI BUS Figure 4. Complete Termination Solution Graphics Memory Bus – AGP Graphics Cards 6 REV. 1.1.3 8/4/03 PRODUCT SPECIFICATION FAN6555 Figure 5. Top Silk Figure 6. Top Layer Figure 7. Bottom Layer 2.5V TO 4V R2 100Ω R1 100Ω C9 0.1µF C8 0.1µF R3 100kΩ U1 FAN6555 TPI L1 3.3µH C3 0.1µF C1 820µF F2V OS-CON TO SDRAMS 1 2 VTT 3 4 C2 0.1µF 5 C4 0.1µF 6 7 8 VDD PVDD1 VL1 PGND1 PGND2 VL2 PVDD2 DGND AVCC VCCQ VREFOUT AGND SHDN VREFIN VFB VDD 16 15 14 13 12 11 10 9 SHDN VREFIN VCCQ VREFOUT C5 470µF R4 100kΩ C7 1nF GND R5 1kΩ GND REV. 1.1.3 8/4/03 7 FAN6555 PRODUCT SPECIFICATION 3.3V POWER SUPPLY V A ACTIVE CLAMP VDD VCCQ VCCQ SUPPLY FAN6555 EVAL GND VTT CURRENT SOURCE/SINK POWER SUPPLY ITT V A Figure 8. Test Circuit Setup VTT VARIANCE WITH VDD@ITT (VCCQ 2.5V) TESTED WITH EVAL PCB 1.29 ITT 2A SINKING 1A SINKING 1.28 0A SINKING VTT (V) 2A SOURCING 1.27 1A SOURCING 1.26 2.0 2.5 3.0 VDD (V) 3.5 4.0 Figure 9. VTT Performance for DDR Bus 8 REV. 1.1.3 8/4/03 PRODUCT SPECIFICATION FAN6555 Table 1. Recommend Parts List for Figure 1. Item Resistors 1 2 3 Capacitors 4 5 6 7 8 ICs 9 Magnetics 10 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HC Pulse Eng./ P0751.332T Gowanda/SMP3316-331M XFMRS inc./XF0046-S4 Tektronics/131-4353-00 Sullins/PTC36SAAN (36 PINS) L1 1 FAN6555 Bus Terminator FAN6555M U1 3 1 1 1 2 0.1µF 1210 Film SMD 820µF 2V Solid Elect. SMD 470µF 6.3V Solid Elect. SMD 1nF 1210 Film SMD 0.1µF 0805 Film Panasonic/ECV3VB1E104K Panasonic/ECU-V1H104KBW Sanyo/2SV820M Os Con Sanyo/6SVP470M Os Con Panasonic/ECU-V1H102KBM Panasonic/ECJ-2VF1C104Z C2, C8, C9 C1 C5 C7 C3, C4 2 1 2 100Ω1210 SMD 1kΩ 1210 SMD 100kΩ1210 SMD Panasonic/ERJ-8ENF1000V Panasonic/ERJ-8ENF1001V Panasonic/ERJ-8ENF1003V R1, R2 R5 R3, R4 Qty Description Manufacturer / Part Number Designator Other 11 12 1 1 Scope probe socket 12 Pin breakaway strip TP1 I/O, standoffs Table 2. Recommend Parts List for Figure 2. Item Resistors 1 2 Capacitors 3 4 5 6 7 ICS 8 Magnetics 9 1 3.3µH 5A inductor SMD Coilcraft/D03316P-332HC Pulse Eng./ P0751.332T Gowanda/SMP3316-331M XFMRS inc./XF0046-S4 Tektronics/131-4353-00 Sullins/PTC36SAAN (36 PINS) L1 1 FAN6555 Bus Terminator FAN6555M U1 1 1 1 1 1 0.1µF, 1210 Film SMD 820µF 2V Solid Elect. SMD 470µF 6.3V Solid Elect. SMD 1nF 1210 Film SMD 10µF 6.3V Ceramic Panasonic/ECV3VB1E104K Panasonic/ECU-V1H104KBW Sanyo/2SV820M Os Con Sanyo/6SVP470M Os Con Panasonic/ECU-V1H102KBM TDK/C2012X5R0J106M C2 C1 C5 C4 C3 2 1 100kΩ 0805 SMD 1kΩ 0805 SMD Panasonic/ERJ-8ENF1000V Panasonic/ERJ-8ENF1000V R1, R3 R2 Qty Description Manufacturer / Part Number Designator Other 10 11 1 1 Scope probe socket 12 Pin breakaway strip TP1 I/O, standoffs REV. 1.1.3 8/4/03 9 FAN6555 PRODUCT SPECIFICATION Vendor List 1. AVX 2. Sanyo 3. Tektronix 4. Coilcraft 5. Pulse 6. Gowanda 7. Xfmrs Inc. 8. Panasonic 9. Digikey (207) 282-5111 (619) 661-6835 (408) 496-0800 (847) 639-6400 (800) 797-8573 (716) 532-2234 (317) 834-1066 (714) 373-7366 (800) 344-4539 Table 3. Termination Solutions Summary By Bus Type Driving Method Open Drain Fairchild Solutions FAN6555; Mode: VREF Input = 1.5V, VCC = 3.3V Industry System Components 300 to 500MHz Processor; PC Chipsets; GTLP 16xxx Buffers; Fairchild, Texas Instr. DDR SDRAM; Hitachi, Fujitsu, NEC, Micro, Mitsubishi Bus GTL+ Description Gunning Transceiver Bus Plus VDDQ 3.3V VTT 1.5V±10% VREF 1.0V±2% DDR (SSTL-2) Series Stub Terminated Logic for 2V Symmetric Drive, Series Resistance 2.5V±10% 0.5x (VDDQ) ±3% 2.5V FAN6555, ML6554CU, or ML6553CS; Mode: VREF Input = Floating or Forced, VCC = 3.3V ML6553CS; Mode: VREF Input = Open, VCC = VDDQ ML6553CS; Mode: VREF Input = Open, VCC = VDDQ RAMBUS RAMBUS Signaling Logic Low Voltage TTL Logic or PECL or 3.3V VME Open Drain None Specified 2.5V 2.0V nDRAM, RAMBUS, Intel, Toshiba Processors or backplanes; LV-TTL SDRAM, EDO RAM LV-TTL Symmetric Drive 3.3±10% VDDQ/2 3.3V 10 REV. 1.1.3 8/4/03 PRODUCT SPECIFICATION FAN6555 Mechanical Dimensions Package: M16 16-Pin SOIC Inches Min. A A1 B C D E e H h L N α ccc Max. Inches (Millimeters) Symbol Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. .053 .069 .004 .010 .013 .020 .0075 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0° — 8° .004 .244 .020 .050 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0° — 8° 0.10 6.20 0.50 1.27 3 6 16 9 E H 1 8 D A1 A SEATING PLANE –C– LEAD COPLANARITY ccc C α h x 45° C e B L REV. 1.1.3 8/4/03 11 FAN6555 PRODUCT SPECIFICATION Ordering Information Part Number FAN6555M FAN6555MX Temperature Range -40°C to +85°C -40°C to +85°C Package 16-Pin SOIC (M16) 16-Pin SOIC in tape-and-reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/4/03 0.0m 002 Stock#DS30006555  2003 Fairchild Semiconductor Corporation