FAN7361_09

FAN7361, FAN7362 High-Side Gate Driver November 2009 FAN7361, FAN7362 High-Side Gate Driver Features ! Floating Channel Designed for Bootstrap ! ! ! ! ! ! Description The FAN7361/FAN7362, a monolithic high-side gate drive IC, can drive MOSFETs and IGBTs that operate up to +600V. Fairchild’s high-voltage process and commonmode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level shift circuit offers high-side gate driver operation up to VS=-9.8V(typ.) for VBS=15V. The UVLO circuit prevents malfunction when VBS is lower than the specified threshold voltage. Output drivers typically source/sink 250mA/500mA, respectively, which is suitable for fluorescent lamp ballast, PDP scan driver, motor control, and so on. Operation to +600V Typically 250mA/500mA Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit VCC & VBS Supply Range from 10V to 20V UVLO Function for VBS Output In-phase with Input Signal 8-SOP Applications ! PDP Scan Driver ! Motor Control ! SMPS ! Electronic Ballast 8-SOP Ordering Information Part Number FAN7361M(1) FAN7361MX(1) FAN7362M(1) FAN7362MX (1) Package Operating Temperature Range Eco Status Packing Method Tube 8-SOP -40°C ~ 125°C RoHS Tape & Reel Tube Tape & Reel Note: 1. These devices passed wave soldering test by JESD22A-111. For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Typical Application Circuit 15V RBOOT DBOOT 600V 1 NC IN1 2 3 IN2 4 GND IN VCC VB 8 HO 7 CBOOT VS 6 NC 5 Q2 R1 R2 Q1 R3 R4 Load FAN7361 Rev.04 Figure 1. Typical Application Circuit Internal Block Diagram VCC 3 UVLO DRIVER 8 VB IN GND 2 4 NOISE CANCELLER R S R Q 7 HO Pin 1 and 5 are not connection FAN7361 Rev.04 PULSE GENERATOR 6 VS Figure 2. Functional Block Diagram © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 2 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Pin Assignments NC IN VCC GND 1 2 3 4 8 VB HO VS NC FAN7361 FAN7362 7 6 5 FAN7361 Rev.04 Figure 3. Pin Configuration (Top View) Pin Definitions Pin 1 2 3 4 5 6 7 8 Name NC IN VCC GND NC VS HO VB No Connection Function/ Description Logic Input for High-Side Gate Driver Output Supply Voltage Logic Ground No Connection High-Voltage Floating Supply Return High-Side Driver Output High-Side Floating Supply © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 3 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol VS VB VHO VCC VIN dVS/dt PD(2)(3)(4) θJA TJ TS TA Notes: Characteristics High-Side Offset Voltage High-Side Floating Supply Voltage High-Side Floating Output Voltage Logic Fixed Supply Voltage Logic Input Voltage Allowable Offset Voltage Slew Rate Power Dissipation Thermal Resistance, Junction-to-Ambient Junction Temperature Storage Temperature Ambient Temperature Min. VB-25 -0.3 VS-0.3 -0.3 -0.3 Max. VB+0.3 625 VB+0.3 25 VCC+0.3 ± 50 0.625 200 +150 +150 Unit V V/ns W °C/W °C °C °C -40 +125 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB VS VHO VIN VCC Parameter High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage High-Side Output Voltage Logic Input Voltage Logic Supply Voltage Min. VS+10 6-VCC VS GND 10 Max. VS+20 600 VB VCC 20 Unit V © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 4 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Electrical Characteristics VBIAS(VCC, VBS)=15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are referenced to VS and are applicable to the respective output HO. Symbol VBSUV+ VBSUVVBSHYS ILK IQBS IQCC IPBS VIH VIL VOH VOL IIN+ IINIO+ IOVS Characteristics Test Condition FAN7361 FAN7362 FAN7361 FAN7362 FAN7361 FAN7362 Min. 8.2 7.6 7.4 7.2 Typ. Max. 9.2 8.6 8.6 8.2 0.5 0.4 10 50 30 420 80 75 550 10.2 9.6 9.2 9.2 Unit VBS Supply Under-Voltage Positive Going VBS=Sweep Threshold VBS Supply Under-Voltage Negative Going Threshold VBS Supply Under-Current Lockout Hysteresis Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Operating VBS Supply Current Logic "1" Input Voltage Logic "0" Input Voltage High Level Output Voltage, VB-VHO Low Level Output Voltage, VHO Logic "1" Input Bias Current Logic "0" Input Bias Current Output High Short Circuit Pulse Current Output Low Short Circuit Pulse Current Allowable Negative VS Pin Voltage for IN Signal Propagation to HO No load No load VIN=5V VIN=0V VBS=Sweep VBS=Sweep VB=VS=600V VIN=0V or 5V VIN=0V CL=1nF, f=10kHz V µA FAN7361 FAN7362 FAN7361 FAN7362 3.6 2.9 1.0 0.8 0.1 0.1 50 1.0 200 400 250 500 -9.8 -7.0 90 2.0 µA mA V V VHO=0V, VIN=5V, PW ≤ 10µs VHO=15V, VIN=0V,PW ≤ 10µs Dynamic Electrical Characteristics VBIAS(VCC, VBS)=15.0V, VS=GND, CL=1000pF and TA = 25°C, unless otherwise specified. Symbol ton toff tr tf Characteristics Turn-on Propagation Delay Turn-off Propagation Delay Turn-on Rise Time Turn-off Fall Time (5) Test Condition VS=0V VS=0V or 600V Min. Typ. 120 90 70 30 Max. 200 180 160 100 Unit ns Note: 5. This parameter guaranteed by design. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 5 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Typical Characteristics 200 80 70 60 VCC=15V IN=COM=0V -40°C 25°C 125°C 150 -40°C 25°C 125°C IQCC [μA] 50 40 30 20 10 0 0 IIN [μA] 100 50 0 5 10 15 20 25 0 2 4 6 8 10 12 14 VCC [V] VIN [V] Figure 4. IQCC vs. Supply Voltage Figure 5. Input Bias Current vs. Input Voltage 10.0 9.5 VBSUVP1 VBSUVP2 VBSUVN1 VBSUVN2 PROPAGATION DELAY TIME [nsec] 10.5 200 180 160 140 120 100 80 60 40 20 0 0 20 40 60 80 100 120 TON TOFF VBS [V] 9.0 8.5 8.0 7.5 -20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE [°C] AMBIENT TEMPERATURE [°C] Figure 6. VBS UVLO vs. Temp. Figure 7. Turn On/Off Propagation Time vs. Temp. 90 OUTPUT CAPABILITY [mA] 80 70 TR TF 600 500 400 300 200 -20 0 20 40 60 80 100 IOH+ IOH- tr/tf [nsec] 60 50 40 30 20 10 -20 0 20 40 60 80 100 120 120 AMBIENT TEMPERATURE [°C] AMBIENT TEMPERATURE [°C] Figure 8. Rising/Falling Time vs. Temp. Figure 9. Output Sinking/Sourcing Current vs. Temp. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 6 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Switching Time Definition 5V IN 50% 50% VCC=15V 10μF 0.1μF GND IN VB 10μF HVIC VS CL HO HO-V S 10% 0.1μF 15V ton tr toff 90% 90% tf 10% FAN7361 Rev.02 FAN7361 Rev.03 Figure 10. Switching Time Test Circuit Figure 11. Input / Output Timing Diagram © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 7 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver Physical Dimensions 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 (1.04) DETAIL A SCALE: 2:1 SEATING PLANE Figure 12. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 8 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 9 www.fairchildsemi.com