FAN7382M

FAN7382 High- and Low-Side Gate Driver February 2007 FAN7382 High- and Low-Side Gate Driver Features Floating Channels Designed for Bootstrap Operation to +600V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for Both Channels Common-Mode dv/dt Noise Canceling Circuit Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VCC=VBS=15V VCC & VBS Supply Range from 10V to 20V UVLO Functions for Both Channels TTL Compatible Input Logic Threshold Levels Matched Propagation Delay Below 50nsec Output In-phase with Input Signal Description The FAN7382, a monolithic high and low side gate-drive IC, can drive MOSFETs and IGBTs that operate up to +600V. Fairchild’s high-voltage process and commonmode noise canceling technique provides stable operation of the high-side driver under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. The input logic level is compatible with standard TTL-series logic gates. UVLO circuits for both channels prevent malfunction when VCC or VBS is lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA, respectively, which is suitable for fluorescent lamp ballasts, PDP scan drivers, motor controls, etc. Applications PDP Scan Driver Fluorescent Lamp Ballast SMPS Motor Driver 8-SOP 8-DIP 14-SOP Ordering Information Part Number FAN7382N FAN7382M (1) Package 8-DIP 8-SOP 14-SOP Pb-Free Operating Temperature Range Packing Method Tube Tube FAN7382MX(1) FAN7382M1(1) FAN7382M1X Note: (1) Yes -40°C ~ 125°C Tape & Reel Tube Tape & Reel 1. These devices passed wave soldering test by JESD22A-111. © 2005 Fairchild Semiconductor Corporation FAN7382 Rev. 1.0.8 www.fairchildsemi.com FAN7382 High- and Low-Side Gate Driver Typical Application Circuit 15V RBOOT DBOOT 600V 1 VCC 2 VB 8 Q1 HO 7 CBOOT VS 6 Q2 R3 R1 R2 HIN LIN C1 HIN 3 LIN 4 COM LO 5 Load R4 FAN7382 Rev.05 Figure 1. Application Circuit for Half-Bridge Internal Block Diagram 8 UVLO VB DRIVER 7 PULSE GENERATOR HO HIN 2 500K HS(ON/OFF) NOISE CANCELLER R S R Q 6 VS UVLO 1 DRIVER VCC LS(ON/OFF) LIN 3 500K DELAY 5 LO 4 COM FAN7382 Rev.04 Figure 2. Functional Block Diagram © 2005 Fairchild Semiconductor Corporation FAN7382 Rev. 1.0.8 2 www.fairchildsemi.com FAN7382 High- and Low-Side Gate Driver Pin Assignments FAN7382N FAN7382M VCC HIN LIN COM 1 2 3 4 8 7 6 5 FAN7382M1 VB HO VS LO VCC HIN LIN NC NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC VB HO VS NC NC NC FAN7382 Rev.05 COM LO FAN7382 Rev.01 Figure 3. Pin Configuration (Top View) Pin Definitions Name VCC HIN LIN COM LO VS HO VB Low-Side Supply Voltage Logic Input for High-Side Gate Driver Output Logic Input for Low-Side Gate Driver Output Logic Ground and Low-Side Driver Return Low-Side Driver Output High-Voltage Floating Supply Return High-Side Driver Output High-Side Floating Supply Description © 2005 Fairchild Semiconductor Corporation FAN7382 Rev. 1.0.8 3 www.fairchildsemi.com FAN7382 High- and Low-Side Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VS VB VHO VCC VLO VIN COM dVS/dt PD(2)(3)(4) Characteristics High-side offset voltage High-side floating supply voltage High-side floating output voltage HO Low-side and logic fixed supply voltage Low-side output voltage LO Logic input voltage (HIN, LIN) Logic ground Allowable offset voltage slew rate Min. VB-25 -0.3 VS-0.3 -0.3 -0.3 -0.3 VCC-25 8-SOP Max. VB+0.3 625 VB+0.3 25 VCC+0.3 VCC+0.3 VCC+0.3 50 0.625 1.0 1.2 200 110 100 150 150 Unit V V/ns W Power dissipation 14-SOP 8-DIP 8-SOP θJA TJ TSTG Notes: Thermal resistance, junction-to-ambient Junction temperature Storage temperature 14-SOP 8-DIP °C/W °C °C 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed PD under any circumstances. Recommended Operating Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB VS VHO VLO VIN VCC TA Parameter High-side floating supply voltage High-side floating supply offset voltage High-side (HO) output voltage Low-side (LO) output voltage Logic input voltage (HIN, LIN) Low-side supply voltage Ambient temperature Min. VS+10 6-VCC VS COM COM 10 -40 Max. VS+20 600 VB VCC VCC 20 125 Unit V °C © 2005 Fairchild Semiconductor Corporation FAN7382 Rev. 1.0.8 4 www.fairchildsemi.com FAN7382 High- and Low-Side Gate Driver Electrical Characteristics VBIAS (VCC, VBS)=15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO. Symbol VCCUV+ VBSUV+ VCCUVVBSUV- Characteristics VCC and VBS supply under-voltage positive going threshold VCC and VBS supply under-voltage negative going threshold Test Condition Min. 8.2 7.6 Typ. Max. 9.2 8.7 0.6 10.0 9.6 Unit V VCCUVH VCC supply under-voltage lockout VBSUVH hysteresis ILK IQBS IQCC IPBS IPCC VIH VIL VOH VOL IIN+ IINIO+ IOVS Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Operating VBS supply current Operating VCC supply current Logic "1" input voltage Logic "0" input voltage High-level output voltage, VBIAS-VO Low-level output voltage, VO Logic "1" input bias current Logic "0" input bias current Output high short-circuit pulsed current Output low short-circuit pulsed current Allowable negative VS pin voltage for HIN signal propagation to HO IO=20mA VIN=5V VIN=0V VO=0V, VIN=5V with PW