FAN73833MX

FAN73833 — Half-Bridge Gate-Drive IC May 2008 FAN73833 Half-Bridge Gate-Drive IC Features Floating Channel for Bootstrap Operation to +600V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for Both Channels Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VDD=VBS=15V 3.3V and 5V Input Logic Compatible Outputs in Phase with Input Signals Built-in UVLO Functions for Both Channels Built-in Shoot-Through Prevention Circuit Built-in Common-Mode dv/dt Noise Canceling Circuit Internal Dead-Time: 400ns Typical Description The FAN73833 is a half-bridge gate-drive IC for driving MOSFETs and IGBTs, operating up to +600V. Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side driver under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. The UVLO circuits for both channels prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA, respectively, which is suitable for all kinds of half- and full-bridge inverters. Applications SMPS Motor Drive Inverter Fluorescent Lamp Ballast HID Ballast 8-SOP Ordering Information Part Number FAN73833M FAN73833MX Package 8-SOP Operating Temperature Range -40°C to +125°C Eco Status RoHS Packing Method Tube Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev. 1.0.0 www.fairchildsemi.com FAN73833 — Half-Bridge Gate-Drive IC Typical Application Circuit RBOOT DBOOT Up to 600V VDD LIN HIN 1 LIN 2 HIN VB 8 HO 7 CBOOT VS 6 LO 5 3 VDD 4 COM Load Figure 1. Application Circuit for Half-Bridge Internal Block Diagram 8 UVLO VB DRIVER PULSE GENERATOR NOISE CANCELLER R S R Q 7 HO SCHMITT TRIGGER INPUT 6 HS(ON/OFF) VS HIN 2 100K UVLO SHOOT-THOUGH PREVENTION LS(ON/OFF) 3 DRIVER VDD LIN 1 100K DEAD TIME { 400ns } DELAY 5 LO 4 COM Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.0 www.fairchildsemi.com 2 FAN73833 — Half-Bridge Gate-Drive IC Pin Configuration LIN HIN VDD COM 1 2 3 4 Figure 3. Pin Configuration (Top View) FAN73833 8 7 6 5 VB HO VS LO Pin Definitions Pin # 1 2 3 4 5 6 7 8 Name LIN HIN VDD COM LO VS HO VB Logic Input for Low-Side Driver Logic Input for High-Side Driver Low-Side Supply Voltage Description Logic Ground and Low-Side Driver Return Low-Side Driver Output High-Side Floating Supply Return High-Side Driver Output High-Side Floating Supply © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.0 www.fairchildsemi.com 3 FAN73833 — Half-Bridge Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol VS VB VHO VDD VLO VIN COM dVS/dt PD θJA TJ TSTG Notes: Parameter High-side Offset Voltage High-side Floating Supply Voltage High-side Floating Output Voltage HO Low-side and Logic-fixed Supply Voltage Low-side Output Voltage LO Logic Input Voltage (HIN/LIN) Logic Ground and Low-side Driver Return Allowable Offset Voltage Slew Rate Power Dissipation(1)(2)(3) Thermal Resistance, Junction-to-Ambient Junction Temperature Storage Temperature Min. VB-25 -0.3 VS-0.3 -0.3 -0.3 -0.3 VDD-25 Max. VB+0.3 625.0 VB+0.3 25.0 VDD+0.3 VDD+0.3 VDD+0.3 50 0.625 200 +150 Unit V V V V V V V V/ns W °C/W °C °C -55 +150 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB VS VDD VHO VLO VIN TA Parameter High-side Floating Supply Voltage High-side Floating Supply Offset Voltage Low-side Supply Voltage High-side (HO) Output Voltage Low-side (LO) Output Voltage Logic Input Voltage (HIN/LIN) Ambient Temperature Min. VS+15 6-VDD 15 VS COM COM -40 Max. VS+20 600 20 VB VDD VDD +125 Unit V V V V V V °C © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.0 www.fairchildsemi.com 4 FAN73833 — Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS)=15.0V, and TA=25°C, unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to VS and COM and are applicable to the respective outputs HO and LO. Symbol IQBS IQDD IPBS IPDD ILK VDDUV+ VBSUV+ VDDUVVBSUVVDDUVH VBSUVH VOH VOL IO+ IOVS Parameter Quiescent VBS Supply Current Quiescent VDD Supply Current Operating VBS Supply Current Operating VDD Supply Current Offset Supply Leakage Current VDD and VBS Supply Under-Voltage Positive-going Threshold VDD and VBS Supply Under-Voltage Negative-going Threshold VDD and VBS Supply Under-Voltage Lockout Hysteresis High-level Output Voltage, VBIAS-VO Low-level Output Voltage, VO Output High Short-Circuit Pulse Current(4) Output Low Short-Circuit Pulse Current(4) Allowable Negative VS Pin Voltage for IN Signal Propagation to HO Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Bias Current Logic "0" Input Bias Current Input Pull-down Resistance VIN=5V VIN=0V IO=20mA Condition VIN=0V or 5V VIN=0V or 5V fIN=20kHz, rms Value fIN=20kHz, rms Value VB=VS=600V Min. Typ. 35 80 420 420 Max. 100 200 750 750 10 Unit µA µA µA µA µA SUPPLY CURRENT SECTION POWER SUPPLY SECTION 8.2 7.2 9.2 8.3 0.9 10.1 9.3 V V V GATE DRIVER OUTPUT SECTION 1.0 0.6 VO=0V, VIN=5V with PW