FAN73901M

FAN73901 — High- and Low Side, Gate-Drive IC August 2008 FAN73901 High- and Low-Side, Gate-Drive IC Features Floating Channels for Bootstrap Operation to +600V Typically 2.5A/2.5A Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit Built-in Under-Voltage Lockout for Both Channels Matched Propagation Delay for Both Channels 3.3V and 5V Input Logic Compatible Output In-Phase with Input Description The FAN73901 is a monolithic high- and low-side gatedrive IC, which can drive high-speed MOSFETs and IGBTs that operate up to +600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fairchild’s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. The high current and low output voltage drop feature make FAN73901 suitable for the switching power supply, motor driver, and high-power DC-DC converter applications. Applications Half-Bridge Driver HID Lamp Ballast SMPS Motor Driver 8-SOP Ordering Information Part Number FAN73901M FAN73901MX Package 8-SOP Operating Temperature Range -40°C ~ 125°C Eco Status RoHS Packing Method Tube Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.0 www.fairchildsemi.com FAN73901 — High- and Low Side, Gate-Drive IC Typical Application Circuit 15V FAN73901 RBOOT Up to 600V DBOOT HIN 1 HIN VB 8 R1 CBOOT R2 Q1 Controller LIN 2 LIN HO 7 3 COM VS 6 OUTPUT 4 LO VDD 5 C1 R3 Q2 Load R4 FAN73901 Rev.01 Figure 1. Application Circuit for Half-Bridge Internal Block Diagram FAN73901 UVLO DRIVER PULSE GENERATOR 8 VB HIN 1 200K NOISE CANCELLER R S R Q 7 HO 6 VS VDD 5 UVLO DRIVER LIN 2 200K DELAY 4 LO 3 COM FAN73901 Rev.01 Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.0 www.fairchildsemi.com 2 FAN73901 — High- and Low Side, Gate-Drive IC Pin Configuration HIN LIN COM LO 1 2 3 4 8 7 6 5 VB HO VS VDD FAN73901 FAN73901 Rev.01 Figure 3. Pin Assignments (Top View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 Name HIN LIN COM LO VDD VS HO VB Description Logic Input for High-Side Gate Driver Output Logic Input for Low-Side Gate Driver Output Low-Side Driver Return Low-Side Driver Output Low-Side and Logic Part Supply Voltage High-Voltage Floating Supply Return High-Side Driver Output High-Side Floating Supply © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.0 www.fairchildsemi.com 3 FAN73901 — High- and Low Side, Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol VS VB VHO VDD VLO VIN dVS/dt PD θJA TJ TSTG Notes: Characteristics High-Side Floating Supply Offset Voltage High-Side Floating Supply Voltage High-Side Floating Output Voltage HO Low-Side and Logic Fixed Supply Voltage Low-Side Output Voltage LO Logic Input Voltage (HIN and LIN) Allowable Offset Voltage Slew Rate Power Dissipation(1)(2)(3) Thermal Resistance, Junction-to-Ambient Junction Temperature Storage Temperature Min. VB-25 -0.3 VS-0.3 -0.3 -0.3 -0.3 Max. VB+0.3 625.0 VB+0.3 25.0 VDD+0.3 VDD+0.3 50 0.625 200 +150 +150 Unit V V V V V V V/ns W °C/W °C °C 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VB VS VHO VDD VLO VIN TA Parameter High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage High-Side Output Voltage Low-Side and Logic Supply Voltage Low-Side Output Voltage Logic Input Voltage (HIN and LIN) Operating Ambient Temperature Min. VS+10 6-VDD VS 10 COM COM -40 Max. VS+20 600 VB 20 VDD VDD +125 Unit V V V V V V °C © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.0 www.fairchildsemi.com 4 FAN73901 — High- and Low Side, Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS)=15.0V, VS=COM, TA=25°C, unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are referenced to COM and VS is applicable to the respective output signals HO and LO. Symbol VDDUV+ VBSUV+ VDDUVVBSUV- Characteristics VDD and VBS Supply Under-Voltage Positive-Going Threshold VDD and VBS Supply Under-Voltage Negative-Going Threshold Test Condition Min. 8.0 7.4 Typ. 8.8 8.3 0.5 Max. Unit 9.8 9.0 V V V 50 µA µA µA µA µA V 1.2 V µA µA KΩ 1.0 35 V mV A A -7.0 V POWER SUPPLY SECTION (VDD AND VBS) VDDUVH VDD and VBS Supply Under-Voltage VBSUVH Lockout Hysteresis Voltage ILK IQBS IQDD IPBS IPDD VIH VIL IIN+ IINRIN VOH VOL IO+ IOVS Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VDD Supply Current Operating VBS Supply Current Operating VDD Supply Current Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Input Bias Current Logic "0" Input Bias Current Input Pull-Down Resistance High-Level Output Voltage, VBIAS-VO Low-Level Output Voltage, VO Output High, Short-Circuit Pulsed Current(4) Output Low, Short-Circuit Pulsed Current(4) Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO No Load No Load VO=0V, VIN=5V with PW