FAN73933M

FAN73933 — Half-Bridge Gate Driver December 2009 FAN73933 Half-Bridge Gate Drive IC Features Floating Channel for Bootstrap Operation to +600V Typically 2.5A/2.5A Sourcing/Sinking Current Driving Capability Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15V Output in Phase with Input Signal 3.3V and 5V Input Logic Compatible Matched Propagation Delay for Both Channels Built-in UVLO Functions for Both Channels Built-in Common-Mode dv/dt Noise Cancelling Circuit Programmable Dead-Time Control Function Internal 220ns Minimum Dead Time at RDT=0Ω Description The FAN73933 is a half-bridge, gate-drive IC with programmable dead-time control functions that can drive high-speed MOSFETs and IGBTs operating up to +600V. It has a buffered output stage with all NMOS transistors designed for high-pulse-current driving capability and minimum cross-conduction. Fairchild’s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. The high-current and low-output voltage drop feature makes this device suitable for diverse half- and fullbridge inverters; motor drive inverters, switching mode power supplies, induction heating, and high-power DCDC converter applications. Applications High-Speed Power MOSFET and IGBT Gate Driver Induction Heating High-Power DC-DC Converter Synchronous Step-Down Converter Motor Drive Inverter 14-SOP Ordering Information Part Number FAN73933M FAN73933MX Package 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 Inch Narrow Body, 225SOP Operating Temperature Range -40°C to +125°C Eco Status RoHS Packing Method Tube Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com FAN73933 — Half-Bridge Gate Driver Typical Application Diagrams +15V RBOOT DBOOT FAN73933 Controller HIN LIN 1 HIN 2 LIN 3 RDT 4 DT 5 COM 6 LO 7 VDD VS 11 NC 10 NC 9 NC 8 R3 VSS NC 14 VB 13 HO 12 CBOOT R1 Up to 600V R2 Load R4 Figure 1. Typical Application Circuit Internal Block Diagram 13 VB UVLO DRIVER PULSE GENERATOR HIN 1 250K HS(ON/OFF) NOISE CANCELLER R S R Q 12 HO SCHMITT TRIGGER INPUT 11 VS 7 VDD LIN 2 250K RDTINT SHOOT THOUGH PREVENTION UVLO DRIVER DT 4 DEAD-TIME { DTMIN=220ns } LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY 6 LO VSS 3 5 Pin 8, 9, 10 and 14 are no connection COM Figure 2. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 2 FAN73933 — Half-Bridge Gate Driver Pin Configuration HIN LIN VSS DT COM LO VDD 1 2 14 13 NC VB HO VS NC NC NC FAN73933 3 4 5 6 7 12 11 10 9 8 Figure 3. Pin Configurations (Top View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Name HIN LIN VSS DT COM LO VDD NC NC NC VS HO VB NC Description Logic Input for High-Side Gate Driver Output Logic Input for Low-Side Gate Driver Output Logic Ground Dead-Time Control with External Resistor (Referenced to VSS) Ground Low-Side Driver Return Supply Voltage No Connection No Connection No Connection High-Voltage Floating Supply Return High-Side Driver Output High-Side Floating Supply No Connection © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 3 FAN73933 — Half-Bridge Gate Driver Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified. Symbol VB VS VHO VLO VDD VIN DT VSS dVS/dt PD θJA TJ TSTG Notes: Characteristics High-Side Floating Supply Voltage High-Side Floating Offset Voltage High-Side Floating Output Voltage Low-Side Output Voltage Low-Side and Logic Fixed Supply Voltage Logic Input Voltage (HIN and LIN) Programmable Dead-Time Pin Voltage Logic Ground Allowable Offset Voltage Slew Rate Power Dissipation(1, 2, 3) Thermal Resistance Junction Temperature Storage Temperature Min. -0.3 VB-25.0 VS-0.3 -0.3 -0.3 -0.3 -0.3 VDD-25 Max. 625.0 VB+0.3 VB+0.3 VDD+0.3 25.0 VDD+0.3 VDD+0.3 VDD+0.3 ± 50 1 110 +150 Unit V V V V V V V V V/ns W °C/W °C °C -55 +150 1 Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2 Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection, and JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 3 Do not exceed maximum PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VB VS VHO VDD VLO VIN DT VSS TA Parameter High-Side Floating Supply Voltage High-Side Floating Supply Offset Voltage High-Side Output Voltage Low-Side and Logic Fixed Supply Voltage Low-Side Output Voltage Logic Input Voltage (HIN and LIN) Programmable Dead-Time Pin Voltage Logic Ground Operating Ambient Temperature Min. VS+10 6-VDD VS 10 COM VSS VSS -5 -40 Max. VS+20 600 VB 20 VDD VDD VDD +5 +125 Unit V V V V V V V V °C © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 4 FAN73933 — Half-Bridge Gate Driver Electrical Characteristics VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, DT=VSS and TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol IQDD IQBS IPDD IPBS ILK VDDUV+ VBSUV+ VDDUVVBSUVVDDUVHVBSUVH VIH VIL IIN+ IINRIN VOH VOL IO+ IOVS Characteristics Quiescent VDD Supply Current Quiescent VBS Supply Current Operating VDD Supply Current Operating VBS Supply Current Offset Supply Leakage Current VDD and VBS Supply Under-Voltage Positive-Going Threshold Voltage VDD and VBS Supply Under-Voltage Negative-Going Threshold Voltage VDD and VBS Supply Under-Voltage Lockout Hysteresis Voltage Logic “1” Input Voltage for HO & Logic “0” for LO Logic “0” Input Voltage for HO & Logic “1” for LO Logic Input High Bias Current Logic Input Low Bias Current Logic Input Pull-Down Resistance High-Level Output Voltage (VBIAS - VO) Low-Level Output Voltage Output High, Short-Circuit Pulsed Current(4) Output Low, Short-Circuit Pulsed Current(4) Allowable Negative VS Pin Voltage for IN Signal Propagation to HO Test Condition VIN=0V or 5V VIN=0V or 5V fIN=20KHz, No Load CL=1nF, fIN=20KHz, rms VB=VS=600V Min. Typ. Max. Unit 0.9 50 1.3 450 1.5 100 1.9 800 10 mA μA mA μA μA POWER SUPPLY SECTION BOOTSTRAPPED SUPPLY SECTION VIN=0V, VDD=VBS=Sweep VIN=0V, VDD=VBS=Sweep VIN=0V, VDD=VBS=Sweep 8.0 7.4 9.0 8.4 0.6 10 9.4 V V V INPUT LOGIC SECTION 2.5 0.8 VIN=5V VIN=0V 100 No Load No Load VHO=0V, VIN=5V, PW ≤10µs VHO=15V,VIN=0V, PW ≤10µs 2.0 2.0 2.5 2.5 -9.8 -7.0 250 1.5 100 20 50 2 V V μA μA KΩ V mV A A V GATE DRIVER OUTPUT SECTION Note: 4. These parameters guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 5 FAN73933 — Half-Bridge Gate Driver Dynamic Electrical Characteristics VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, CL=1000pF, DT=VSS and TA=25°C, unless otherwise specified. Symbol tON tOFF MtON MtOFF tR tF DT MDT Parameter Turn-On Propagation Delay Time(5) Turn-Off Propagation Delay Time Delay Matching, HO & LO Turn-On Delay Matching, HO & LO Turn-Off Turn-On Rise Time Turn-Off Fall Time Dead Time: LO Turn-Off to HO Turn-On & HO Turn-Off to LO Turn-On Dead-Time Matching=|DTLO-HO - DTHO-LO| Conditions VS=0V, RDT=0Ω VS=0V Min. Typ. 160 160 0 0 Max. 230 230 50 50 60 35 270 600 50 100 Unit ns ns ns ns ns ns ns ns ns ns VS=0V VS=0V RDT=0Ω RDT=300KΩ RDT=0Ω RDT=300KΩ 170 400 40 20 220 500 0 0 Note: 5 The turn-on propagation display does not include dead time. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 6 FAN73933 — Half-Bridge Gate Driver Typical Characteristics 230 210 190 230 210 190 tON [ns] tOFF [ns] 170 150 130 110 90 -40 High-Side Low-Side -20 0 20 40 60 80 100 120 170 150 130 110 90 -40 High-Side Low-Side -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 4. Turn-On Propagation Delay vs. Temperature Figure 5. Turn-Off Propagation Delay vs. Temperature 60 50 40 tR [ns] High-Side Low-Side 30 High-Side Low-Side tF [ns] 20 30 20 10 0 -40 10 -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 6. Turn-On Rise Time vs. Temperature Figure 7. Turn-Off Fall Time vs. Temperature 300 50 25 MDT [ns] DT1 DT2 (RDT=0Ω) DT [ns] 250 0 200 -25 (RDT=0Ω) -50 -40 -20 0 20 40 60 80 100 120 150 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 8. Dead Time (RDT=0Ω) vs. Temperature Figure 9. Dead Time Matching (RDT=0Ω) vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 7 FAN73933 — Half-Bridge Gate Driver Typical Characteristics (Continued) 600 575 50 40 550 DT [ns] 525 500 475 450 425 400 -40 -20 0 20 40 60 80 DT1 DT2 (RDT=300KΩ) 100 120 MDT [ns] 30 20 10 (RDT=300KΩ) 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 10. Dead Time (RDT=300KΩ) vs. Temperature Figure 11. Dead Time Matching (RDT=300KΩ) vs. Temperature 50 40 600 Delay Matching [ns] 30 20 10 0 -10 -20 -30 -40 -50 -40 -20 0 20 40 60 80 MTON MTOFF (RDT=0Ω) 100 120 500 DT [ns] 400 300 200 100 0 50 100 150 200 250 300 Temperature [°C] RDT [KΩ] Figure 12. Delay Matching vs. Temperature Figure 13. Dead Time vs. RDT 1500 1300 100 80 IQDD [μA] 1100 900 700 500 300 -40 IQBS [μA] 60 40 20 -20 0 20 40 60 80 100 120 0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 14. Quiescent VDD Supply Current vs. Temperature Figure 15. Quiescent VBS Supply Current vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 8 FAN73933 — Half-Bridge Gate Driver Typical Characteristics (Continued) 1900 1700 1500 800 700 600 IPDD [μA] IPBS [μA] 500 400 300 200 100 -40 1300 1100 900 700 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 16. Operating VCC Supply Current vs. Temperature Figure 17. Operating VBS Supply Current vs. Temperature 10.0 9.5 9.5 9.0 VDDUV+ [V] 9.0 VDDUV- [V] -20 0 20 40 60 80 100 120 8.5 8.5 8.0 8.0 -40 7.5 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 18. VDD UVLO+ vs. Temperature Figure 19. VDD UVLO- vs. Temperature 10.0 9.5 9.5 9.0 VBSUV+ [V] VBSUV- [V] 9.0 8.5 8.5 8.0 8.0 -40 -20 0 20 40 60 80 100 120 7.5 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO- vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 9 FAN73933 — Half-Bridge Gate Driver Typical Characteristics (Continued) 2.0 High-Side Low-Side 1.5 0.4 High-Side Low-Side 0.2 VOH [V] VOL [V] 1.0 0.0 0.5 -0.2 0.0 -40 -20 0 20 40 60 80 100 120 -0.4 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 22. High-Level Output Voltage vs. Temperature Figure 23. Low-Level Output Voltage vs. Temperature 3.0 High-Side Low-Side 2.5 3.0 High-Side Low-Side 2.5 VIH [V] 2.0 VIH [V] -20 0 20 40 60 80 100 120 2.0 1.5 1.5 1.0 -40 1.0 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 24. Logic High Input Voltage vs. Temperature Figure 25. Logic Low Input Voltage vs. Temperature 50 High-Side Low-Side 40 -7 -8 -9 IIN+ [μA] 30 VS [V] -10 -11 20 10 -12 -13 -40 0 -40 -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 26. Logic Input High Bias Current vs. Temperature Figure 27. Allowable Negative VS Voltage vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 10 FAN73933 — Half-Bridge Gate Driver Typical Characteristics (Continued) 230 210 190 230 210 190 tON [ns] 170 150 130 110 90 10 High-Side Low-Side 12 14 16 18 20 tOFF [ns] 170 150 130 110 90 10 High-Side Low-Side 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 28. Turn-On Propagation Delay vs. Supply Voltage Figure 29. Turn-Off Propagation Delay vs. Supply Voltage 60 50 40 tR [ns] High-Side Low-Side 35 30 25 High-Side Low-Side tF [ns] 12 14 16 18 20 20 15 30 20 10 10 0 10 5 0 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 30. Turn-On Rise Time vs. Supply Voltage Figure 31. Turn-Off Fall Time vs. Supply Voltage 1500 1300 100 80 IQDD [μA] 1100 900 700 500 300 10 IQBS [μA] 60 40 20 12 14 16 18 20 0 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 32. Quiescent VDD Supply Current vs. Supply Voltage Figure 33. Quiescent VBS Supply Current vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 11 FAN73933 — Half-Bridge Gate Driver Typical Characteristics (Continued) 2.0 High-Side Low-Side 1.5 0.4 High-Side Low-Side 0.2 VOH [V] VOL [V] 1.0 0.0 0.5 -0.2 0.0 10 12 14 16 18 20 -0.4 10 12 14 16 18 20 Supply Voltage [V] Supply Voltage [V] Figure 34. High-Level Output Voltage vs. Supply Voltage Figure 35. Low-Level Output Voltage vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 12 FAN73933 — Half-Bridge Gate Driver Switching Time Definitions HIN LIN 1 2 3 4 5 HIN LIN NC 14 VB 13 +15V HO 1nF FAN73933 VSS DT COM LO VDD HO 12 VS 11 10μF 100nF NC 10 NC NC LO 1nF +15V 10μF 100nF 6 7 9 8 Figure 36. Switching Time Test Circuit LIN HIN Shoot Though Prevent Shoot Though Prevent HO LO DT DT DT DT Figure 37. Input/Output Timing Diagram LIN 50% 50% 50% More than dead-time More than dead-time 50% HIN 50% tOFF 90% tON tOFF 90% LO 10% tOFF 90% tON HO 10% Figure 38. Switching Time Waveform Definitions © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 13 FAN73933 — Half-Bridge Gate Driver Application Information Negative VS Transient The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at the emitter of the high-side switching device when the high-side switch is turned off in half-bridge applications. If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load; a current commutation occurs from high-side switch, Q1, to the diode, D2, in parallel with the low-side switch of the same inverter leg. Then the negative voltage present at the emitter of the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, D2, as shown in Figure 39. DC+ Bus Q1 D1 iLOAD ifreewheeling D2 Q2 Figure 41. and Figure 42. show the commutation of the load current between the high-side switch, Q1, and lowside freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire bonding to the PCB tracks are jumped together in LC and LE for each IGBT. When the high-side switch, Q1, and low-side switch, Q4, are turned on; the VS1 node is below DC+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as shown in Figure 41. When the high-side switch, Q1, is turned off and Q4 remains turned on, the load current to flows the low-side freewheeling diode, D3, due to the inductive load connected to VS1 as shown in Figure 42. The current flows from ground (which is connected to the COM pin of the gate driver) to the load and the negative voltage present at the emitter of the high-side switching device. In this case, the COM pin of the gate driver is at a higher potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3. DC+ Bus VS1 Load VS2 Q3 D3 D4 Q4 LC1 VLC1 LC2 Q2 Q1 D1 iLOAD LE1 VLE1 D2 ifreewheeling LE2 VS2 VLC4 Figure 39. Half-Bridge Application Circuits This negative voltage can be trouble for the gate driver’s output stage. There is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal missing, and latch-up problems because it directly affects the source VS pin of the gate driver, as shown in Figure 40. This undershoot voltage is called “negative VS transient. VS1 LC3 Load LC4 Q4 Q3 D3 D4 LE3 VLE4 LE4 Figure 41. Q1 and Q4 Turn-On Q1 GND DC+ Bus LC1 LC2 Q2 D1 iLOAD ifreewheeling D2 Q1 LE1 VS GND Freewheeling LE2 VS2 VLC4 VS1 LC3 VLC3 Load LC4 Q4 Q3 D3 D4 LE3 VLE3 VLE4 LE4 Figure 40. VS Waveforms During Q1 Turn-Off Figure 42. Q1 Turn-Off and D3 Conducting © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 14 FAN73933 — Half-Bridge Gate Driver The FAN73933 has a negative VS transient performance curve, as shown in Figure 43. Placement of Components The recommended selection of component is as follows: Place a bypass capacitor between the VDD and VSS pins. A ceramic 1µF capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic elements. The bypass capacitor from VCC to COM supports both the low-side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. The bootstrap resistor, RBOOT, must be considered in sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground). Recommended use is typically 5 ~ 10Ω, which increases the VBS time constant. If the votage drop of the bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. The bootstrap capacitor, CBOOT, uses a low-ESR capacitor, such as a ceramic capacitor. It is stongly recommended that the placement of components is as follows: Place components tied to the floating voltage pins (VB and VS) near the respective high-voltage portions of the device and the FAN73933. NC (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins (see Figure 3.). Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC. Locate the bootstrap diode, DBOOT, as close as possible to bootstrap capacitor, CBOOT. The bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. -100 -90 -80 -70 -60 VS [V] -50 -40 -30 -20 -10 0 0 100 200 300 400 500 600 700 800 900 1000 Pulse Width [ns] Figure 43. Negative VS Transient Chracteristic Even though the FAN73933 has been shown able to handle these negative VS tranient conditions, it is strongly recommended that the circuit designer limit the negative VS transient as much as possible by careful PCB layout to minimize the value of parasitic elements and component use. The amplitude of negative VS voltage is proportional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. General Guidelines Printed Circuit Board Layout The layout recommended for minimized parasitic elements is as follows: Direct tracks between switches with no loops or deviation. Avoid interconnect links. These can add significant inductance. Reduce the effect of lead-inductance by lowering package height above the PCB. Consider co-locating both power switches to reduce track length. To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 15 FAN73933 — Half-Bridge Gate Driver Physical Dimensions 8.76 8.36 7.62 14 8 A 0.65 B 5.60 4.15 3.75 B 6.00 B 1.70 #1 1.27 PIN ONE INDICATOR (0.27) TOP VIEW #1 7 1.27 0.51 0.36 0.20 CBA LAND PATTERN RECOMMENDATION 1.80 MAX 1.65 1.45 SEE DETAIL A (R0.20) C 0.05MIN 1.27 SIDE VIEW 0.10 MAX C END VIEW 0.30 0.15 B NOTES: A) THIS DRAWING COMPLIES WITH JEDEC MS-012 EXCEPT AS NOTED. B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-012 VALUE. C) ALL DIMENSIONS ARE IN MILLIMETERS. D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. E) LANDPATTERN STANDARD: SOIC127P600X145-14M F) DRAWING FILE NAME AND REVISION : M14CREV1 GAGE PLANE 8° (R0.10) 0.36 SEATING PLANE DETAIL A 0.90 0.50 Figure 44. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 Inch Narrow Body, 225SOP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 16 FAN73933 — Half-Bridge Gate Driver © 2009 Fairchild Semiconductor Corporation FAN73933 • Rev. 1.0.0 www.fairchildsemi.com 17