FAN7554_03

www.fairchildsemi.com FAN7554 Versatile PWM Controller Features • • • • • • • • • • • • • • • Current mode control Pulse by pulse current limiting Low external components Under voltage lockout(UVLO): 9V/15V Stand-by current: typ. 100uA Power saving mode current: typ. 200uA Operating current: typ. 7mA Soft start On/off control Over load protection(OLP) Over voltage protection(OVP) Over current protection(OCP) Over current limit(OCL) Operating frequency up to 500kHz 1A totem-pole output current Description The FAN7554 is a fixed frequency current mode PWM controller. It is specially designed for off-line and DC to DC converter applications with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, an ON/OFF control, a high gain error amplifier, a current sensing comparator, and a high current totem-pole output. The FAN7554 has various protection functions such as an over load protection, an over current protection, and the over voltage protection, which include built-in auto restart circuit. The FAN7554 is available in the 8-DIP package as well as the 8-SOP package. 8-DIP Applications • Off-Line & DC-DC converter 8-SOP 1 1 Rev. 1.0.3 ©2003 Fairchild Semiconductor Corporation FAN7554 Internal Block Diagram Rt/Ct 4 3.5V + _ _ S Q R off PWR / SAVE Vref 8 + 34V + _ + _ _ _ OVP Vcc 7 Vref 100uA + _ UVLO Vref S/S 2 1k + 0.3V 1.5V on 15V/9V OSC CLK PWM + _ S Q R 14V FB 1 1mA Absolute Maximum Ratings ( Ta = 25°C, unless otherwise specified ) Parameter Supply voltage Output current Input voltage to FB pin Input voltage to IS pin Power dissipation at TA ≤ 25°C 8-DIP 8-SOP Operating temperature Storage temperature Thermal resistance, junction-to-air (Note1) 8-DIP 8-SOP Symbol Vcc IO VFB VIS PD TOPR TSTG Rθja Value 30 ±1 -0.3 to VSD -0.3 to VOC 0.85 0.42 -25 to +85 -55 to +150 147.8 291.4 Unit V A V V W °C °C °C/W Note: 1. Junction -to -air thermal resistance test environments. - JESD51-2 : Integrated circuits thermal test method environmental conditions-natural convection (still air). - JESD51-3 : Low effective thermal conductivity test board for leaded surface mount packages. - JESD51-10 : Test boards for through-hole perimeter leaded package thermal measurements. 2 _ 6V + + _ MAX. 1V 2R R 6 OUT Vref Vcc 5uA OLP OVP-out OCL-out Offset(0.1V) 3 OCL S R UVLO-out Q 2V IS 5 GND FAN7554 Temperature Characteristics ( -25°C ≤ Ta ≤ 85°C ) Parameter Vref temperature stability Fosc temperature stability Symbol ∆VREF3 ∆FOSC2 Value ±0.5 ±5 Unit % % PIN Array Vref Vcc OUT GND 8 7 6 5 YWW FA N7554 1 FB 2 S/S 3 IS 4 Rt/Ct PIN Definitions Pin Number 1 2 3 4 5 6 7 8 Pin Name FB S/S IS Rt/Ct GND OUT Vcc Vref Soft start Non-inverting(+) input of PWM comparator, OCL sensing terminal Oscillator time constant(Rt/Ct) Ground Output of gate driver Power supply Output of 5V reference Pin Function Description Inverting(-) input of pwm comparator, on/off control & OLP sensing terminal. 3 FAN7554 Electrical Characteristics (Ta = 25°C, Vcc=16V, Rt=10kΩ, Ct=3.3nF unless otherwise specified) Parameter < REFERENCE SECTION > Reference output voltage Line regulation Load regulation Short circuit output current < OSCILLATOR SECTION > Oscillation frequency Frequency change with Vcc Ramp high voltage Ramp low voltage Discharge current < PWM SECTION > Sense threshold voltage Feedback threshold voltage Feedback source current Max. duty cycle Min. duty cycle < PROTECTION SECTION > Shutdown delay current Shutdown feedback voltage Over current protection Over voltage protection < ON/OFF CONTROL SECTION > Off mode sink current Off threshold voltage < SOFT-START SECTION > Soft start current Soft start limit voltage Low output voltage1 High output voltage1 Low output voltage2 High output voltage2 Rising time (Note1) Falling time (Note1) Start threshold voltage Min. operating voltage VTH(ST) VOPR(M) 13.2 8.2 15 9 16.2 10.2 V V VOL1 VOH1 VOL2 VOH2 tR tF VCC = 18V, IO = 50mA VCC = 18V, IO = -50mA VCC = 18V, IO = 200mA Vcc = 18V, Io = -200mA Tj = 25°C, CL = 1nF Tj = 25°C, CL = 1nF 13 12 0.15 15 1.5 14 80 40 0.4 17 2.5 16 V V V V ns ns IS/S VLIM(S/S) VFB = 5V, VS/S = 0V Vcc = 16V 1.1 5.2 mA V ISINK VOFF VFB < VTH(FB), VS/S = 5V VFB < VTH(FB) 1.2 4 1.5 1.8 mA V ISD VSD VOC VOVP 4V ≤ VFB ≤ VSD VFB > 5V VIS > 1.5V, ton > 500nS 3.5 5.4 1.6 30 5 6 2 34 6.5 6.6 2.4 38 uA V V V VTH(IS) VTH(FB) IFB D(MAX) D(MIN) VFB = 5V VIS = 0V VFB = 0V, VS/S = 5V 0.8 0.2 92 1.0 0.3 1.0 95 1.2 0.4 98 0 V V mA % % FOSC ∆FOSC1 VRH VRL Idisch Tj = 25°C Vcc = 12V ~ 25V VRT/CT = 3.3V 45 6.1 50 0.05 2.8 1.2 55 1.0 9.4 kHz % V V mA VREF ∆VREF1 ∆VREF2 ISC Tj =25°C , Iref =1mA Vcc =12V ~ 25V Iref =1mA ~ 20mA Tj = 25°C 4.90 5.00 6 6 0.1 5.10 20 25 0.18 V mV mV A Symbol Conditions Min. Typ. Max. Unit 4 FAN7554 Electrical Characteristics (Continued) (Ta = 25°C, Vcc=16V, Rt =10kΩ, Ct = 3.3nF unless otherwise specified) Parameter Start-up current Operating supply current Off State current Symbol IST IOP IOFF Conditions VFB 5kΩ] tc td CT Ct 4 Discharge Discharge Gate Drive Ct Internal clock Vhigh(2.8V) 2.8V /1.2V Sawtooth waveform Vlow(1.2V) tc td [ Rt < 5kΩ] FAN7554 Internal clock Figure 14. Oscillator Circuit Figure 15. Sawtooth & Clock Waveform 9 FAN7554 Feedback As shown in figure16, the internal oscillator clock turns on the MOSFET. The feedback comparator operates to turn it off again, when the MOSFET current reaches a set value proportional to Vfb. The feedback capacitor Cfb is charged by the internal current sources , 1mA and 5uA, and is discharged by the secondary side photo-coupler to control the output voltage. DRIN OSC Vfb 2R Vfb/3 S R 1mA Cfb 5uA 5V Vcc R Q OUT 6 IS 3 FAN7554 Rs Vsense 1 FB Figure 16. Feedback & PWM Circuit Delayed Shutdown During the normal operation, the feedback voltage is between 0~3V. If the output terminal overloads or an error happens to the feedback loop, the delayed shutdown circuit operates. When the feedback voltage is less than 3V, the feedback capacitor is charged by current sources, 1mA and 5uA; when the feedback voltage becomes greater than 3V, the capacitor is charged by the 5uA current source because diode D1 turns off. When the feedback voltage is less than 3V, the charge slope becomes an exponential function and, when it is greater than 3V, the charge slope becomes linear. When the feedback voltage reaches almost 6V, the FAN7554 shuts down. The shut down circuit is configured for auto-restart, so it automatically restarts when Vcc reaches the under voltage 9V. FB 1 5uA Vcc 2R D1 1mA Cfb 5V R S R Q DRIN OSC OUT 6 IS 3 Rs Over Current Comparator S R Q Shutdown 6V UVLO - out FAN7554 Figure 17-A . Delayed Shutdown & Feedback Circuit 10 FAN7554 Vfb 6V Slope (dv/dt) = 5uA / Cfb Shutdown start point 3V t1 t2 Figure 17-B . Delayed Shutdown & Feedback Waveform t Gate Driver The gate drive circuit has the totem-pole output configuration. The output has 1A peak current and 200mA average current drive ability. 7 Clock DRAIN OUT 6 Q Shutdown FAN7554 Figure 18. Gate Drive Circuit ON/OFF Control The FAN7554 is able to use the feedback pin for ON/OFF control by placing NPN transistor between the cathode of the KA431 and ground as shown in figure 19. When the transistor turns on, the current flows through the photo diode and saturates the photo transistor. As a result, the feedback voltage is dropped to zero. When the feedback voltage is below 0.3V, the soft start voltage starts to discharge by connecting the internal resistor 1kΩ in parallel with the external capacitor Cs. When the soft start voltage becomes less than 1.5V, all the blocks in the FAN7554 are turned off , with the exceptions of the UVLO block and ON/OFF control block. The operation current is about 200uA. So the stand-by power is reduced and SMPS efficiency is improved. When the feedback voltage exceeds 0.3V, the FAN7554 normally operates by turning on Vref block. 11 FAN7554 Vref 3.5V S 100uA Q OFF PWR / SAVE 5V Vref R VCC 7 UVLO S/S 2 1K Ω 0.3V Vo Cs Cfb 1.5V ON 15V/9V Good logic Internal bias FB 1 5uA Vcc Remote control FAN7554 Figure 19. ON/OFF Control Circuit Vref 5V Icc 4.5mA 0.2mA t VS/S 5V Slope (dv/dt) = 100uA / Cs Slope (dv/dt) = 1kΩ * Cs 3V Slope (dv/dt) = (1mA +100uA) / Cs 1.5V t Vfb 0.3~3V Slope (dv/dt) = (1mA +5A) / Cfb OFF Signal Slope (dv/dt) = (5uA) / Cfb 0.3V Normal State ON Signal OFF State Figure 20. ON-OFF Control Circuit Waveforms Normal State t 12 FAN7554 Protection Circuits The FAN7554 has many built-in protection circuits that do not need additional components, providing reliability without cost increase. These protection circuits have the auto-restart configuration. In this configuration, the protection circuits reset when Vcc is below UVLO stop threshold (9V) and restarts when Vcc is above UVLO start threshold voltage (15V) Over Voltage Protection Abnormalities may occur in the SMPS secondary side feedback circuit. First, when the feedback pin is short to the ground, the feedback voltage is zero and the FAN7554 is unable to start switching. Second, when the feedback circuit is open, the secondary voltage generally becomes much greater than the rated voltage as the primary side continues to switch at the maximum current level. This may cause the blowing off the fuse or, in serious cases, fires. It is possible that the devices directly connected to the secondary output without a regulator could be destroyed. Even in these cases, the over voltage protection circuit operates. Since Vcc is proportional to the output , in an over voltage situation, it also will increase. In the FAN7554, the protection circuit operates when Vcc exceeds 34V. Therefore ,in normal operation, Vcc must be set below 34V. Over Load Protection An overload is the state in which the load is operating normally but in excess of the preset load. The overload protection circuit can force the FAN7554 to stop its operation . The protection can also operate in transient states such as initial SMPS operation. Because the transient state returns to the normal state after a fixed time, the protection circuit need not to operate during this time. That is, the FAN7554 needs the time to detect and decide whether it is an overload condition or not. The protection circuit can be prevented from operating during transient states by ensuring that a certain amount of time passes before the protection circuit operates. The above operations are executed as follows: Since the FAN7554 adopts a current mode, it is impossible for current to flow above a maximum level. For a fixed input voltage, this limits power. Therefore, if the power at the output exceeds this maximum, Vo, shown in figure21, becomes less than the set voltage, and the KA431pulls in only the given minimum current. As a result, the photo-coupler’s secondary side current becomes zero. The same goes for the photo-coupler’s primary side current. Consequently, when the full current 1mA flows through the internal resistor (2R + R = 3R), Vfb becomes approximately 3V and from that time, the 5uA current source begins to charge Cfb, the photo-coupler’s secondary current is almost zero. The FAN7554 shuts down when Vfb reaches 6V. 6V S R Q Shutdown Vo Vfb UVLO out OSC 1mA Cfb 5uA 5V Vcc R 2R S R Q FAN7554 KA431 1 FB V 6V Shutdown start point 3V t1 Time Constant = 3R * Cfb t2 5uA = (Cfb *3V)/t2 t Figure 21. Delayed Shutdown 13 FAN7554 FAN7554 Flyback Converter Demo Circuit (Fsw:100kHz) BD NTC R103 T101 D201 L201 12V/3.5A R203 C102 C104 R104 C201 D101 R101 C103 C301 C302 R102 C202 R204 LF101 R201 C101 D102 R106 R105 TNR FUSE D103 8 7 6 5 R202 Q101 IC301 R205 C203 IC201 R108 Vref Vcc OUT GND R107 FAN7554 FB 1 IC101 C109 R109 Input:85 ~ 265VAC 50/60Hz C105 IC301 S/S 2 IS Rt/Ct 3 4 R110 C108 C106 C107 R111 14 FAN7554 Part List For FAN7554 Flyback Converter Demo Board Part FUSE NTC R101 R102 R103, R104 R105 R106 R107 R108 R109 R110 R201 R202 R203 R204 R205 Q101 IC101 IC201 IC301 Value FUSE 250 2A NTC 5D-11 RESISTOR 330kΩ 100kΩ 22Ω 4.7kΩ 12kΩ 10Ω 1kΩ 0.5Ω 1kΩ 1kΩ 4.7kΩ 1.2kΩ MOSFET FQP6N70 IC FAN7554 KA431 Opto-coupler Fairchild Fairchild Fairchild Fairchild D201 D101 D102 D103 BD 1W 1W 2W LF101 L201 INDUCTOR 30mH 6.4uH DIODE MBRF10100CT UF4007 1N4148 UF4004 G3SBA60 Fairchild Fairchild C101 C102 C103 C104 C105 C106 C107 C108 C109 C201 C202 C203 C301 C302 Note Part Value CAPACITOR 100nF/ 275V 100nF/ 275V 470nF/ 400WV 103/ 1kV 104 1uF/ 10V 101 122 22uF/ 50V 330uF 330uF 104 Box Capacitor Box Capacitor Electrolytic Film Capacitor Ceramic Electrolytic Ceramic Ceramic Electrolytic Electrolytic Electrolytic Ceramic Note 15 FAN7554 Transformer Specification Schematic Diagram (Top view) 3mm 1 12 10 3 9 8 11 4 6mm 2mm NP NB NP N12V N12V NP bottom top NB 5 7 6 Winding Specification No. NP N12V NP NB Pin(S → F) 1→3 7 → 11 1→3 5→4 Wire 0.35φ × 1 0.35φ × 4 0.35φ × 1 0.35φ × 1 Turns 44 12 44 13 Winding Method - Electrical Characteristic Closure Inductance Leakagel Pin 1-3 1-3 Spec. 400uH ±10% 10uH MAX . Remarks 100kHz, 1V 2nd All short 16 FAN7554 FAN7554 forward converter demo circuit ( fsw:100kHz) BD D201 T101 C104 R105 C102 R103 R104 L201 +12V/2A C201 D102 C202 C301 C302 D202 L101 R106 C101 R101 IC2 FUSE R102 R113 D101 RT101 C106 F/B S/S 1 2 IS Rt/Ct 3 4 +5V/3A L202 R201 C203 C204 R202 C103 R107 D103 D104 C105 R108 Q101 R110 R109 R203 5 8 7 6 Vref Vcc OUT GND FAN7554 Input: 85 ~ 265VAC 50/60Hz IC301 C110 C111 C107 C108 R112 C109 R111 IC301 R204 C205 IC201 17 FAN7554 Part List For FAN7554 Forward Converter Demo Board Part FUSE RT101 R101 R102 R103, R104 R105, R106 R107 R108 R109 R110 R111 R112 R113 R201, R202 R203 R204 Q101 IC101 IC201 IC301 Value FUSE 250 2A NTC DSC 10D-11 RESISTOR 330kΩ 56kΩ 220kΩ 10Ω 20Ω 4.7kΩ 1.2kΩ 0.5Ω//0.5Ω//0.5Ω 1kΩ 12kΩ 10kΩ 1kΩ 330Ω MOSFET SSH8N80 IC FAN7554 KA431 Opto-Coupler Fairchild Fairchild Fairchild Fairchild D101 D102 D103 D201 D202 BD 1W 1W 1W 2W LF101 L201 C101 C102, C103 C104 C105 C106 C107 C108 C109 C110 C111 C201, C202 C203 C204 C205 C301, C302 Note Part Value CAPACITOR 470nF/ 275V 470nF/ 400WV 223/ 630V 33uF/ 35V 104 1uF/ 35V 101 122 272 333 1000uF/ 35V 330uF/ 16V 2200uF/ 16V 104 332/ 1kV INDUCTOR 30mH DIODE 1N4004 FR157 UF4007 MBRF10100CT MBR3045PT PBS406GU Box Capacitor Electrolytic Film Film Capacitor Ceramic Electrolytic Ceramic Ceramic Film Film Electrolytic Electrolytic Electrolytic Ceramic Ceramic Note 18 FAN7554 Transformer specification Schematic Diagram (Top view) 1 13, 14 Np ; 32turn 3 Ns,12 ; 5turn Nvcc ; 6turn 8, 9 Np ; 32turn Ns,12 ; 5turn 6 Nvcc ; 5turn 7 Ns,5 ; 4turn 10,11,12 Ns,5 ; 4turn Np ; 32turn Winding Specification No. NP NS , 5 NS, 12 NP NVCC Core : Powder 27 pi 16grade 5V : 12T ( 1 φ × 2 ) 12V : 27T ( 1.2 φ × 1 ) Pin(S → F) 1→3 8 → 11 4→9 1→3 7→6 Wire 0.65 φ × 1 0.65 φ × 4 0.65 φ × 4 0.65 φ × 1 0.65 φ × 1 Turns 32 4 5 32 5 19 FAN7554 Mechanical Dimensions Package Dimensions in millimeters 8-SOP Symbol A A1 A2 B C D E e H h L GP q aaa bbb Min 0.10 1.25 0.35 0.19 4.80 3.80 5.79 0.25 0.50 0 - Nom 0.15 1.45 0.37 0.20 4.90 3.90 1.27BSC 5.99 0.70 0.36 BSC - Max 1.75 0.25 1.50 0.51 0.25 5.00 4.00 6.20 0.50 0.90 8 0.25 0.10 20 FAN7554 Mechanical Dimensions (Continued) Package Dimensions in millimeters 8-DIP 21 FAN7554 Ordering Information Product Number FAN7554 FAN7554D Package 8-DIP 8-SOP Operating Temperature -25°C ~ 85°C DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 10/2/03 0.0m 001 Stock#DSxxxxxxxx  2003 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.