FAN7888

FAN7888 — 3 Half-Bridge Gate-Drive IC May 2008 FAN7888 3 Half-Bridge Gate-Drive IC Features Floating Channel for Bootstrap Operation to +200V Typically 350mA/650mA Sourcing/Sinking Current Driving Capability for All Channels 3 Half-Bridge Gate Driver Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15V Matched Propagation Delay Time Maximum 50ns 3.3V and 5V Input Logic Compatible Built-in Shoot-Through Prevention Circuit for All Channels with Typically 270ns Dead Time Built-in Common Mode dv/dt Noise Canceling Circuit Built-in UVLO Functions for All Channels Description The FAN7888 is a monolithic three half-bridge gate-drive IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +200V. Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side drivers under high-dv/dt noise circumstances. An advanced level-shift circuit allows high-side gate driver operation up to VS = -9.8V (typical) for VBS =15V. The UVLO circuits prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source/sink 350mA/650mA, respectively, which is suitable for three-phase half-bridge applications in motor drive systems. Applications 3-Phase Motor Inverter Driver 20-SOIC Ordering Information Part Number FAN7888M FAN7888MX Package 20-SOIC Operating Temperature Range -40°C to +125°C Packing Method Tube Tape & Reel All packages are lead free per JEDEC: J-STD-020B standard. © 2008 Fairchild Semiconductor Corporation FAN7888 • Rev. 1.0.0 www.fairchildsemi.com FAN7888 — 3 Half-Bridge Gate-Drive IC Typical Application Circuit +15V Up to 200V UU 1 HIN1 VB1 20 UL 2 LIN1 HO1 VS1 19 VU 3-Phase BLDC Motor Controller VL 3 HIN2 18 VS1 Q1 Q3 Q5 FAN7888 Q1 Q3 Q5 4 LIN2 LO1 17 WU 5 HIN3 VB2 16 VS1 IU U WL 6 LIN3 HO2 15 3-Phase Inverter VS2 Q4 Q6 Q2 VS3 Q4 Q6 Q2 VS2 7 LO3 VS2 14 IV V W 8 VS3 LO2 13 IW 9 HO3 VB3 VDD 12 GND 11 10 VS3 FAN7888 Rev.00 Figure 1. 3-Phase BLDC Motor Drive Application Internal Block Diagram VB1 UVLO DRIVER PULSE GENERATOR HO1 RR S UHIN HIN1 NOISE CANCELLER Q VS1 VDD_UVLO HIN2 UVLO DRIVER VDD SCHMITT TRIGGER INPUT ULIN HIN3 VDD DELAY LO1 GND LIN1 SHOOT-THOUGH PREVENTION VDD U Phase Driver VB2 LIN2 VHIN VLIN LIN3 V Phase Driver HO2 VS2 LO2 CONTROL LOGIC VDD WHIN WLIN VB3 W Phase Driver HO3 VS3 LO3 FAN7888 Rev.01 Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN7888 • Rev.1.0.0 www.fairchildsemi.com 2 FAN7888 — 3 Half-Bridge Gate-Drive IC Pin Configuration HIN1 1 LIN1 2 HIN2 3 20 VB1 19 HO1 18 VS1 FAN7888 LIN2 4 HIN3 5 LIN3 6 LO3 7 VS3 8 17 LO1 16 VB2 15 HO2 14 VS2 13 LO2 12 VDD 11 GND HO3 9 VB3 10 FAN7888 Rev.00 Figure 3. Pin Configuration (Top View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name HIN1 LIN1 HIN2 LIN2 HIN3 LIN3 LO3 VS3 HO3 VB3 GND VDD LO2 VS2 HO2 VB2 LO1 VS1 HO1 VB1 Description Logic input 1 for high-side gate 1 driver Logic input 1 for low-side gate 1 driver Logic input 2 for high-side gate 2 driver Logic input 2 for low-side gate 2 driver Logic input 3 for high-side gate 3 driver Logic input 3 for low-side gate 3 driver Low-side gate driver 3 output High-side driver 3 floating supply offset voltage High-side driver 3 gate driver output High-side driver 3 floating supply voltage Ground Logic and all low-side gate drivers power supply voltage Low-side gate driver 2 output High-side driver 2 floating supply offset voltage High-side driver 2 gate driver output High-side driver 2 floating supply voltage Low-side gate driver 1 output High-side driver 1 floating supply offset voltage High-side driver 1 gate driver output High-side driver 1 floating supply voltage © 2008 Fairchild Semiconductor Corporation FAN7888 • Rev.1.0.0 www.fairchildsemi.com 3 FAN7888 — 3 Half-Bridge Gate-Drive IC Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol VB VS VHO1,2,3 VDD VLO1,2,3 VIN dVS/dt PD θJA TJ TS Notes: Parameter High-side Floating Supply Voltage of VB1,2,3 High-side Floating Supply Offset Voltage of VS1,2,3 High-side Floating Output Voltage Low-side and Logic-fixed Supply Voltage Low-side Output Voltage Logic Input Voltage (HIN1,2,3 and LIN1,2,3) Allowable Offset Voltage Slew Rate Power Dissipation(1)(2)(3) Thermal Resistance, Junction-to-ambient Junction Temperature Storage Temperature Min. -0.3 VB1,2,3-25 VS1,2,3-0.3 -0.3 -0.3 -0.3 Max. 225.0 VB1,2,3+0.3 VB1,2,3+0.3 25.0 VDD+0.3 VDD+0.3 50 1.8 80 +150 Unit V V V V V V V/ns W °C/W °C °C -55 +150 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages. 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VB1,2,3 VS1,2,3 VDD VHO1,2,3 VLO1,2,3 VIN TA Parameter High-side Floating Supply Voltage High-side Floating Supply Offset Voltage Supply Voltage High-side Output Voltage Low-side Output Voltage Logic Input Voltage (HIN1,2,3 and LIN1,2,3) Ambient Temperature Min. VS1,2,3+10 6-VDD 10 VS1,2,3 GND GND -40 Max. VS1,2,3+20 200 20 VB1,2,3 VDD VDD +125 Unit V V V V V V °C © 2008 Fairchild Semiconductor Corporation FAN7888 • Rev.1.0.0 www.fairchildsemi.com 4 FAN7888 — 3 Half-Bridge Gate-Drive IC Electrical Characteristics VBIAS (VDD, VBS1,2,3) = 15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are referenced to GND and VS1,2,3 and are applicable to the respective outputs LO1,2,3 and HO1,2,3. Symbol IQDD IPDD1,2,3 VDDUV+ VDDUVVDDHYS Characteristics Quiescent VDD Supply Current Operating VDD Supply Current for each Channel VDD Supply Under-Voltage Positive-going Threshold VDD Supply Under-Voltage Negative-going Threshold VDD Supply Under-Voltage Lockout Hysteresis Quiescent VBS Supply Current for each Channel Operating VBS Supply Current for each Channel VBS Supply Under-Voltage Positive-going Threshold VBS Supply Under-Voltage Negative-going Threshold VBS Supply Under-Voltage Lockout Hysteresis Offset Supply Leakage Current High-level Output Voltage, VBIAS-VO Low-level Output Voltage, VO Output HIGH Short-circuit Pulsed Current(4) Current(4) Output LOW Short-circuit Pulsed Condition VLIN1,2,3=0V or 5V fLIN1,2,3=20kHz, rms Value VDD=Sweep, VBS=15V VDD=Sweep, VBS=15V VDD=Sweep, VBS=15V Min. Typ. Max. Unit 160 500 7.2 6.8 8.2 7.8 0.4 350 900 9.0 8.5 µA µA V V V LOW SIDE POWER SUPPLY SECTION BOOTSTRAPPED POWER SUPPLY SECTION IQBS1,2,3 IPBS1,2,3 VBSUV+ VBSUVVBSHYS ILK VOH VOL IO+ IOVS VHIN1,2,3=0V or 5V fHIN1,2,3=20kHz, rms Value VDD=15V, VBS=Sweep VDD=15V, VBS=Sweep VDD=15V, VBS=Sweep VB1,2,3=VS1.2.3=200V IO=20mA IO=20mA VO=0V, VIN=5V with PW