FAN8005D2

www.fairchildsemi.com FAN8005D2 3-CH Motor Driver Features • • • • • • • 3-Channel BTL (Balanced transformer-less) driver Built-in variable regulator with reset (Series-REG) Built-in thermal shutdown circuit Built-in power save circuit Built-in general OP-amp Operating supply voltage: 4.5V ~ 5.5V Corresponds to 3.3V or 5V DSP Description The FAN8005D2 is a monolithic integrated circuit, suitable for a 3-ch motor driver which drives focus actuator, tracking actuator, and sled motor of a CD-media system. 28-SSOPH-300 Typical Applications • Compact disk player • Digital video disk player • Compact disk ROM Ordering Information Device FAN8005D2 Package 28-SSOPH-300 Operating Temp. −35°C ~ +85°C −35°C ~ +85°C FAN8005D2TF 28-SSOPH-300 Rev. 1.0.2 ©2001 Fairchild Semiconductor Corporation 2 REF 28 1 2 3 4 5 6 7 VM12 PS DO2+ DO2− FIN(GND) 8 9 10 11 12 13 DO1+ DO1− 14 SGND 27 26 25 24 23 22 21 20 VCC IN.1 IN.2 OUT1 IN2.1 IN2.2 IN3.1 IN3.2 OUT3 OPOUT OPIN+ OPIN− FIN(GND) OUT2 REGOX FAN8005D2 Pin Assignments FAN8005D2 VM3 19 18 17 16 15 VREGX RESX DO3+ DO3− PGND FAN8005D2 Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name REF IN1.1 IN1.2 OUT1 IN2.1 IN2.2 OUT2 SGND VM12 PS DO2+ DO2− DO1+ DO1− PGND DO3− DO3+ RESX VREGX VM3 REGOX OPIN− OPIN+ OPOUT OUT3 IN3.2 IN3.1 VCC I/O I I I O I I O I O O O O O O I O I I I O O I I Bias voltage input Op-amp CH1 input (+) Op-amp CH1 input (−) Op-amp CH1 output Op-amp CH2 input (+) Op-amp CH2 input (−) Op-amp CH2 output Signal ground BTL CH1, 2 supply voltage Power save Drive2 output (+) Drive2 output (−) Drive1 output (+) Drive1 output (−) Power ground Drive3 output (−) Drive3 output (+) Regulator reset Op-amp output BTL CH3 supply voltage Op-amp input(+) Op-amp input (−) Op-amp input (+) Op-amp output Op-amp CH3 output Op-amp CH3 input (−) Op-amp CH3 input (+) Supply voltage Pin Function Descrition 3 FAN8005D2 Internal Block Diagram REGOX OPOUT VREGX DO3(+) OPIN− PGND 15 OUT3 VCC RESX IN3.1 IN3.2 VM3 FIN (GND) DO3(−) 16 10k OPIN+ 23 28 27 26 25 24 22 21 20 19 18 17 + −− +− +− + + − 10k + + − REGULATOR + VM3 TSD 20k 10k 10k − 10k + LEVEL SHIFT − 10k 10k − -+ −+ +− 10k 10k − + LEVEL SHIFT − 10k − 10k + VM12 + 10k − ++ − ++ − 10k 50k 50k VM12 + 10k + − 10k + − 10k + 1 REF 2 IN1.1 3 IN1.2 4 OUT1 5 IN2.1 6 IN2.2 7 OUT2 (GND) FIN 8 SGND 9 VM12 10 PS 11 DO2(+) 12 DO2(−) 13 DO1(+) 14 DO1(−) 4 10k FAN8005D2 Equivalent Circuits Error amp input Power save input 2 5 27 50Ω 50Ω 3 6 26 10 50Ω 50kΩ 50kΩ Error amp output Signal reference input 4 50Ω 6 25 1 50Ω 0.2kΩ Power output Regulator reset 11 12 13 14 16 17 30kΩ 18 50Ω 50kΩ 5 FAN8005D2 Equivalent Circuits (Continued) Regulator Regulator output 50Ω 21 19 50Ω General op amp input General op amp output 24 22 50Ω 50Ω 23 6 FAN8005D2 Absolute Maximum Ratings ( Ta=25°C) Parameter Maximum supply voltage Power dissipation Operating temperature range Storage temperature range Symbol VCCmax PD TOPR TSTG Value 7 @1.4 −35 ~ +85 −55 ~ +150 Unit V W °C °C Notes: 1. When mounted on a 76.2mm × 114mm × 1.57mm PCB (Phenolic resin material). 2. Power dissipation reduces 11.2mW / °C for using above Ta = 25°C 3. Do not exceed PD and SOA (Safe operating area). PD (Temporary) Pd (mW) 2,000 1,200 SOA 400 0 0 25 50 75 85 100 125 150 175 Ambient temperature, Ta [°C] Recommended Operating Conditions ( Ta=25°C) Parameter Supply voltage Symbol VCC Min. 4.5 Typ. Max. 5.5 Unit V 7 FAN8005D2 Electrical Characteristics (Unless otherwise specified, Ta=25°C, VCC=VM12=VM3=5V) Parameter Quiescent current Power save on current Power save on voltage Power save off voltage BTL DRIVE CIRCUIT Output offset voltage 1 Output offset voltage 2 Maximum output voltage 1 Maximum output voltage 2 Closed loop voltage gain 1 Closed loop voltage gain 2 Ripple rejection ratio Slew rate ERROR AMP CIRCUIT Input offset voltage Input bias current High level output voltage Low level output voltage Output sink current Output source current Slew rate GENERAL OP AMP CIRCUIT Input offset voltage Input bias current High level output voltage Low level output voltage Output sink current Output source current Open loop voltage gain Ripple rejection ratio Slew rate Common mode rejection ratio Regulator output voltage Load regulation Line regulation VARIABLE REGULATOR CIRCUIT VREG ∆VR1 ∆VCC IL=100mA IL=0→200mA IL=200mA, VCC=5→8V 3.0 −40 −20 4.5 10 30 V mV mV VOFOP IBOP VOHOP VOLOP ISINK ISOURCE GVO RROP SROP CMRR VCC=5V, RL=1kΩ VCC=5V, RL =1kΩ VCC=5V, RL= 50Ω VCC=5V, RL=50Ω VIN=−75dB, f=1kHz VIN=−20dB, f =120Hz f=120kHz, 2Vp-p VIN=−20dB, f=1kHz −20 3 2 2 4 1 5 5 75 65 1 80 +20 300 1.3 mV nA V V mA mA dB dB V/µs dB VOFOP IBOP VOHOP VOLOP ISINK ISOURCE SROP VCC=5V, RL=10kΩ VCC=5V, RL =10kΩ VCC=5V, RL= 1kΩ VCC=5V, RL=1kΩ f=120kHz, 2Vp-p −20 4.5 1 1 4.8 0.2 3 3 1 +20 300 0.5 mV nA V V mA mA V/µs VOO1 VOO2 VOM1 VOM2 GVC1 GVC2 RR SR VIN=2.5V (CH1,2) VIN=2.5V (CH3) VCC=5V, RL=8Ω (CH1, 2) VCC=5V, RL=24Ω (CH3) f=1kHz, VIN=0.1VRMS (CH1, 2) f=1kHz, VIN=0.1VRMS (CH3) VIN=0.1VRMS, f=120Hz VO=2Vp-p, f=120kHz −50 −60 2.7 3 10.5 16 3.5 3.8 12 18 60 1 +50 +60 13.5 20 mV mV V V dB dB dB V/µs Symbol ICC IPS VPSon VPSoff VIN=0V PS pin=GND Conditions Min. 2 Typ. 13 Max. 1 0.5 Unit mA mA V V 8 FAN8005D2 Application Information 1. Reference Input & Power Save Function Pin 1 (REF) is a reference input pin. • Reference input The applied voltage at the reference input pin must be between 1.5V and 3.5V, when VCC=5V. • Power save input The following input conditions must be satisfied for the power save function. Power save on voltage Power save off voltage Below 0.5V Above 2V Power save function operation Normal operation 2. Protection Function Thermal shutdown (TSD) • If the chip temperature rises above 175°C, the thermal shutdown (TSD) circuit is activated and the output circuit is in the mute state, that is off state. The TSD circuit has a temperature hysteresis of 25°C. 3. Regulator & Reset Function The regulator configuration with the external components is illustrated in figure 1. • The external circuit is composed of the KSB772 PNP transistor and a capacitor about 33µF, and two feedback resistors R1, R2. The capacitor operates both as a ripple eliminator and as a compensator of the feedback loop. • The output voltage (REG OUT) is R1 Vout =  1 + ------- × 2.5  R2 • When the voltage of pin18 (Vreset) is 0V, the regulator reset function is activated, and the output voltage (REG OUT) becomes 0V. Otherwise, if the voltage of pin 18 is 5V, the regulator operates properly. VCC KSB772 REG OUT + Vreset R1 R2 21 19 18 + − FAN8005D2 2.5V Figure 1. Regulator circuit 9 FAN8005D2 4. Focus / Tracking Actuator Sled Motor Drive Part R2 R1 OPin+ OPinOPout 2 3 4 5 6 7 Vref 27 26 25 1 + − Vin R1 Vp R2 R1 − + R2 R2 + − R2 M DON 12 14 16 DOP 11 13 17 VM12 Dp 60k + 62k Qp − Vp • The voltage, Vref is the reference voltage given by the external bias voltage of the pin 1. • The input signal (Vin) through pins 3,6 and 26 are amplified one time and then fed to the output stage. (assume that input opamp was used as a buffer) • The total closed loop voltage gain is as follows (assume that R2=2R1) Vin = Vref + ∆V DOP = Vp + 2 ∆V DON = Vp – 2 ∆V Vout = DOP – DON = 4 ∆V Vout Gain = 20 log ------------ = 20 log 4 = 12dB ∆V • To change the total closed loop voltage gain, Use the input opamp as an amplifier • The output stage is the balanced transformerless (BTL) driver. • The bias voltage Vp is expressed as ; 62k Vp = ( PVCC1 – VDp – VcesatQp ) × ------------------------- + VcesatQp 60k + 62k PVCC1 – VDp + VcesatQp = -------------------------------------------------------------------------- + VcesatQp 1.97 ---------- (1) 10 FAN8005D2 Typical Performance Characteristics < VCC & ICC > < VCC & VOM > ICC (mA) 10 9 8 7 6 5 4 3 2 1 0 3 6 VOM (V) 14 12 10 8 6 4 CH1 CH2 CH3 Ta=25℃ VCC=VM12=VM3 9 12 15 2 0 2 5 8 Ta= Ta= 25 ℃ VCC= VM 12= VM 3 ( CH RL 1= 8Ω (CH1, 2 ) ( CH RL 2= 24 Ω (CH3) 11 14 VCC (V) VCC (V) VOUT (V) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 100 200 < IOM & VOUT > GVC (dB) 20 18 < VCC & GVC > CH1 Upp. CH1 Low CH2 Upp. CH2 Low CH3 Upp. CH3 Low Ta= 25 ℃ VCC= VM 1 2= VM 3 16 14 12 10 8 6 4 2 0 300 400 500 600 700 3 5 7 9 11 13 15 17 19 21 CH1 CH2 CH3 Ta= 25℃ VCC= VM 1 2= VM 3 ( CH RL 1= 8Ω (CH1, 2 ) ( CH RL 2= 24 Ω (CH3) IOM (mA) VCC (V) VOUT (V) 4 < VCC & VOUT (LINE REGULATION) > VOUT (V) 3.40 3.35 < IO & VOUT (LOAD REGULATION) > 3 3.30 3.25 2 3.20 3.15 1 Ta= 25℃ 0 4 6 8 10 12 14 16 18 3.10 3.05 3.00 0 200 400 600 800 1000 Ta= 25℃ VCC= 5V VCC (V) IO (mA) 11 FAN8005D2 Typical Performance Characteristics (Continued) < VCC & Isource (ERROR OP-AMP) > < VCC & Isink (ERROR OP-AMP) > CH1 CH2 CH3 Isource (mA) 5 Isink (mA) 16 14 12 10 4 3 8 6 2 1 CH1 CH2 CH3 4 Ta= 25℃ RL= 1K Ω 2 0 Ta= 25℃ RL= 1 KΩ 3 6 9 12 15 0 3 6 9 12 15 VCC (V) VCC (V) Isource (mA) 30 < VCC & Isource (GENERAL OP-AMP) > Isink (mA) 120 100 80 60 < VCC & Isink (GENERAL OP-AMP) > 25 20 15 10 Ta= 25℃ RL= 50Ω 40 20 0 3 6 9 12 15 3 6 9 12 15 5 Ta= 25℃ RL= 50Ω 0 VCC (V) VCC (V) GVC (dB) 20 18 16 14 12 10 8 6 4 2 0 - 40 - 20 0 < TEMP & GVC > Δ VCC (mV) 20 TEMP & LINE REGULATION 16 12 8 CH1 CH2 CH3 VCC= VM 1 2= VM 3= 4.5V RL 1= 8 Ω (CH1, 2) ( CH RL 2= 24 Ω (CH3) ( CH 4 VCC= 6V →9V IL= 200mA 0 20 40 60 80 100 - 40 - 20 0 20 40 60 80 100 TEMP (℃) TEMP (℃) 12 FAN8005D2 Application Circuits 1 (Differential PWM control mode) BIAS VOLTAGE SERVO AMP SLED PWM1 PWM2 FOCUS TRACKING PWM1 PWM2 PWM1 PWM2 BIAS 4 OUT1 OUT3 25 3 IN1.2 IN3.2 26 BIAS 2 IN1.1 IN3.1 27 1 REF VCC 28 VCC BIAS 5 IN2.1 OPOUT 24 OPIN+ 23 OPIN− 22 6 IN2.2 OUT2 7 FAN8005D2 VARIABLE REGULATOR 8 SGND REGOX 21 VM3 20 5V 10 PS 11 DO2+ TRACKING ACTUATOR 12 DO2− 13 DO1+ FOCUS ACTUATOR 14 DO1− VREGX 19 VCC REGULATOR RESET 9 5V PS VM12 RESX 18 DO3+ 17 SLED MOTOR DO3- 16 PGND 15 13 FAN8005D2 Application Circuits 2 (Voltage control mode) BIAS VOLTAGE 1 REF SERVO AMP SLED FOCUS TRACKING 2 IN1.1 3 IN1.2 4 OUT1 5 IN2.1 6 IN2.2 7 OUT2 VCC 28 IN3.1 27 IN3.2 26 OUT3 25 OPOUT 24 OPIN+ 23 OPIN- 22 VCC FAN8005D2 33uF 8 SGND 9 VM12 5V PS 10 PS 11 DO2+ 12 DO213 DO1+ FOCUS ACTUATOR 14 DO1VREGX 19 RESX 18 DO3+ 17 SLED MOTOR DO3- 16 PGND 15 VCC REGULATOR RESET REGOX 21 + VARIABLE REGULATOR VM3 20 5V TRACKING ACTUATOR 14 FAN8005D2 15 FAN8005D2 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the www.fairchildsemi.com 3/17/01 0.0m 001 Stock#DSxxxxxxxx  2001 Fairchild Semiconductor Corporation user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.