FAN8026G3

www.fairchildsemi.com FAN8026G3 5-CH Motor Driver Features • • • • • 5-CH Balanced transformerless (BTL) driver Operating supply voltage : 4.5 V ~ 13.2V Built-in thermal shut down circuit (TSD) Built-in channel mute circuit Built-in 1-OP AMP Description The FAN8026G3 is a monolithic integrated circuit suitable for a 5-CH motor driver which drives a tracking actuator, a focus actuator, a sled motor, a spindle motor, and a tray motor of the CDP/CAR-CD/DVDP systems. 28-SSOPH-375SG3 Typical application • • • • Compact disk player Video compact disk player Car compact disk player Digital video disk player Ordering information Device FAN8026G3 FAN8026G3Xnote1 FAN8026G3X_NL Notes: 1. X : Tape&Reel 2. NL : Lead free Package Operating temp 28-SSOPH-375-SG2 -35°C ~ +85°C 28-SSOPH-375-SG2 -35°C ~ +85°C 28-SSOPH-375-SG2 -35°C ~ +85°C FAN8026G3_NLnote2 28-SSOPH-375-SG2 -35°C ~ +85°C Rev. 1.0.0 ©2004 Fairchild Semiconductor Corporation FAN8026G3 Pin Assignments DO5- DO5+ DO4- DO4+ VM2 MUTE REF IN3 OUT3 SVCC DO1+ DO1- DO2+ DO2- 28 27 26 25 24 23 22 FIN 21 20 19 18 17 16 15 FAN8026G3 1 OPIN+ 2 OPIN- 3 OPOUT 4 IN5 5 OUT5 6 IN4 7 OUT4 FIN 8 GND 9 IN2 10 OUT2 11 IN1 12 VM1 13 DO3+ 14 DO3- 2 FAN8026G3 Pin Definitions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name OPIN+ OPINOPOUT IN5 OUT5 IN4 OUT4 GND IN2 OUT2 IN1 VM1 DO3+ DO3DO2DO2+ DO1DO1+ SVCC OUT3 IN3 REF MUTE VM2 DO4+ DO4DO5+ DO5I/O I I O I O I O I O I O O O O O O O I I I O O O O OP-AMP Input(+) OP-AMP Input(-) OP-AMP Output CH5 Op-amp Input(-) CH5 Op-amp Output CH4 Op-amp Input(-) CH4 Op-amp Output Ground CH2 Op-amp Input(-) CH2 Op-amp Output CH1 Input Power Supply Voltage(For CH2,CH3) CH3 Drive Output(+) CH3 Drive Output(-) CH2 Drive Output(-) CH2 Drive Output(+) CH1 Drive Output(-) CH1 Drive Output(+) Power Supply Voltage(For Signal,CH1) CH3 Op-amp Output CH3 Op-amp Input(-) CH1,2,3,4,5 Input Reference MUTE(CH2,3,4,5) Power Supply Voltage(For CH4,CH5,Normal Op-amp) CH4 Drive Output(+) CH4 Drive Output(-) CH5 Drive Output(+) CH5 Drive Output(-) Pin Function Description 3 FAN8026G3 Internal Block Diagram VM2 OPIN+ 1 OPIN2 3 OPOUT SVCC OUT5 IN5 5 10K VM2 4 10K Level Shift SVCC VM2 27 DO5+ 28 DO5- 24 VM2 OUT4 IN4 7 6 10K 10K 25 DO4+ Level Shift SGND 8 26 DO4- OUT3 20 IN3 21 10K FIN OUT2 IN2 10 9 10K FIN TSD SVCC VM1 10K 13 DO3+ SVCC VM1 10K Level Shift Level Shift 14 DO3- 12 VM1 16 DO2+ 15 DO2MUTE 23 CH2,3,4,5 SVCC SVCC 19 SVCC REF IN1 22 11 10K 18 DO1+ Level Shift 17 DO1- 4 FAN8026G3 Equivalent Circuits BTL CH1 Input SVCC BTL CH2,3,4,5 Op-amp Input SVCC SVCC SVCC 4 9 6 21 1K 1K 1K 11 100 BTL CH2,3,4,5 Op-amp Output BTL CH1 Driver Output SVCC SVCC SVCC SVCC 5 7 10 20 20K 17 18 30K BTL CH2,3 Driver Output SVCC VM1 BTL CH4,5 Driver Output SVCC VM2 20K 13 14 15 16 20K 25 26 27 28 30K 30K 5 FAN8026G3 Equivalent Circuits (Continued) Mute REF SVCC SVCC SVCC 50 23 40K 22 1K 40K 40K 40K Op-amp Input Op-amp Output VM2 VM2 VM2 VM2 VM2 1 1K 1K 2 3 6 FAN8026G3 Absolute Maximum Ratings ( Ta=25°C) Parameter Maximum supply voltage Power dissipation Operating temperature Storge temperature Symbol SVCC VM1 VM2 PD TOPR TSTG 2.5 Value 15 15 15 note1,2,3 Unit V V V W °C °C −35 ~ +85 −55 ~ +150 Notes: 1. When mounted on glass epoxy PCB (76 × 114 × 1.6mm) 2. Power dissipation is reduced at the rate of -20mW/°C for TA≥25°C. 3. Do not exceed Pd and SOA(Safe Operating Area). Pd (mW) 3,000 2,000 SOA 0 25 50 75 100 125 150 175 1,000 0 Ambient temperature, Ta [°C] Recommended Operating Conditions ( Ta=25°C) Parameter Supply voltage1 Supply voltage2 Supply voltage3 Symbol SVCC VM1 VM2 Min. 4.5 4.5 4.5 Typ. Max. 13.2 SVCC SVCC Unit V V V 7 FAN8026G3 Electrical Characteristics (Unless otherwise specified, Ta=25°C, SVCC=8V, VM1=5V, VM2=5V, Vref=1.65V) Parameter Quiescent current 1* MUTE on voltage MUTE off voltage Reference MUTE on voltage Reference MUTE off voltage REF Input voltage range Output offset voltage1 Maximum output voltage1 Close-loop voltage gain1 CH2,3 BTL DRIVER CIRCUIT (RL=8Ω) Output offset voltage2,3,4,5 Maximum output voltage2,3,4,5 Close-loop voltage gain2,3,5 Close-loop voltage gain4 INPUT OP-AMP CIRCUIT Input offset voltage1 Input bias current1 High level output voltage1 Low level output voltage1 Output sink current1 Output source current1 Common mode input range1*note1 Open loop voltage gain1* Ripple rejection ratio1* Slew rate1* note1 note1 note1 note1 note1 Symbol ICC1 ICC2 Vmon Vmoff Vrmon Vrmoff Vrefin1 VOF1 Vom1 Gvf1 VOF2,3,4,5 Vom2,3,4,5 Gvf2,3,5 Gvf4 VOF1 IB1 VOH1 VOL1 ISINK1 ISOU1 Vicm1 GVO1 RR1 SR1 Conditions MUTE Off MUTE On Pin23=Variation Pin23=Variation Pin22=Variation Pin22=Variation VIN=1.65V VIN=100mVpp, f=1kHz VIN=1.65V VIN=100mVpp, f=1kHz VIN=100mVpp, f=1kHz SVCC=8V f=1kHz, VIN= -75dB f=120Hz, VIN= -20dB f=120Hz, 2Vp-p Min. 2.0 1.0 1.0 -50 6 10 -50 3.6 10.5 11.5 -10 7 1 0.5 -0.3 - Typ. 21 12 6.5 12 4.0 12.5 13.5 75 65 1 Max. 0.5 0.4 3.3 +50 14 +50 14.5 15.5 +10 300 0.5 7.0 - Unit mA mA V V V V V mV V dB mV V dB dB mV nA V V mA mA V dB dB V/us Quiescent current 2* CH1 LOADING DRIVER CIRCUIT (RL=12Ω) Note: 1.Guaranteed field. ( No EDS/ Final test . ) 8 FAN8026G3 Electrical characteristics (Countinued) (Unless otherwise specified, Ta=25°C, SVCC=8V, VM1=5V, VM2=5V, Vref=1.65V) Parameter NORMAL OP-AMP CIRCUIT Input offset voltage Input bias current High level output voltage Low level output voltage Output sink current Output source current Common mode input range1* Open loop voltage gain*note1 Ripple rejection ratio*note1 Slew rate *note1 note1 Symbol VOF2 IB2 VOH2 VOL2 ISINK2 ISOU2 Vicm1 GVO2 RR2 SR2 Conditions VM2=5V f=1kHz, VIN= -75dB f=120Hz, VIN= -20dB f=120Hz, 2Vp-p Min. -10 4.5 1 0.5 -0.3 - Typ. 75 65 1 Max. +10 300 0.5 4.0 - Unit mV nA V V mA mA V dB dB V/us Note: 1.Guaranteed field. ( No EDS/ Final test . ) 9 FAN8026G3 Application information 1. MUTE Function When the mute pin is low(GND), the TR Q1 is turned on and the bias circuit is enabled. On the other hand, when the mute pin is high , the TR Q1 is turned off and the bias circuit is disabled. It will make all the circuit blocks except CH1 off, so low power quiescent state can be established. • Truth table is as follows Pin 23 High Low FAN8026 Mute-On Mute-Off 23 Bias Current CH2,3,4,5 Q1 2. TSD Function • When the chip temperature reaches to 175°C by abnormal condition, the TSD circuit is activated • This makes the bias current of the output drivers shut down, and all the output drivers are on cut-off state. Therefore the chip temperature begins to decrease. • When the chip temperature falls to 155°C, the TSD circuit is deactivated and the output drivers start to operate normally. SVCC IREF R1 Q0 R2 Hysteresis Ihys R3 Output driver Bias 3. Notice • If REF(pin23) is lower than 0.7V, BTL output is off. • Under voltage protecton function. ( If SVcc is lower than 3.8V, Chip is disable. Hysterisis is 0.2V) • Mute on BTL output voltage is as followed: - Mute on BTL output(CH2,3,4,5) = VM / 2 - Mute on BTL output CH1 = ((PVcc2-0.6) / 2 • Each output to output and output to GND short should be kept away. 10 FAN8026G3 Typical Application Circuit Spindl e Motor 1 5 DO2- DO3- 1 4 M 1 6 1 7 DO2+ DO1DO3+ VM1 1 3 1 2 M S led Motor Loadin g Motor M 1 8 DO1+ IN1 1 1 5V 8V 2 0 OUT3 FAN8026G3 1 9 SVCC OUT2 1 0 IN2 9 2 1 IN3 GND 8 FIN 2 2 REF OUT4 IN4 2 3 2 4 MUTE VM2 OUT5 5V Focus Actuat or 2 5 DO4+ IN5 2 6 DO4- OPOUT Trackin g Actuato r 2 7 DO5+ DO5- OPIN- 2 8 OPIN+ VREF FIN 7 6 5 4 3 2 1 7 TRACKING SERVO LOADING FOCUS MUTE SLED SPINDLE 11 FAN8026G3 Test Circuits SW3 SW5 SW4 A V A A A A A V 28 DO527 DO5+ 26 DO4- V 25 DO4+ 24 VM2 23 MUTE 22 REF FIN 21 IN3 20 OUT3 19 SVCC 18 DO1+ 17 DO116 DO2+ DO3+ 13 SW2 V 15 DO2V DO314 11 IN1 A VM1 12 SW1 A FAN8026G3 OPIN+ OPIN- OPOUT OUT5 OUT4 IN4 1 IN+ 2 IN- 3 OUT 4 5 6 7 FIN 8 IN2 9 10 OP-AMP A A A A A IN+ SW6 v OP-AMP INSW7 OUT SW8 SW9 12 OUT4 A IN5 GND FAN8026G3 Package Dimension 28-SSOPH-375-SG2 13 FAN8026G3 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 3/17/04 0.0m 001 Stock#DSxxxxxxxx  2004 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.