FDG901D

FDG901D April 2002 FDG901D Slew Rate Control Driver IC for P-Channel MOSFETs General Description The FDG901D is specifically designed to control the turn on of a P-Channel MOSFET in order to limit the inrush current in battery switching applications with high capacitance loads. During turn-on the FDG901D drives the MOSFET’s gate low with a regulated current source, thereby controlling the MOSFET’s turn on. For turn-off, the IC pulls the MOSFET gate up quickly, for efficient turn off. Features • Three Programmable slew rates • Reduces inrush current • Minimizes EMI • Normal turn-off speed • Low-Power CMOS operates over wide voltage range Applications • Power management • Battery Load switch • Compact industry standard SC70-5 surface mount package GATE 1 pin 1 5 GND SLEW 2 VDD 3 4 LOGIC IN Absolute Maximum Ratings Symbol VDD VIN PD TJ, TSTG Supply Voltage TA=25oC unless otherwise noted Parameter DC Input Voltage (Logic Inputs) Power Dissipation for Single Operation @ 85°C Operating and Storage Junction Temperature Range Ratings -0.5 to 10 -0.7 to 6 150 -65 to +150 Units V V mW °C Recommended Operating Range VDD TJ Supply Voltage Operating Temperature 2.7 to 6.0 -40 to +125 V °C Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 425 °C/W Package Marking and Ordering Information Device Marking 91 Device FDG901D Reel Size 7’’ Tape width 8mm Quantity 3000 units 2002 Fairchild Semiconductor Corporation FDG901D rev. E (W) FDG901D Electrical Characteristics Symbol Logic Levels VIH VIL Logic HIGH Input Voltage Logic LOW Input Voltage TA = 25°C unless otherwise noted Parameter Test Conditions Min 75% of VDD Typ Max Units VDD = 2.70V to 6.0 V VDD = 2.70V to 6.0 V V 25% of VDD V OFF Characteristics BVIN BVSLEW BVDG IRIN IRSLEW IRDG Logic Input Breakdown Voltage Slew Input Breakdown Voltage Supply Input Breakdown Voltage LOGIC Input Leakage Current SLEW Input Leakage Current Supply Input Leakage Current Gate Current IIN = 10µA, VSLEW = 0 V ISLEW = 10µA, VIN = 0 V IDG = 10µA, VIN = 0 V, VSLEW = 0 V VIN = 8 V, VSLEW = 0 V VSLEW = 8 V, VIN = 0 V VDG = 8 V, VIN = 0 V, VSLEW = 0 V SLEW = OPEN SLEW = GND SLEW = VDD 90 1 10 9 9 9 100 100 100 120 10 50 V V V nA nA nA µA µA nA ON Characteristics IG VIN = 6V VGATE = 2V Switching Characteristics tdon tdon tdon trise trise trise dv/dt dv/dt dv/dt Output Turn-On Delay Time Slew Pin = OPEN Output Turn-On Delay Time Slew Pin = GROUND Output Turn-On Delay Time Slew Pin = VDD Output Rise Time Slew Pin = OPEN Output Rise Time Slew Pin = GROUND Output Rise Time Slew Pin = VDD Output Slew Rate Slew Pin = OPEN Output Slew Rate Slew Pin = GROUND Output Slew Rate Slew Pin = VDD VSupply = 5.5 V, VDD = 5.5 V, Logic IN = 5.5 V, CLOAD = 510 pF, Test Circuit 8.3 0.6 2.2 VSupply = 5.5 V, VDD = 5.5 V, Logic IN = 5.5 V, CLOAD = 510 pF, Test Circuit 28 1.8 11 162 VSupply = 5.5 V, VDD = 5.5 V, Logic IN = 5.5 V, CLOAD = 510 pF, Test Circuit 2.6 0.3 µs ms ms µs ms ms V/ms V/ms V/ms Notes: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. VDD VSUPPLY 10% 3 SLEW 2 1 LOGIC IN 4 5 CLoad LOGIC IN 90% OUTPUT (Inverted) 10% tdon trise Test Circuit Switching Waveforms FDG901D rev. D (W) FDG901D Typical Characteristics 100 95 90 Slew = Open Vdd=Vin=6V 2.0 Slew = Gnd Vdd=Vin=6V 1.5 Gate Current, (µA) 85 80 75 70 65 60 -50 0 50 100 o Gate Current (µA) 150 1.0 0.5 0.0 -50 0 50 100 150 Temperature, ( C) Temperature, (oC) Figure 1. GATE Output current vs. Temperature. SLEW = OPEN 14 100 Figure 2. GATE Output current vs. Temperature. SLEW = Ground 12 Output Risetime, microseconds (µsec) Slew = Vdd Vdd=Vin=6V Slew = Open Vdd=Vin=5.5V Gate Current, (nA) 10 10 8 1 6 4 -50 0 50 100 o 0.1 150 1 10 100 1000 Temperature, ( C) Load Capacitance, picoFarad (pF) Figure 3. GATE Output current vs. Temperature. SLEW = VDD 10000 Slew = Gnd Vdd=Vin=5.5V Figure 4. trise vs. Load Capacitance. SLEW = OPEN 100 Slew = Vdd Vdd=Vin=5.5V Output Risetime, microseconds (µs) 1000 Output Risetime, milliseconds (ms) 10 100 1000 10 100 1 10 1 1 0.1 1 10 100 1000 Load Capacitance, picoFarad (pF) Load Capacitance, picoFarad (pF) Figure 5. trise vs. Load Capacitance. SLEW = GROUND Figure 6. trise vs. Load Capacitance. SLEW = VDD FDG901D rev. D (W) I Source Drain Gate Load VDD Logic Signal Slew Rate Control 4 2 5 Ig 3 1 Application Circuit Typical Application Battery powered systems make extensive usage of load switching, turning the power to subsystems off, in order to extend battery life. Power MOSFETs are used to accomplish this task. In PDA’s and Cell phones, these MOSFETs are usually low threshold P-Channels. Since the loads typically include bypass capacitor components (high capacitive component), a high inrush current can occur when the load is switched on. This inrush current can cause transients on the main power supply disturbing circuitry supplied by it. The simplest method of limiting the inrush current is to control the slew rate of the MOSFET switch. This can be done with external R/C circuits, but this approach can occupy significant PCB area, and involves other compromises in performance. The slew rate control driver IC FDG901D is specifically designed to interface low voltage digital circuitry with power MOSFETs and reduce the rapid inrush current in load switch applications. The IC limits inrush current by controlling the current, which drives the gate of the P-Channel MOSFET switch. The control input is a CMOS compatible input with a minimum high input voltage of 2.55V with a power rail voltage of 6V. Therefore, it is compatible with any CMOS logic voltages between 2.55V and 5V and under these conditions there is no additional configuration required. FDG901D rev. D (W) The Slew Rate Control Driver (FDG901D) is designed to give a programmed choice of one of three steady dv/dt states on the output during turn-on. To change the dv/dt value, the user needs to use the Slew Rate Control Pin (Pin 2). To utilize the smallest current setting (≈10 nA) from the IC, a voltage equal to Vdd must be applied to the Slew Rate Control Pin 2. To use the next higher current setting (≈1 µA) a voltage equal to Ground must be applied to Pin 2. To achieve the highest current setting (≈ 80 µA) or obtain a faster switching speed, the Slew Rate Pin2 must be open (floating). A higher value of capacitance will result in a slower switching rate. To determine the switching times of each setting use the simple equation: t= Qg IG where Qg is the Gate charge in nC for a given MOSFET and IG is the gate current controlled by the slew rate pin. Below is a captured image from an oscilloscope depicting the device response. The FDG901D was connected to control an FDG258P P-Channel DMOS. The Slew Rate control pin was set to open (floating state). Test Conditions: VDD = 5.5V VIN = 5.5V RLOAD = 1.5Ω VIN Vgate (inverted) VRLoad Circuit waveforms for an FDG901D controlling a P-Channel FDG258P MOSFET. FDG901D rev. D (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. H5