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FDJ129

FDJ129

  • 厂商:

    FAIRCHILD(仙童半导体)

  • 封装:

  • 描述:

    FDJ129 - P-Channel -2.5 Vgs Specified PowerTrench MOSFET - Fairchild Semiconductor

  • 数据手册
  • 价格&库存
FDJ129 数据手册
FDJ129P July 2004 FDJ129P P-Channel -2.5 Vgs Specified PowerTrench MOSFET General Description This P-Channel -2.5V specified MOSFET uses Fairchild’s advanced low voltage PowerTrench process. It has been optimized for battery power management applications. Features • –4.2 A, –20 V. RDS(ON) = 70 mΩ @ VGS = –4.5 V RDS(ON) = 120 mΩ @ VGS = –2.5 V • Low gate charge • High performance trench technology for extremely low RDS(ON) • Compact industry standard SC75-6 surface mount package Applications • Battery management • Load switch S S G Bottom Drain 4 5 3 2 1 SC75-6 FLMP S S S 6 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed TA=25oC unless otherwise noted Parameter Ratings –20 ± 12 (Note 1a) Units V V A W °C –4.2 –16 1.6 –55 to +150 Power Dissipation for Single Operation (Note 1a) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 77 °C/W Package Marking and Ordering Information Device Marking .A Device FDJ129P Reel Size 7’’ Tape width 8mm Quantity 3000 units 2004 Fairchild Semiconductor Corporation FDJ129P Rev F1 W) FDJ129P Electrical Characteristics Symbol BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR VGS(th) ∆VGS(th) ∆TJ RDS(on) ID(on) gFS TA = 25°C unless otherwise noted Parameter Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse (Note 2) Test Conditions VGS = 0 V, ID = –250 µA Min –20 Typ Max Units V Off Characteristics ID = –250 µA,Referenced to 25°C VDS = –16 V, VGS = 0 V VGS = 12 V, VDS = 0 V VGS = –12 V, VDS = 0 V ID = –250 µA –0.6 –1.1 3 54 91 72 –8 11 70 120 100 –18 –1 100 –100 mV/°C µA nA nA On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance On–State Drain Current Forward Transconductance VDS = VGS, –1.5 V mV/°C mΩ A S ID = –250 µA,Referenced to 25°C VGS = –4.5 V, ID = –4.2 A ID = –3.3 A VGS = –2.5 V, VGS = –4.5 V, ID = –4.2,TJ=125°C VGS = –4.5 V, VDS = –5 V VDS = –5 V, ID = –4.2 A Dynamic Characteristics Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd VSD trr Qrr Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) VDS = –10 V, V GS = 0 V, f = 1.0 MHz 585 124 61 pF pF pF Switching Characteristics Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDD = –10 V, ID = –1 A, VGS = –4.5 V, RGEN = 6 Ω 10 9 17 10 20 18 30 20 6 ns ns ns ns nC nC nC VDS = –10 V, ID = –4.2 A, VGS = –4.5 V 4 1.1 1.2 Drain–Source Diode Characteristics and Maximum Ratings Drain–Source Diode Forwar Voltage Diode Reverse Recovery Time Diode Reverse Recovery Charge VGS = 0 V, IS = –1.5 A (Note 2) –0.7 16 13 –1.2 V nS nC IF = –4.2 A, diF/dt = 100 A/µs Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 77°C/W when mounted on a 1in2 pad of 2 oz copper. b) 110°C/W when mounted on a minimum pad of 2 oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDJ129P Rev F1 (W) FDJ129P Typical Characteristics 16 -3.0V 1.8 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS=-4.5V -3.5V VGS=-2.5V -ID, DRAIN CURRENT (A) 1.6 12 -2.5V 8 1.4 -3.0V -3.5V -4.0V -4.5V 1.2 4 -2.0V 1 0 0 1 2 3 4 -VDS, DRAIN TO SOURCE VOLTAGE (V) 0.8 0 4 8 -ID, DRAIN CURRENT (A) 12 16 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.22 RDS(ON), ON-RESISTANCE (OHM) 1.4 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.3 1.2 1.1 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) ID = -4.2A VGS = -4.5V ID = -2.1A 0.18 0.14 TA = 125 C 0.1 o o TA = 25 C 0.06 0.02 1 2 3 4 5 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation withTemperature. 12 VDS = -5V -ID, DRAIN CURRENT (A) 9 25 C 125 C 6 o o Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 -IS, REVERSE DRAIN CURRENT (A) TA = -55 C o VGS = 0V 10 1 0.1 0.01 0.001 TA = 125 C 25 C -55 C o o o 3 0 0.5 1 1.5 2 2.5 3 -VGS, GATE TO SOURCE VOLTAGE (V) 0.0001 0 0.2 0.4 0.6 0.8 1 1.2 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDJ129P Rev F1 (W) FDJ129P Typical Characteristics 5 -VGS, GATE-SOURCE VOLTAGE (V) 800 ID = -4.2A VDS = -5V -10V CISS f = 1 MHz VGS = 0 V 4 3 CAPACITANCE (pF) -15V 600 400 2 COSS 1 200 CRSS 0 0 1 2 3 4 5 Qg, GATE CHARGE (nC) 0 0 5 10 15 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 100 P(pk), PEAK TRANSIENT POWER (W) 10 Figure 8. Capacitance Characteristics. -ID, DRAIN CURRENT (A) 10 RDS(ON) LIMIT 1 100µs 1ms 10ms 100ms 1s 10s DC 8 SINGLE PULSE RθJA = 110°C/W TA = 25°C 6 4 0.1 VGS = -4.5V SINGLE PULSE RθJA = 110oC/W TA = 25oC 2 0.01 0.1 1 10 100 -VDS, DRAIN-SOURCE VOLTAGE (V) 0 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 110 C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.01 0.1 t1, TIME (sec) 1 10 100 1000 o 0. 0.1 0.1 0.0 5 0.0 0.01 SINGLE PULSE 0.01 0.0001 0.001 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDJ129P Rev F1 (W) FDJ129P Dimensional Outline and Pad Layout FDJ129P Rev F1 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11
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