FDMF6705

FDMF6705 - XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module March 2011 FDMF6705 – XS™ DrMOS — Extra-Small, HighPerformance, High-Frequency DrMOS Module Benefits Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions Fully Optimized System Efficiency Clean Switching Waveforms with Minimal Ringing High-Current Handling Description The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solutions for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6705 integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance, and Power MOSFET RDS(ON). XS™ DrMOS uses Fairchild's high-performance PowerTrench® MOSFET technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications. A new driver IC with reduced dead times and propagation delays further enhances the performance of this part. A thermal warning function has been included to warn of a potential over-temperature situation. The FDMF6705 also incorporates features, such as Skip Mode (SMOD), for improved light-load efficiency along with a 3-state PWM input for compatibility with a wide range of PWM controllers. Features Over 93% Peak-Efficiency High-Current Handling of 43A High-Performance PQFN Copper Clip Package 3-State 5V PWM Input Driver Shorter Propagation Delays than FDMF6704 Shorter Dead Times than FDMF6704 Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Driver Output Disable Function (DISB# Pin) Internal Pull-Up and Pull-Down for SMOD# and DISB# Inputs, Respectively Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Fairchild SyncFET™ (Integrated Schottky Diode) Technology in the Low-Side MOSFET Integrated Bootstrap Schottky Diode Adaptive Gate Drive Timing for Shoot-through Protection Under-Voltage Lockout (UVLO) Optimized for Switching Frequencies up to 1MHz Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliant Based on the Intel® 4.0 DrMOS Standard Applications High-Performance Gaming Motherboards Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters Desktop Computers, V-Core and Non-V-Core DC-DC Converters W orkstations High-Current DC-DC Point-of-Load (POL) Converters Networking and Telecom Microprocessor Voltage Regulators Small Form-Factor Voltage Regulator Modules Ordering Information Part Number FDMF6705 Current Rating 38A Input Voltage 19V Maximum Frequency 1000kHz Package 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package Top Mark FDMF6705 www.fairchildsemi.com © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0 0 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Typical Application Circuit V5V CVDRV CVIN VIN 3V ~ 20.5V VDRV VCIN VIN DISB# DISB# BOOT RBOOT PWM Input OFF ON Open-Drain Output PWM CBOOT FDMF6705 PHASE SMOD# VSWH VOUT LOUT THWN# COUT CGND PGND Figure 1. Typical Application Circuit DrMOS Block Diagram VDRV VCIN UVLO BOOT VIN Q1 HS Power MOSFET DBoot DISB# 10 A VCIN RUP_PWM PWM RDN_PWM Input 3-State Logic GH Logic Level Shift GH 30kΩ PHASE Deadtime Control VDRV GL Logic VSWH GL 30kΩ THWN# Temp. Sense VCIN Q2 LS Power MOSFET 10 A CGND SMOD# PGND Figure 2. © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 DrMOS Block Diagram www.fairchildsemi.com 2 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Pin Configuration Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # 1 2 3 4 5, 37, 41 6 7 8 9 - 14, 42 15, 29 35, 43 16 – 28 36 38 39 40 Name Description W hen SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, SMOD# the low-side driver is disabled. This pin has a 10 A internal pull-up current source. Do not leave this pin floating. Do not add a noise filter capacitor. VCIN VDRV BOOT CGND GH IC bias supply. Minimum 1 F ceramic capacitor is recommended from this pin to CGND. Power for gate driver. Minimum 1 F ceramic capacitor is recommended to be connected as close as possible from this pin to CGND. Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE. IC ground. Ground return for driver IC. For manufacturing test only. This pin must float. Must not be connected to any pin. No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. Power input. Output stage supply voltage. Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. Power ground. Output stage ground. Source pin of low-side MOSFET. For manufacturing test only. This pin must float. Must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. Output disable. When LOW, this pin disables FET switching (GH and GL are held LOW). This pin has a 10 A internal pull-down current source. Do not leave this pin floating. Do not add a noise filter capacitor. PWM signal input. This pin accepts a 3-state logic-level PWM signal from the controller. PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. NC VIN VSWH PGND GL THWN# DISB# PWM © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 3 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VIN to PGND, CGND Pins Parameter VCIN, VDRV, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins BOOT, GH to VSWH, PHASE Pins BOOT, VSWH, PHASE, GH to GND Pins BOOT to VDRV Pins fSW =300kHz fSW =1MHz Min. Max. 6 25 6 25 22 43 38 3.5 Unit V IO(AV) (1) VIN=19V, VO=1.0V Junction-to-PCB Thermal Resistance A °C/W °C V θJPCB TSTG ESD Operating and Storage Temperature Range Electrostatic Discharge Protection Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -55 2000 2000 +150 Note: 1. IO(AV) is measured in Fairchild’s evaluation board. This rating can be changed with different application settings. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCIN VDRV VIN Parameter Control Circuit Supply Voltage Gate Drive Circuit Supply Voltage Output Stage Supply Voltage (2) Min. 4.5 4.5 3.0 Typ. 5.0 5.0 12.0 Max. 5.5 5.5 20.5 Unit V V V Note: 2. May be operated at lower input voltage. © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 4 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Electrical Characteristics Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = +25°C unless otherwise noted. Symbol Basic Operation IQ UVLO PWM Input RUP_PWM VIH_PWM VTRI_HI VTRI_LO VIL_PWM VHiZ_PWM DISB# Input VIH_DISB VIL_DISB IPLD tPD_DISBL tPD_DISBH Parameter Quiescent Current UVLO Threshold Condition IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float VCIN Rising Min. Typ. Max. Unit 2 2.9 3.1 0.4 10 10 3.30 3.20 1.00 0.85 2.3 2 0.8 10 3.55 3.45 1.25 1.15 160 2.5 3.80 3.70 1.50 1.40 200 2.7 3.3 mA V V k k V V V V ns V V V A ns ns UVLO_Hyst UVLO Hysteresis Pull-Up Impedance PWM High Level Voltage 3-State Rising Threshold 3-State Falling Threshold PWM Low Level Voltage 3-State Open Voltage High-Level Input Voltage Low-Level Input Voltage Pull-Down Current Propagation Delay Propagation Delay PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH 2 RDown_PWM Pull-Down Impedance tD_HOLD-OFF 3-State Shutoff Time 25 25 SMOD# Input VIH_SMOD VIL_SMOD IPLM tPD_SLGLL tPD_SHGLH High-Level Input Voltage Low-Level Input Voltage Pull-Up Current Propagation Delay Propagation Delay PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH 10 10 10 V 0.8 V A ns ns Thermal Warning Flag TACT TRST RTHWN Activation Temperature Reset Temperature Pull-Down Resistance IPLD=5mA SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH 150 135 30 °C °C 250ns Timeout Circuit tD_TIMEOUT Timeout Delay 250 ns Continued on the following page… © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 5 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Electrical Characteristics Typical values are VIN = 12V, VCIN = 5V, VDRV = 5V, and TA = +25°C unless otherwise noted. High-Side Driver RSOURCE_GH Output Impedance, Sourcing Source Current=100mA RSINK_GH tR_GH tF_GH tD_DEADON tPD_PLGHL tPD_PHGHH tPD_TSGHH Output Impedance, Sinking Rise Time Fall Time LS to HS Deadband Time PWM LOW Propagation Delay PWM HIGH Propagation Delay (SMOD Held LOW) Exiting 3-State Propagation Delay Sink Current=100mA GH = 10% to 90%, CLOAD=1.1nF GH = 90% to 10%, CLOAD=1.1nF GL Going LOW to GH Going HIGH, 2V GL to 10% GH PWM Going LOW to GH Going LOW, VIL_PWM to 90% GH PWM Going HIGH to GH Going HIGH, VIH_PWM to 10% GH (SMOD=LOW) PWM (from 3-State) Going HIGH to GH Going HIGH, VIH_PWM to 10% GH 1 0.8 12 11 10 16 30 30 30 ns ns ns ns ns ns Low-Side Driver RSOURCE_GL Output Impedance, Sourcing Source Current=100mA RSINK_GL tR_GL tF_GL Output Impedance, Sinking Rise Time Fall Time Sink Current=100mA GL = 10% to 90%, CLOAD=2.7nF GL = 90% to 10%, CLOAD=2.7nF SW Going LOW to GL Going HIGH, 2.2V SW to 10% GL PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL PWM (from 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL IF=10mA IR=1mA 22 1 0.5 12 8 12 9 20 25 ns ns ns ns ns tD_DEADOFF HS to LS Deadband Time tPD_PHGLL tPD_TSGLH Boot Diode VF VR Forward-Voltage Drop Breakdown Voltage PWM-HIGH Propagation Delay Exiting 3-State Propagation Delay 0.35 V V © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 6 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module V IH_PWM V IL_PWM PWM GL 90% 2.0V 10% 90% GH to SW 10% 1.2V t D_TIMEOUT (250ns Timeout) SW 2.2V t PD_PHGLL t D_DEADON Figure 5. t PD_PLGHL tD_DEADOFF PWM Timing Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 7 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. VIN=12V 300kHz 1MHz Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current IOUT = 30A fSW = 300kHz IOUT = 30A Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage fSW = 300kHz IOUT = 30A fSW = 300kHz IOUT = 30A Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 8 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. fSW = 300kHz IOUT = 30A IOUT = 0A Figure 12. Power Loss vs. Output Inductance Figure 13. Driver Supply Current vs. Frequency fSW = 300kHz IOUT = 0A Figure 14. Driver Supply Current vs. Driver Supply Voltage Figure 15. Driver Supply Current vs. Output Current Figure 16. PWM Thresholds vs. Temperature Figure 17. DISB# Thresholds vs. Temperature © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 9 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Typical Performance Characteristics (Continued) Test Conditions: VIN=12V, VOUT=1.0V, VCIN=5V, VDRV=5V, LOUT=320nH, TA=25°C, and natural convection cooling, unless otherwise specified. Figure 18. SMOD# Thresholds vs. Temperature Figure 19. BOOT Diode VF vs. Temperature VIN = 19V Figure 20. Power Loss vs. Output Current © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 10 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Functional Description The FDMF6705 is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz. 3-State PWM Input The FDMF6705 incorporates a 3-state PWM input gate drive design. The 3-state gate drive has both logic HIGH level and LOW level, along with a 3-state shutdown window. When the PWM input signal enters and remains within the 3-state window for a defined hold-off time (tD_HOLD-OFF), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high-and low-side MOSFETs to support features such as phase shedding, which is a common feature on multiphase voltage regulators. VCIN and Disable The VCIN pin is monitored by an under-voltage lockout (UVLO) circuit. When VCIN rises above ~3.1V, the driver is enabled for operation. When VCIN falls below ~2.7V, the driver is disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < VIL_DISB), which holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > VIH_DISB). Operation when Exiting 3-State Condition W hen exiting a valid 3-state condition, the FDMF6705 design follows the PWM input command. If the PWM input goes from 3-state to LOW, the low side MOSFET is turned on. If the PWM input goes from 3-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 22. The FDMF6705 design allows for short propagation delays when exiting the 3-state window (see Electrical Characteristics). Table 1. UVLO 0 1 1 1 UVLO and Disable Logic DISB# X 0 1 Open Driver State Disabled (GH, GL=0) Disabled (GH, GL=0) Enabled (See Table 2) Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced low RDS(ON) N-channel MOSFET. The bias for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW. Note: 3. DISB# has an internal pull-down current source of 10 A. Thermal Warning Flag The FDMF6705 provides a thermal warning flag (THWN) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). For use, the THWN output requires a pull-up resistor, which can be connected to VCIN. THWN does NOT disable the DrMOS module. 135°C Reset HIGH THWN Logic State LOW TJ_driverIC Figure 21. THWN Operation Normal Operation 150°C Activation Temperature Thermal Warning High-Side Driver The high-side driver is designed to drive a floating Nchannel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is inphase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the 3-state window for longer than the 3state hold-off time, tD_HOLD-OFF. © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 11 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Adaptive Gate Drive Circuit The driver IC advanced design ensures minimum MOSFET dead-time while eliminating potential shoot through (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 22 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 begins to turn off after some propagation delay (tPD_PHGLL). Once the GL pin is discharged below ~2V, Q1 begins to turn on after adaptive delay tD_DEADON. To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 begins to turn off after some propagation delay (tPD_PLGHL). Once the VSWH pin falls below ~2.2V, Q2 begins to turn on after adaptive delay tD_DEADOFF. Additionally, VGS(Q1) is monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven on after tD_TIMEOUT, regardless of SW state. This function is implemented to ensure CBOOT is recharged each switching cycle in the event that the SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay tD_TIMEOUT is longer than tD_DEADOFF. V IH_PWM V IH_PWM V TRI_HI V IH_PWM V IH_PWM V TRI_HI V TRI_LO V IL_PWM V IL_PWM PWM tR_GH less than t D_HOLD -OFF tF_GHS tD_HOLD -OFF 90% 1 0% GH to SW V IN CCM 2.2V SW DCM DCM V OUT GL 90% 2.0V 10% 9 0% 1 0% tPD_PHGLL tD_DEADON tPD_PLGHL tR_GL tD_DEADOFF tF_GL Enter 3-State tPD_TSGHH Exit 3-State tD_HOLD -OFF Enter 3 -State tPD_TSGHH Exit 3- State less than t D_HOLD -OFF tD_HOLD-OFF tPD_TSGLH Enter 3 -State Exit 3-State . Notes: t PD_xxx = propagation delay from external signal (PWM, SMOD, etc.) to IC generated signal. Example (t PD_PHGLL - PWM going high to LS Vgs (GL) going low). t D_xxx = delay from IC generated signal to IC generated signal. Example (t D_DEADON – LS Vgs (GL) low to HS Vgs (GH) high). PWM t PD_PHGLL t PD_PLGHL t PD_PHGHH SMOD t PD_SLGLL t PD_SHGLH = PWM rise to GL fall , V IH_PWM to 90% GL = PWM fall to GH fall, V IL_PWM to 90% GH = PWM rise to GH rise, V IH_PWM to 10% GH (assumes SMOD held low). Exiting 3-State t PD_TSGHH = PWM t PD_TSGLH = PWM 3-state to high to GH rise, V IH_PWM to 10% GH 3-state to low to GL rise, V IL_PWM to 10% GL = SMOD fall to GL fall, V IL_SMOD to 90% GL = SMOD rise to GL rise, V IH_SMOD to 10% GL Dead Times t D_DEADON = GL fall to GH rise, LS - comp trip value (~2.0V GL ) to 10% GH t D_DEADOFF = SW - node fall off to GL rise, SW -comp trip value (~ 2.2V) to 10% GL Figure 22. PWM and 3-StateTiming Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 12 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Skip Mode (SMOD) The SMOD function allows for higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as “Diode Emulation” Mode. When the SMOD pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode, gating on the low-side FET. When the SMOD pin is pulled LOW, the low-side FET is gated off. The SMOD pin is connected to the PWM controller, which enables or disables the SMOD automatically when the controller detects light-load condition from output current sensing. Normally this pin is active LOW. See Figure 23 for timing delays. Table 2. DISB# 0 1 1 1 1 1 SMOD Logic PWM X 3-State 0 1 0 1 SMOD# X X 0 0 1 1 GH 0 0 0 1 0 1 GL 0 0 0 0 1 0 Note: 4. The SMOD feature is intended to have low propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IL_PWM PWM V IH_PWM 90% GH to SW 10% 10% DCM 2.2V SW CCM CCM V OUT GL 90% 2.0V 2.2V 10% 10% tPD_PHGLL tPD_PLGHL tPD_SLGLL tPD_PHGHH tPD_SHGLH tD_DEADON tD_DEADOFF Delay from SMOD going LOW to LS VGS LOW HS turn -on with SMOD LOW. Delay from SMOD going HIGH to LS VGS HIGH Figure 23. SMOD Timing Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 13 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Application Information Supply Capacitor Selection For the supply input (VCIN), a local ceramic bypass capacitor is recommended to reduce noise and to supply the peak current. Use at least a 1 F X7R or X5R capacitor. Keep this capacitor close to the VCIN pin and connect it to the GND plane with vias. power to the logic section of the driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10 and 1 F. Power Loss and Efficiency Measurement and Calculation Refer to Figure 24 for power loss testing method. Power loss calculations are: PIN=(VIN x IIN) + (V5V x I5V) (W) PSW =VSW x IOUT (W) POUT=VOUT x IOUT (W) PLOSS_MODULE=PIN - PSW (W) PLOSS_BOARD=PIN - POUT (W) EFFMODULE=100 x PSW /PIN (%) EFFBOARD=100 x POUT/PIN (%) Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 24. A bootstrap capacitance of 100nF X7R or X5R capacitor is adequate. A series bootstrap resistor would be needed for specific applications to improve switching noise immunity. VCIN Filter The VDRV pin provides power to the gate drive of the high-side and low-side power FET. In most cases, it can be connected directly to VCIN, the pin that provides V5V A I5V CVDRV CVIN A I IN VIN VDRV VCIN VIN DISB# PWM Input OFF ON DISB# RBOOT BOOT PWM FDMF6705 VSWH SMOD# CBOOT IOUT LOUT V VSW COUT A VOUT OpenDrain Output PHASE THWN CGND PGND Figure 24. Power Loss Measurement Block Diagram © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 14 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines Figure 25 provides an example of a proper layout for the FDMF6705 and critical components. All of the highcurrent paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This technique aids in achieving a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. The following guidelines are recommendations for the PCB designer: 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, highcurrent flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high voltage and highfrequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 3. An output inductor should be located close to the FDMF6705 to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 4. PowerTrench® MOSFETs are used in the output stage. The Power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered as well. 6. Include a trace from PHASE to VSWH to improve noise margin. Keep the trace as short as possible. 7. The layout should include the option to insert a small-value series boot resistor between the boot capacitor and BOOT pin. The boot-loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor is normally not required, but is effective at controlling the highside MOSFET turn-on slew rate. This can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. Inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise tradeoffs must be considered. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. 8. CGND pad and PGND pins should be connected by plane GND copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of gate driver and MOSFET. 9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode. 10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. They should not be left floating. These pins should not have any noise filter capacitors. 11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as RBOOT, CBOOT, the RC snubber, and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias. © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 15 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Top View Figure 25. PCB Layout Example Bottom View © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 16 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C 2X 6.00 A 30 31 6.00 2.50 PIN#1 INDICATOR 5.80 4.50 21 20 0.40 0.65 0.25 0.10 C 2X TOP VIEW 40 10 0.35 0.15 2.10 1 SEE 0.60 DETAIL 'A' 0.50 TYP 1.60 11 0.40 21 0.50 20 (0.70) FRONT VIEW 4.40±0.10 (2.20) 0.10 CAB 0.05 C 0.30 30 0.20 (40X) 31 2.40±0.10 0.20 2.10 LAND PATTERN RECOMMENDATION PIN #1 INDICATOR 1.50±0.10 0.40 2.00±0.10 11 40 10 (0.20) 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2 0.50 (40X) 0.30 BOTTOM VIEW 1.10 0.90 0.10 C 0.08 C 0.30 0.20 0.05 0.00 DETAIL 'A' SCALE: 2:1 C SEATING PLANE Figure 26. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 17 FDMF6705- XS™ DrMOS — Extra-Small High-Performance, High-Frequency DrMOS Module © 2011 Fairchild Semiconductor Corporation FDMF6705 • Rev. 1.0.0 www.fairchildsemi.com 18