FDPF7N50

FDP7N50/FDPF7N50 500V N-Channel MOSFET April 2007 FDP7N50/FDPF7N50 500V N-Channel MOSFET Features • 7A, 500V, RDS(on) = 0.9Ω @VGS = 10 V • Low gate charge ( typical 12.8 nC) • Low Crss ( typical 9 pF) • Fast switching • 100% avalanche tested • Improved dv/dt capability UniFET Description TM These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficient switched mode power supplies and active power factor correction. D G GDS TO-220 FDP Series GD S TO-220F FDPF Series S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL Drain-Source Voltage Drain Current Drain Current Gate-Source voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) - Derate above 25°C (Note 2) (Note 1) (Note 1) (Note 3) Parameter - Continuous (TC = 25°C) - Continuous (TC = 100°C) - Pulsed (Note 1) FDP7N50 7 4.2 28 FDPF7N50 500 7* 4.2 * 28 * ±30 270 7 8.9 4.5 Unit V A A A V mJ A mJ V/ns 89 0.71 -55 to +150 300 31.3 0.25 W W/°C °C °C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purpose, 1/8” from Case for 5 Seconds * Drain current limited by maximum junction temperature. Thermal Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Typ. Thermal Resistance, Junction-to-Ambient FDP7N50 1.4 0.5 62.5 FDPF7N50 4.0 -62.5 Unit °C/W °C/W °C/W ©2007 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDP7N50/FDPF7N50 REV. B FDP7N50/FDPF7N50 500V N-Channel MOSFET Package Marking and Ordering Information Device Marking FDP7N50 FDPF7N50 Device FDP7N50 FDPF7N50 Package TO-220 TO-220F TC = 25°C unless otherwise noted Reel Size --- Tape Width --- Quantity 50 50 Electrical Characteristics Symbol Off Characteristics BVDSS ΔBVDSS / ΔTJ IDSS IGSSF IGSSR VGS(th) RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS ISM VSD trr Qrr NOTES: Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Conditions VGS = 0V, ID = 250μA ID = 250μA, Referenced to 25°C VDS = 500V, VGS = 0V VDS = 400V, TC = 125°C VGS = 30V, VDS = 0V VGS = -30V, VDS = 0V VDS = VGS, ID = 250μA VGS = 10V, ID = 3.5A VDS = 40V, ID = 3.5A VDS = 25V, VGS = 0V, f = 1.0MHz (Note 4) Min. 500 -----3.0 ------ Typ. -0.5 -----0.76 2.5 720 95 9 6 55 25 35 12.8 3.7 5.8 Max Units --1 10 100 -100 5.0 0.9 -940 190 13.5 20 120 60 80 16.6 --V V/°C μA μA nA nA V Ω S pF pF pF ns ns ns ns nC nC nC On Characteristics Dynamic Characteristics Switching Characteristics VDD = 250V, ID = 7A RG = 25Ω (Note 4, 5) ------(Note 4, 5) VDS = 400V, ID = 7A VGS = 10V -- Drain-Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0V, IS = 7A VGS = 0V, IS = 7A dIF/dt =100A/μs (Note 4) ------ ---275 0.04 7 28 1.4 --- A A V ns μC 1. Repetitive Rating: Pulse width limited by maximum junction temperature 2. IAS = 7A, VDD = 50V, L=10mH, RG = 25Ω, Starting TJ = 25°C 3. ISD ≤ 7A, di/dt ≤ 200A/μs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test: Pulse width ≤ 300μs, Duty Cycle ≤ 2% 5. Essentially Independent of Operating Temperature Typical Characteristics FDP7N50/FDPF7N50 REV. B 2 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Typical Performance Characteristics Figure 1. On-Region Characteristics 20 Top : VGS 10.0 V 8.0 V 7.5 V 7.0 V 6.5 V 6.0 V 5.5 V Bottom : 5.0 V Figure 2. Transfer Characteristics 10 1 ID , Drain Current [A] 15 ID, Drain Current [A] 150 C 10 0 o 10 25 C -55 C * Note: 1. VDS = 40V 2. 250μs Pulse Test -2 o o 5 * Notes : 1. 250μs Pulse Test 2. TC = 25 C o 10 -1 0 0 10 20 30 40 50 10 VDS, Drain-Source Voltage [V] 2 4 6 8 10 VGS , Gate-Source Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature RDS(ON) [Ω],Drain-Source On-Resistance 2.5 IDR , Reverse Drain Current [A] 10 1 2.0 VGS = 10V 1.5 1.0 VGS = 20V 10 0 150 C o 25 C * Notes : 1. VGS = 0V 2. 250μs Pulse Test o 0.5 * Note : TJ = 25 C o 0.0 0 5 10 15 20 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ID, Drain Current [A] VSD , Source-Drain Voltage [V] Figure 5. Capacitance Characteristics 12 Figure 6. Gate Charge Characteristics Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd VDS = 100V 1000 VGS, Gate-Source Voltage [V] 10 VDS = 250V VDS = 400V Ciss Coss Capacitance [pF] 8 6 100 Crss * Notes : 1. VGS = 0 V 2. f = 1 MHz 4 2 * Note : ID = 7 A 10 0 1 0 10 10 0 5 10 15 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] FDP7N50/FDPF7N50 REV. B 3 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Typical Performance Characteristics (Continued) Figure 7. Breakdown Voltage Variation vs. Temperature 1.2 Figure 8. On-Resistance Variation vs. Temperature 3.0 BVDSS, (Normalized) Drain-Source Breakdown Voltage Drain-Source On-Resistance 2.5 1.1 RDS(ON), (Normalized) 2.0 1.0 1.5 0.9 *Notes : 1. VGS = 0 V 2. ID = 250 μA 1.0 ∗Notes : 0.5 1. VGS = 10 V 2. ID = 3.5 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 9-1. Maximum Safe Operating Area - FDP7N50 Figure 9-2. Maximum Safe Operating Area - FDPF7N50 10 us 10 1 10 us 10 1 100 us 10 ms 100 us 1 ms 10 ms 100 ms DC ID, Drain Current [A] 10 0 100 ms Operation in This Area is Limited by R DS(on) ID, Drain Current [A] 1 ms DC 10 0 Operation in This Area is Limited by R DS(on) 10 -1 * Notes : o 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o 10 -1 * Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 10 -2 10 0 10 1 10 2 10 -2 10 0 10 1 10 2 VDS, Drain-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 10. Maximum Drain Current Vs. Case Temperature 8 6 ID, Drain Current [A] 4 2 0 25 50 75 100 o 125 150 TC, Case Temperature [ C] FDP7N50/FDPF7N50 REV. B 4 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Figure 11-1. Transient Thermal Response Curve - FDP7N50 10 0 D = 0 .5 ZθJC(t), Thermal Response 0 .2 0 .1 10 -1 0 .0 5 0 .0 2 0 .0 1 PDM t1 * N o te s : t2 o 1 . Z θ JC (t) = 1 .4 C /W M a x. s in g le p u ls e 10 -2 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z θ JC (t) 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] Figure 11-2. Transient Thermal Response Curve - FDPF7N50 D = 0 .5 ZθJC(t), Thermal Response 10 0 0 .2 0 .1 0 .0 5 10 -1 0 .0 2 0 .0 1 PDM t1 * N o te s : t2 o s in g le p u ls e 10 -2 -5 -4 -3 -2 1 . Z θ JC (t) = 4 .0 C /W M a x. 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C (t) 10 10 10 10 10 -1 10 0 10 1 t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ] FDP7N50/FDPF7N50 REV. B 5 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Gate Charge Test Circuit & Waveform Resistive Switching Test Circuit & Waveforms Unclamped Inductive Switching Test Circuit & Waveforms FDP7N50/FDPF7N50 REV. B 6 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Peak Diode Recovery dv/dt Test Circuit & Waveforms FDP7N50/FDPF7N50 REV. B 7 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Mechanical Dimensions TO-220 Dimensions in Millimeters FDP7N50/FDPF7N50 REV. B 8 www.fairchildsemi.com FDP7N50/FDPF7N50 500V N-Channel MOSFET Mechanical Dimensions (Continued) TO-220F 3.30 ±0.10 10.16 ±0.20 (7.00) ø3.18 ±0.10 2.54 ±0.20 (0.70) 6.68 ±0.20 15.80 ±0.20 (1.00x45°) MAX1.47 9.75 ±0.30 0.80 ±0.10 (3 ) 0° 0.35 ±0.10 2.54TYP [2.54 ±0.20] #1 2.54TYP [2.54 ±0.20] 4.70 ±0.20 0.50 –0.05 +0.10 2.76 ±0.20 9.40 ±0.20 Dimensions in Millimeters FDP7N50/FDPF7N50 REV. B 9 15.87 ±0.20 www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I31 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. No Identification Needed Full Production Obsolete Not In Production © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com