FDS4070N3

FDS4070N3 February 2004 FDS4070N3 40V N-Channel PowerTrench MOSFET General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for “low side” synchronous rectifier operation, providing an extremely low RDS(ON) in a small package. Features • 15.3 A, 40 V. RDS(ON) = 7.5 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • High power and current handling capability • Fast switching, low gate charge • FLMP SO-8 package: Enhanced thermal performance in industry-standard package size Applications • Synchronous rectifier • DC/DC converter 5 6 7 8 Bottom-side Drain Contact 4 3 2 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed Maximum Power Dissipation TA=25oC unless otherwise noted Parameter Ratings 40 ± 20 (Note 1a) Units V V A W °C 15.3 60 3.0 –55 to +150 (Note 1a) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 40 0.5 °C/W Package Marking and Ordering Information Device Marking FDS4070N3 Device FDS4070N3 Reel Size 13’’ Tape width 12mm Quantity 2500 units 2004 Fairchild Semiconductor Corporation FDS4070N3 Rev B2 (W) FDS4070N3 Electrical Characteristics Symbol EAS IAS BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR VGS(th) ∆VGS(th) ∆TJ RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd TA = 25°C unless otherwise noted Parameter Drain-Source Avalanche Energy Drain-Source Avalanche Current Test Conditions Single Pulse, VDD=40V, ID=15.3A Min Typ Max 310 15.3 Units mJ A Drain-Source Avalanche Ratings (Note 2) Off Characteristics Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse (Note 2) ID = 250 µA VGS = 0 V, ID = 250 µA, Referenced to 25°C VDS = 32 V, VGS = 0 V 40 42 1 100 –100 V mV/°C µA nA nA VGS = 20 V, VDS = 0 V VGS = –20 V, VDS = 0 V ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25 °C VGS = 10 V, ID = 15.3 A VGS = 10 V, ID=15.3A, TJ =125°C VDS = 10 V, ID = 15.3 A VDS = 20 V, f = 1.0 MHz V G S = 0 V, 2 3.9 –8 5.5 8 52 On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance 5 V mV/°C 7.5 12 mΩ S Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) VDD = 20 V, VGS = 10 V, ID = 1 A, RGEN = 6 Ω 16 12 41 29 VDS = 20 V, VGS = 10 V ID = 15.3 A, 47 15 14 29 22 66 46 67 ns ns ns ns nC nC nC 2819 600 291 pF pF pF Switching Characteristics Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge FDS4070N3 Rev B2 (W) FDS4070N3 Electrical Characteristics Symbol IS VSD trr Qrr TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max 2.5 Units A V nS nC Drain–Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward IS = 2.5 A VGS = 0 V, Voltage Diode Reverse Recovery Time IF = 15.3 A, diF/dt = 100 A/µs Diode Reverse Recovery Charge (Note 2) 0.7 32 39 1.2 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 40°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size pape 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0 FDS4070N3 Rev B2 (W) FDS4070N3 Typical Characteristics 60 50 ID, DRAIN CURRENT (A) 40 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 10V 7.0V 6.0V 3 5.5V VGS = 5.0V 2.6 2.2 1.8 1.4 1 0.6 5.0V 30 20 5.5V 6.0V 7.0V 10V 4.5V 10 0 0 0.25 0.5 0.75 1 1.25 1.5 VDS, DRAIN-SOURCE VOLTAGE (V) 0 10 20 30 40 50 60 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.015 RDS(ON), ON-RESISTANCE (OHM) 1.8 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.6 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 o ID = 15.3A VGS = 10V ID = 7.7A 0.013 0.011 TA = 125oC 0.009 0.007 TA = 25oC 0.005 0.003 4 5 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) 125 150 TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation withTemperature. 60 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 IS, REVERSE DRAIN CURRENT (A) VGS = 0V 10 TA = 125oC 1 25oC 0.1 0.01 0.001 0.0001 -55oC VDS = 5V 50 ID, DRAIN CURRENT (A) 40 30 TA =125oC 20 10 25oC -55oC 0 2.5 3 3.5 4 4.5 5 5.5 6 VGS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4070N3 Rev B2 (W) FDS4070N3 Typical Characteristics 10 VGS, GATE-SOURCE VOLTAGE (V) 4000 ID = 15.3 VDS = 10V 20V 30V 8 6 CAPACITANCE (pF) 3000 CISS f = 1MHz VGS = 0 V 2000 COSS 1000 4 2 CRSS 0 0 10 20 30 40 50 Qg, GATE CHARGE (nC) 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 1000 P(pk), PEAK TRANSIENT POWER (W) Figure 8. Capacitance Characteristics. 50 ID, DRAIN CURRENT (A) 100 RDS(ON) LIMIT 10 10s DC 1ms 10ms 100ms 1s 100µs 40 SINGLE PULSE RθJA = 85°C/W TA = 25°C 30 1 VGS = 10V SINGLE PULSE RθJA = 85oC/W TA = 25oC 0.01 0.01 0.1 1 20 0.1 10 10 100 0 0.01 0.1 1 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS4070N3 Rev B2 (W) FDS4070N3 Dimensional Outline and Pad Layout FDS4070N3 Rev B2 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8