FDS4072N3

FDS4072N3 February 2004 FDS4072N3 40V N-Channel PowerTrench MOSFET General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for “low side” synchronous rectifier operation, providing an extremely low RDS(ON) in a small package. Features • 12.4 A, 40 V RDS(ON) = 12 mΩ @ VGS = 4.5 V RDS(ON) = 10 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • High power and current handling capability • Fast switching • FLMP SO-8 package: Enhanced thermal performance in industry-standard package size Applications • Synchronous rectifier • DC/DC converter 5 6 7 8 Bottom-side Drain Contact 4 3 2 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed Power Dissipation TA=25oC unless otherwise noted Parameter Ratings 40 ± 12 (Note 1a) Units V V A W °C 12.4 60 3.0 1.5 –55 to +150 (Note 1a) (Note 1b) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) 40 0.5 °C/W °C/W Package Marking and Ordering Information Device Marking FDS4072N3 Device FDS4072N3 Reel Size 13’’ Tape width 12mm Quantity 2500 units 2004 Fairchild Semiconductor Corporation FDS4072N3 Rev B2 (W) FDS4072N3 Electrical Characteristics Symbol EAS IAS BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR VGS(th) ∆VGS(th) ∆TJ RDS(on) TA = 25°C unless otherwise noted Parameter Drain-Source Avalanche Energy Drain-Source Avalanche Current Test Conditions Single Pulse, VDD = 20V, ID=12.4 A Min Typ Max Units 200 12.4 mJ A Drain-Source Avalanche Ratings (Note 2) Off Characteristics Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse (Note 2) ID = 250 µA VGS = 0 V, ID = 250 µA, Referenced to 25°C VDS = 32 V, VGS = 12 V, VGS = –12 V , VGS = 0 V VDS = 0 V VDS = 0 V 40 38 1 100 –100 V mV/°C µA nA nA On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25°C VGS = 4.5 V, ID = 12.4 A VGS = 10 V, ID = 13.7 A VGS = 4.5 V, ID = 12.4 A,TJ = 125°C VDS = 10 V, ID = 12.4 A 1 1.3 –4.5 9.7 8.5 14.7 84 3 V mV/°C 12 10 20 mΩ gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD trr Qrr S Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) VDS = 20 V, f = 1.0 MHz V G S = 0 V, 4299 351 149 pF pF pF Switching Characteristics Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDD = 20 V, VGS = 4.5 V, ID = 1 A, RGEN = 6 Ω 20 12 52 18 36 22 83 32 46 ns ns ns ns nC nC nC VDS = 20 V, VGS = 4.5 V ID = 12.4 A, 33 7.8 8.1 Drain–Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 2.5 A Voltage IF = 12.4 A, Diode Reverse Recovery Time diF/dt = 100 A/µs Diode Reverse Recovery Charge 2.5 (Note 2) A V nS nC 0.7 30 90 1.2 FDS4072N3 Rev B2 (W) FDS4072N3 Electrical Characteristics Notes: TA = 25°C unless otherwise noted 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 40°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS4072N3 Rev B2 (W) FDS4072N3 Typical Characteristics 80 4.5V ID, DRAIN CURRENT (A) 60 2.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS =10V 1.6 3.0V 1.4 VGS = 2.5V 1.2 40 3.0V 3.5V 4.5V 10V 20 1 0 0 1 2 3 4 VDS, DRAIN-SOURCE VOLTAGE (V) 0.8 0 20 40 ID, DRAIN CURRENT (A) 60 80 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.025 RDS(ON), ON-RESISTANCE (OHM) 1.9 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID = 12.4A VGS = 4.5V 1.6 ID = 6.2A 0.02 1.3 TA = 125oC 0.015 1 0.01 0.7 TA = 25oC 0.005 0.4 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 1 4 7 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation withTemperature. 80 IS, REVERSE DRAIN CURRENT (A) Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 VDS = 5V ID, DRAIN CURRENT (A) 60 VGS = 0V 10 1 0.1 0.01 0.001 0.0001 TA = 125 C o 40 25 C o 20 -55 C o TA =125 C 25 C 0 1 1.5 2 o o -55 C 2.5 3 o 0 0.2 0.4 0.6 0.8 1 1.2 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4072N3 Rev B2 (W) FDS4072N3 Typical Characteristics 10 VGS, GATE-SOURCE VOLTAGE (V) 6000 ID = 12.4A 8 VDS = 10V 20V CAPACITANCE (pF) 5000 f = 1MHz VGS = 0 V CISS 30V 6 4000 3000 2000 1000 4 2 COSS CRSS 0 0 20 40 Qg, GATE CHARGE (nC) 60 80 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 1000 P(pk), PEAK TRANSIENT POWER (W) Figure 8. Capacitance Characteristics. 50 ID, DRAIN CURRENT (A) 100 RDS(ON) LIMIT 10 1 0.1 VGS = 4.5V SINGLE PULSE o RθJA = 85 C/W TA = 25 C o 100µs 1ms 10ms 100ms 1s 10s DC 40 SINGLE PULSE RθJA = 85°C/W TA = 25°C 30 20 10 0.01 0.01 0.1 1 10 100 0 0.01 0.1 1 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. 1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS4072N3 Rev B2 (W) FDS4072N3 Dimensional Outline and Pad Layout FDS4072N3 Rev B2 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8