FDS4080N7_04

FDS4080N7 February 2004 FDS4080N7 40V N-Channel FLMP PowerTrench MOSFET General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for “low side” synchronous rectifier operation, providing an extremely low RDS(ON) in a small package. Features • 13 A, 40 V RDS(ON) = 10 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • High power and current handling capability • Fast switching (Qg = 30 nC ) • FLMP SO-8 package: Enhanced thermal performance in industry-standard package size Applications • • Synchronous rectifier DC/DC converter 5 6 7 8 Bottom-side Drain Contact 4 3 2 1 Absolute Maximum Ratings Symbol VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed TA=25oC unless otherwise noted Parameter Ratings 40 ± 20 (Note 1a) Units V V A W °C 13 60 3.9 –55 to +150 Power Dissipation for Single Operation (Note 1a) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ambient (Note 1a) 38 1 °C/W °C/W Package Marking and Ordering Information Device Marking FDS4080N7 Device FDS4080N7 Reel Size 13’’ Tape width 12mm Quantity 2500 units 2004 Fairchild Semiconductor Corporation FDS4080N7 Rev D1 (W) FDS4080N7 Electrical Characteristics Symbol EAS IAS BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR VGS(th) ∆VGS(th) ∆TJ RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD TA = 25°C unless otherwise noted Parameter Drain-Source Avalanche Energy Drain-Source Avalanche Current Test Conditions Single Pulse, VDD = 10V, ID=13A Min Typ Max Units 200 13 mJ A Drain-Source Avalanche Ratings (Note 2) Off Characteristics Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse (Note 2) VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 32 V, VGS = 0 V VGS = 20 V, VDS = 0 V VGS = –20 V ,VDS = 0 V VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25°C VGS = 10 V, ID = 13 A VGS = 10 V, ID = 13 A, TJ=125°C VDS = 5 V, ID = 13 A 40 44 1 100 –100 V mV/°C µA nA nA On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance 2 3.9 –8 7.8 12 41 5 V mV/°C 10 21 mΩ S Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance (Note 2) VDS = 20 V, V GS = 0 V, f = 1.0 MHz 1750 357 138 pF pF pF Switching Characteristics Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDD = 20 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω 12 8 29 14 21 17 46 25 40 ns ns ns ns nC nC nC VDS = 20 V, ID = 13 A, VGS = 10 V 30 9 10 Drain–Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 3.2 A Voltage 3.2 (Note 2) A V 0.7 1.2 FDS4080N7 Rev D1 (W) FDS4080N7 Electrical Characteristics TA = 25°C unless otherwise noted Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 49°C/W when mounted on a 1in2 pad of 2 oz copper b) 85°C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS4080N7 Rev D1 (W) FDS4080N7 Typical Characteristics 60 6.0V 5.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 10V 7.0V 2.2 2 1.8 1.6 ID, DRAIN CURRENT (A) 45 VGS = 5.5V 30 6.0V 1.4 1.2 1 0.8 5.0V 15 7.0V 8.0V 10V 0 0 0.5 1 1.5 2 2.5 VDS, DRAIN-SOURCE VOLTAGE (V) 0 15 30 ID, DRAIN CURRENT (A) 45 60 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.03 RDS(ON), ON-RESISTANCE (OHM) 2.2 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.9 1.6 1.3 1 0.7 0.4 -50 -25 0 25 50 75 100 o ID = 13A VGS = 10V ID = 7A 0.025 0.02 TA = 125oC 0.015 TA = 25oC 0.01 125 150 0.005 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation withTemperature. 80 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 VDS = 5V ID, DRAIN CURRENT (A) 60 IS, REVERSE DRAIN CURRENT (A) TA =-55oC 25oC 125oC VGS = 0V 10 TA = 125oC 1 25oC 0.1 40 -55oC 0.01 0.001 0.0001 20 0 2.5 3.5 4.5 5.5 6.5 VGS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4080N7 Rev D1 (W) FDS4080N7 Typical Characteristics 10 VGS, GATE-SOURCE VOLTAGE (V) ID = 13 A 8 VDS = 10V 20V 30V 6 CAPACITANCE (pF) 2000 2500 f = 1MHz VGS = 0 V CISS 1500 4 1000 COSS 500 2 CRSS 0 0 5 10 15 20 25 30 35 Qg, GATE CHARGE (nC) 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. 100 Figure 8. Capacitance Characteristics. 50 1ms ID, DRAIN CURRENT (A) 10 P(pk), PEAK TRANSIENT POWER (W) 100µs RDS(ON) LIMIT 10ms 100ms 1s 10s DC 40 SINGLE PULSE RθJA = 85°C/W TA = 25°C 30 1 0.1 VGS = 10V SINGLE PULSE RθJA = 85oC/W TA = 25oC 20 10 0.01 0.1 1 10 100 VDS, DRAIN-SOURCE VOLTAGE (V) 0 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 RθJA(t) = r(t) * RθJA RθJA = 85 °C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 0.01 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDS4080N7 Rev D1 (W) FDS4080N7 Dimensional Outline and Pad Layout FDS4080N7 Rev D1 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I8