FDS8978

FDS8978 Dual N-Channel PowerTrench® MOSFET May 2007 FDS8978 N-Channel PowerTrench® MOSFET 30V, 7.5A, 18mΩ Features rDS(on) = 18mΩ, VGS = 10V, ID = 7.5A rDS(on) = 21mΩ, VGS = 4.5V, ID = 6.9A High performance trench technology for extremely low rDS(on) Low gate charge High power and current handling capability 100% Rg Tested RoHS Compliant D2 D1 D1 SO-8 S2 Pin 1 S1 G1 D2 D2 D2 G2 D1 D1 5 6 7 8 Q1 Q2 4 3 2 1 tm General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on) and fast switching speed. Applications DC/DC converters G2 S2 G1 S1 MOSFET Maximum Ratings TA = 25°C unless otherwise noted Symbol VDSS VGS ID EAS PD TJ, TSTG Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TA = 25oC, VGS = 4.5V, RθJA = 50oC/W) Pulsed Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W) 7.5 6.9 49 57 1.6 13 -55 to 150 A A A mJ W mW/oC oC Ratings 30 ±20 Units V V Thermal Characteristics RθJC RθJA RθJA Thermal Resistance, Junction to Case (Note 2) Thermal Resistance, Junction to Ambient (Note 2a) Thermal Resistance, Junction to Ambient (Note 2c) 40 78 135 o o C/W C/W oC/W Package Marking and Ordering Information Device Marking FDS8978 Device FDS8978 Package SO-8 1 Reel Size 330mm Tape Width 12mm Quantity 2500 units www.fairchildsemi.com ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B FDS8978 Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 24V VGS = 0V VGS = ±20V TJ = 150oC 30 1 250 ±100 V µA nA On Characteristics VGS(TH) rDS(on) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA ID = 7.5A, VGS = 10V Drain to Source On Resistance ID = 6.9A, VGS = 4.5V ID = 7.5A, VGS = 10V, TJ = 150oC 1.2 14 17 22 2.5 18 21 29 mΩ V Dynamic Characteristics CISS COSS CRSS RG Qg(TOT) Qg(5) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 10V Total Gate Charge at 5V Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain “Miller” Charge VDS = 15V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 10V V = 15V DD VGS = 0V to 5V ID = 7.5A 907 191 112 1.2 17 9 2.3 1.5 3.3 4.0 26 14 pF pF pF Ω nC nC nC nC nC Switching Characteristics (VGS = 10V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 15V, ID = 7.5A VGS = 10V, RGS = 16Ω 44 7 37 48 24 72 66 10.5 55.5 72 36 108 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 7.5A ISD = 2.1A ISD = 7.5A, dISD/dt = 100A/µs ISD = 7.5A, dISD/dt = 100A/µs 19 10 1.25 1.0 25 13 V V ns nC Notes: 1: Starting TJ = 25°C, L = 1mH, IAS = 7.5A, VDD = 30V, VGS = 10V. 2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. a) 78°C/W when mounted on a 0.5 in2 pad of 2 oz copper. b) 125°C/W when mounted on a 0.02 in2 pad of 2 oz copper. c) 135°C/W when mounted on a minimun pad. ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 2 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 1.2 1.0 0.8 0.6 0.4 8 7 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 6 5 4 3 2 1 0 25 RθJA = 78 C/W o VGS = 10V VGS = 4.5V 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 50 75 100 125 o 150 TA, AMBIENT TEMPERATURE ( C) Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 Figure 2. Maximum Continuous Drain Current vs Ambient Temperature 1 NORMALIZED THERMAL IMPEDANCE, ZθJA DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE RθJA = 135 C/W o 0.001 -4 10 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 1000 P(PK), PEAK TRANSIENT POWER (W) VGS = 10V SINGLE PULSE RθJA = 135 C/W o 100 TA = 25 C o 10 1 0.5 -4 10 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t, PULSE WIDTH (s) Figure 4. Single Pulse Maximum Power Dissipation ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 3 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 50 40 ID, DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX IAS, AVALANCHE CURRENT (A) VDS = 5V 30 TJ = 25oC 10 STARTING TJ = 25oC 20 10 0 1 STARTING TJ = 150oC 1 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms) TJ = 150oC TJ = -55oC 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Unclamped Inductive Switching Capability 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX Figure 6. Transfer Characteristics 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10V VGS = 5V VGS = 4.5V VGS = 3.5V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mW) 40 30 20 10 0 0.0 40 ID = 10.2A 30 20 ID = 1 A 10 VGS = 3V 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Gate Voltage and Drain Current 1.2 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.4 1.0 1.2 0.8 1.0 VGS = 10V, ID = 10.2A 0.8 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 4 Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 2000 CISS = CGS + CGD 1000 C, CAPACITANCE (pF) 1.05 1.00 CRSS = CGD COSS ≅ CDS + CGD 0.95 VGS = 0V, f = 1MHz 0.90 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 10 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 30 Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) Figure 12. Capacitance vs Drain to Source Voltage 60 100us ID, DRAIN CURRENT (A) VDD = 15V 8 10 1ms 6 1 4 THIS AREA IS LIMITED BY rDS(on) 10ms 100ms 1s 10s DC 0.1 2 WAVEFORMS IN DESCENDING ORDER: ID = 7.5A ID = 1A 0 3 6 9 12 15 18 SINGLE PULSE TJ = MAX RATED RθJA = 125 C/W o 0 Qg, GATE CHARGE (nC) 0.01 0.01 TA = 25oC 0.1 1 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 13. Gate Charge Waveforms for Constant Gate Currents Figure 14. Forward Bias Safe Operating Area ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 5 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG + BVDSS VDS VDD VDD - 0V IAS 0.01Ω 0 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD L Qg(TOT) VDS Qg(5) VGS VGS = 10V VGS + DUT Ig(REF) VDD Qgs2 VGS = 5V VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 90% 50% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 6 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance RθJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. (T –T ) JM A P DM = -----------------------------Rθ JA thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R θ JA = 64 + ------------------------------- 26 0.23 + Area (EQ. 2) (EQ. 1) In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient 150 120 90 60 30 0 10-1 100 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2 The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 200 RθJA = 64 + 26/(0.23+Area) RθJA (oC/W) 150 100 50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10 Figure 21. Thermal Resistance vs Mounting Pad Area ZθJA, THERMAL IMPEDANCE (oC/W) 101 t, RECTANGULAR PULSE DURATION (s) 102 103 Figure 22. Thermal Impedance vs Mounting Pad Area ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 7 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET PSPICE Electrical Model .SUBCKT FDS8978 2 1 3 *February 2005 Ca 12 8 7.8e-10 Cb 15 14 7.8e-10 Cin 6 8 .78e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 32.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.29e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.18e-9 RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.6e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 8.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=7.0e-3 TRS1=8e-4 TRS2=2e-7 + CJO=3.5e-10 M=0.55 TT=7e-11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1e-30 N=10 M=0.45) .MODEL MstroMOD NMOS (VTO=2.36 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.95 KP=5.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MweakMOD NMOS (VTO=1.57 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=15e-3 TC2=0.1e-5) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6) MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5).ENDSNote: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. LGATE GATE 1 RLGATE CIN LDRAIN 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO LSOURCE 8 RSOURCE 12 S1A 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 RLSOURCE SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 DPLCAP 10 RSLC2 5 51 ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6 ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 8 + - RDRAIN 21 16 DBODY www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET SABER Electrical Model REV February 2005 template FDS8978 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=7.0e-3,trs1=8e-4,trs2=2e-7,cjo=3.5e-10,m=0.55,tt=7e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=3.8e-10,isl=10e-30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.36,kp=150,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.95,kp=5.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.57,kp=0.02,is=1e-30, tox=1,rs=0.1) LDRAIN DPLCAP 5 sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0) RLDRAIN RSLC1 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5) 51 c.ca n12 n8 = 7.8e-10 RSLC2 c.cb n15 n14 = 7.8e-10 ISCL c.cin n6 n8 = .78e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 32.9GATE 1 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.29e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.18e-9 CA 12 LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DRAIN 2 DBODY RLGATE LSOURCE 7 RLSOURCE 18 RVTEMP SOURCE 3 RSOURCE S1A 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 19 VBAT + 22 res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 1.6e-3, tc1=15e-3,tc2=0.1e-5 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 8.9e-3, tc1=1e-3,tc2=3e-6 res.rvthres n22 n8 = 1, tc1=-2.0e-3,tc2=-6e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 9 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET SPICE Thermal Model REV February 2005 template FDS8878 n2,n1,n3 Copper Area =1.0 in2 CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 th JUNCTION RTHERM1 CTHERM1 8 RTHERM2 CTHERM2 7 RTHERM3 CTHERM3 SABER Thermal Model Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 } 2 6 RTHERM4 5 CTHERM4 RTHERM5 CTHERM5 4 RTHERM6 CTHERM6 3 RTHERM7 CTHERM7 2 RTHERM8 CTHERM8 tl CASE TABLE 1. THERMAL MODELS COMPONANT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7 0.52 in2 2.0e-1 1.0 3.0 15 21 31.3 0.76 in2 2.0e-1 1.0 3.0 13 19 29.7 1.0 in2 2.0e-1 1.0 3.0 12 18 25 ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 10 www.fairchildsemi.com FDS8978 Dual N-Channel PowerTrench® MOSFET tm TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx® Across the board. Around the world™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ E2CMOS™ EcoSPARK® EnSigna™ FACT Quiet Series™ FACT® FAST® FASTr™ FPS™ FRFET® GlobalOptoisolator™ GTO™ HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ Motion-SPM™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR® PACMAN™ PDP-SPM™ POP™ Power220® Power247® PowerEdge™ PowerSaver™ Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ The Power Franchise® ™ TinyBoost™ tm TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ UHC® UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I27 ©2007 Fairchild Semiconductor Corporation FDS8978 Rev. B 11 www.fairchildsemi.com