FDZ202P
January 2004
FDZ202P
P-Channel 2.5V Specified PowerTrench BGA MOSFET
General Description
Combining Fairchild’s advanced 2.5V specified PowerTrench process with state of the art BGA packaging, the FDZ202P minimizes both PCB space This BGA MOSFET embodies a and RDS(ON). breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, high current handling capability, ultralow profile packaging, low gate charge, and low RDS(ON).
Features
• –5.5 A, –20 V. RDS(ON) = 45 mΩ @ VGS = –4.5 V RDS(ON) = 75 mΩ @ VGS = –2.5 V • Occupies only 5 mm2 of PCB area: only 55% of the area of SSOT-6 • Ultra-thin package: less than 0.80 mm height when mounted to PCB • Outstanding thermal transfer characteristics: 4 times better than SSOT-6 • Ultra-low Qg x RDS(ON) figure-of-merit • High power and current handling capability
Applications
• Battery management • Load switch • Battery protection
D S G
D S S D
D S S D
Pin 1
S
F202
G
Pin 1
D
Bottom
Top
TA=25oC unless otherwise noted
D
Absolute Maximum Ratings
Symbol
VDSS VGSS ID PD TJ, TSTG
Parameter
Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous (Note 1a) – Pulsed Power Dissipation (Steady State) (Note 1a) Operating and Storage Junction Temperature Range
Ratings
–20 ±12 –5.5 –20 2 –55 to +150
Units
V V A W °C
Thermal Characteristics
RθJA RθJB RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1) (Note 1)
64 8 0.7
°C/W °C/W °C/W
Package Marking and Ordering Information
Device Marking 202P Device FDZ202P Reel Size 7’’ Tape width 8mm Quantity 3000 units
2004 Fairchild Semiconductor Corporation
FDZ202P Rev. D2 (W)
FDZ202P
Electrical Characteristics
Symbol
BVDSS ∆BVDSS ∆TJ IDSS IGSSF IGSSR VGS(th) ∆VGS(th) ∆TJ RDS(on) gFS Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd IS VSD trr Qrr
TA = 25°C unless otherwise noted
Parameter
Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage, Forward Gate–Body Leakage, Reverse
(Note 2)
Test Conditions
VGS = 0 V, ID = –250 µA ID = –250 µA, Referenced to 25°C VDS = –16 V, VGS = –12 V, VGS = 12 V, VGS = 0 V VDS = 0 V VDS = 0 V
Min
–20
Typ
Max Units
V mV/°C –1 –100 100 µA nA nA V mV/°C mΩ S pF pF pF
Off Characteristics
–17
On Characteristics
Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
(Note 2)
VDS = VGS, ID = –250 µA ID = –250 µA, Referenced to 25°C VGS= –4.5 V, ID= –5.5 A VGS= –2.5 V, ID= –4.0 A VGS= –4.5 V, ID= –5.5 A, TJ=125°C VDS = –5 V, ID = –5.5 A VDS = –10 V, f = 1.0 MHz V G S = 0 V,
–0.6
–0.9 3 37 57 50 15 884 258 103
–1.5
45 75 65
Dynamic Characteristics
Switching Characteristics
Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge
VDD = –6 V, VGS = –4.5 V,
ID = –1 A, RGEN = 6 Ω
12 9 36 24
22 18 58 38 13
ns ns ns ns nC nC nC
VDS = –10 V, VGS = –4.5 V
ID = –5.5 A,
9 2 3
Drain–Source Diode Characteristics and Maximum Ratings
Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = –1.7 A Voltage Diode Reverse Recovery Time IF = –5.5 A, diF/dt = 100 A/µs Diode Reverse Recovery Charge
(Note 2)
–0.76 25 26
–1.7 –1.2
A V nS nC
Notes: 1. RθJA is determined with the device mounted on a 1 in² 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to the circuit board side of the solder ball, RθJB, is defined for reference. For RθJC, the thermal reference point for the case is defined as the top surface of the copper chip carrier. RθJC and RθJB are guaranteed by design while RθJA is determined by the user's board design.
a)
64°C/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB
b)
128°C/W when mounted on a minimum pad of 2 oz copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDZ202P Rev D2 (W)
FDZ202P
Dimensional Outline and Pad Layout
FDZ202P Rev D2 (W)
FDZ202P
Typical Characteristics
20
2 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE
VGS = -4.5V -3.5V
-3.0V -2.5V
1.8 VGS = -2.5V 1.6 1.4 1.2 1 0.8
-ID, DRAIN CURRENT (A)
15
10
-3.0V -3.5V -4.0V -4.5V
-2.0V
5
0 0 1 2 3 4 -VDS, DRAIN-SOURCE VOLTAGE (V)
0
5
10 -ID, DRAIN CURRENT (A)
15
20
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.
0.18 RDS(ON), ON-RESISTANCE (OHM)
1.6 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE ID = -5.5A VGS = -4.5V 1.4
ID = -2.8 A
0.14
1.2
0.1
1
TA = 125oC
0.8
0.06
TA = 25oC
0.02
0.6 -50 -25 0 25 50 75 100
o
125
150
1.5
2
2.5
3
3.5
4
4.5
5
TJ, JUNCTION TEMPERATURE ( C)
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with Temperature.
15
Figure 4. On-Resistance Variation with Gate-to-Source Voltage.
100
VDS = -5V
-ID, DRAIN CURRENT (A)
-IS, REVERSE DRAIN CURRENT (A)
TA = -55oC
25oC 125oC
VGS = 0V 10 1 0.1 0.01 0.001 0.0001 TA = 125oC 25oC -55oC
10
5
0 0.5 1 1.5 2 2.5 3 -VGS, GATE TO SOURCE VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1
1.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.
FDZ202P Rev D2 (W)
FDZ202P
Typical Characteristics
5 -VGS, GATE-SOURCE VOLTAGE (V)
1600 ID = -5.5A VDS = -5V -10V 1200 CISS 800 COSS 400 CRSS f = 1MHz VGS = 0 V
4
-15V
3
2
1
CAPACITANCE (pF)
0 0 2 4 6 8 10 12 Qg, GATE CHARGE (nC)
0 0 5 10 15 20
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
P(pk), PEAK TRANSIENT POWER (W) 50
Figure 8. Capacitance Characteristics.
RDS(ON) LIMIT
1ms 10ms 100ms
ID, DRAIN CURRENT (A)
10
40
S IN G LE P U LS E R π JA = 1 28°C /W T A = 2 5°C
30
1 DC 0.1 VGS = -4.5V SINGLE PULSE R JA = 128oC/W TA = 25oC 0.01 0.1 1
1s
20
10
10
100
VDS, DRAIN-SOURCE VOLTAGE (V)
0 0.001
0.01
0.1
1 t 1 , TIM E (sec)
10
100
1000
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power Dissipation.
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
1
D = 0.5 0.2
RθJA(t) = r(t) + RθJA RθJA = 128 °C/W P(pk) t1 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2
SINGLE PULSE
0.1
0.1 0.05 0.02 0.01
0.01 0.001
0.01
0.1
1 t1, TIME (sec)
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design.
FDZ202P Rev D2 (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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DISCLAIMER
ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC OPTOPLANAR™ PACMAN™
POP™ Power247™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART START™ SPM™ Stealth™
SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™
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Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I7