FDZ209N

FDZ209N May 2004 FDZ209N 60V N-Channel PowerTrench BGA MOSFET General Description Combining Fairchild’s advanced PowerTrench process with state-of-the-art BGA packaging, the FDZ209N minimizes both PCB space and RDS(ON). This BGA MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, high current handling capability, ultra-low profile packaging, low gate charge, and low RDS(ON).   Features • 4 A, 60 V. RDS(ON) = 80 mΩ @ VGS = 5 V • Occupies only 5 mm2 of PCB area: only 55% of the area of SSOT-6 • Ultra-thin package: less than 0.80 mm height when mounted to PCB • Outstanding thermal transfer characteristics: 4 times better than SSOT-6 • Ultra-low Qg x RDS(ON) figure-of-merit • High power and current handling capability Applications • Solenoid Drivers D S D S S D D S S D D Index slot Index slot G D G Bottom Top TA=25oC unless otherwise noted S Absolute Maximum Ratings VDSS VGSS ID Symbol PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous (Note 1a) – Pulsed Power Dissipation (Steady State) (Note 1a) Operating and Storage Junction Temperature Range Parameter 60 ±20 4 20 2 –55 to +150 Ratings Units V V A W °C Thermal Characteristics RθJA RθJB RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) (Note 1) 64 8 0.7 °C/W Package Marking and Ordering Information Device Marking 209N Device FDZ209N Reel Size 7’’ Tape width 8mm Quantity 3000 units ©2004 Fairchild Semiconductor Corporation FDZ209N Rev B2 (W) FDZ209N Electrical Characteristics Symbol WDSS IAR BVDSS ∆BVDSS ∆TJ IDSS IGSS VGS(th) ∆VGS(th) ∆TJ RDS(on) gFS Ciss Coss Crss RG td(on) tr td(off) tf Qg Qgs Qgd IS VSD trr Qrr TA = 25° unless otherwise noted C Parameter Drain-Source Avalanche Energy Drain-Source Avalanche Current Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate–Body Leakage. (Note 2) Test Conditions Single Pulse, ID= 4 A VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 48 V, VGS = ±20 V, VGS = 0 V VDS = 0 V VDD = 30 V, Min Typ Max Units 90 4 mJ A V mV/°C 1 ±100 µA nA V mV/°C mΩ S pF pF pF Ω 32 8 27 16 9 ns ns ns ns nC nC nC 1.7 1.2 A V nS nC Drain-Source Avalanche Ratings (Note 2) Off Characteristics 60 59 On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance (Note 2) VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25°C VGS = 5 V, ID = 4 A VGS = 5 V, ID = 4 A, TJ=125°C VDS = 5 V, ID = 4 A VDS = 30 V, f = 1.0 MHz VGS = 15 mV, VDD = 30 V, VGS = 5 V, V GS = 0 V, 1 2.5 –6 60 91 12 657 76 32 3 80 130 Dynamic Characteristics f = 1.0 MHz ID = 1 A, RGEN = 6 Ω 1.5 18 4 15 8 Switching Characteristics Turn–On Delay Time Turn–On Rise Time Turn–Off Delay Time Turn–Off Fall Time Total Gate Charge Gate–Source Charge Gate–Drain Charge VDS = 30 V, VGS = 5 V ID = 4 A, 6.3 2.5 2.5 Drain–Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 1.7 A Voltage Diode Reverse Recovery Time IF = 4A diF/dt = 100 A/µs Diode Reverse Recovery Charge (Note 2) 0.77 27 (Note 2) 45 Notes: 1. RθJA is determined with the device mounted on a 1 in² 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to copper chip carrier. RθJC and RθJB are guaranteed by design while RθJA is determined by the user' board design. s the circuit board side of the solder ball, RθJB, is defined for reference. For RθJC, the thermal reference point for the case is defined as the top surface of the a) 64° C/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB b) 128° C/W when mounted on a minimum pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDZ209N Rev B2 (W) Dimensional Outline and Pad Layout FDZ209N FDZ209N Rev B2 (W) FDZ209N Typical Characteristics 20 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 5.0V 1.8 4.8V 4.5V ID, DRAIN CURRENT (A) 15 1.6 VGS = 4.0V 1.4 4.3V 10 4.3V 1.2 4.5V 4.8V 5.0V 4.0V 5 3.8V 1 0 0 1 2 3 4 5 6 7 VDS, DRAIN-SOURCE VOLTAGE (V) 0.8 0 5 10 ID, DRAIN CURRENT (A) 15 20 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.35 RDS(ON), ON-RESISTANCE (OHM) ID =2A 0.3 0.25 0.2 0.15 0.1 0.05 0 3 3.5 4 4.5 5 VGS, GATE TO SOURCE VOLTAGE (V) TA = 25oC TA = 125oC 1.8 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.6 1.4 1.2 1 0.8 0.6 0.4 -50 -25 0 25 50 75 100 o ID = 4A VGS = 5.0V 125 150 TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. 20 VDS = 5V ID, DRAIN CURRENT (A) 15 TA = -55 C o Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 VGS = 0V TA = 125oC 1 0.1 0.01 -55oC 0.001 0.0001 25 C o IS, REVERSE DRAIN CURRENT (A) 10 125 C o 10 25oC 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VGS, GATE TO SOURCE VOLTAGE (V) 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDZ209N Rev B2 (W) FDZ209N Typical Characteristics 7 VGS, GATE-SOURCE VOLTAGE (V) 6 ID = 4A VDS = 20V 40V 30V 1000 f = 1MHz VGS = 0 V CISS 800 CAPACITANCE (pF) 5 4 3 2 1 0 0 2 4 6 600 400 COSS 200 CRSS 8 10 0 0 10 20 30 40 50 60 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. 100 Figure 8. Capacitance Characteristics. 50 1ms ID, DRAIN CURRENT (A) 10 100ms 1 VGS = 5.0V SINGLE PULSE RθJA = 128oC/W TA = 25oC 0.01 0.1 1 10 100 VDS, DRAIN-SOURCE VOLTAGE (V) DC 1s 10s 10ms P(pk), PEAK TRANSIENT POWER (W) RDS(ON) LIMIT 40 SINGLE PULSE RθJA = 128° C/W TA = 25° C 30 20 0.1 10 0 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RθJA(t) = r(t) * RθJA RθJA = 128 ° C/W P(pk) t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.1 0.1 0.05 0.02 t1 0.01 0.01 0.001 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDZ209N Rev B2 (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11