FIN1028_04

FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver March 2001 Revised May 2004 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1028 can be paired with its companion driver, the FIN1027, or any other LVDS driver. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s Flow-through pinout simplifies PCB layout Ordering Code: Order Number FIN1028M (Note 1) FIN1028K8X (Preliminary) FIN1028MPX (Preliminary) Package Number M08A MAB08A MLP08C Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL] 8-Terminal Molded Leadless Package (MLP) Dual, MO-229, 2mm Square [TAPE and REEL] Note 1: D evices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Name ROUT1, ROUT2 RIN1+, RIN2+ RIN1−, RIN2− VCC GND Description LVTTL Data Outputs Non-inverting LVDS Inputs Inverting LVDS Inputs Power Supply Ground Connection Diagrams Pin Assignment for SOIC Function Table Input RIN+ L H RIN+ H L Outputs ROUT L H H (Top View) Terminal Assignments for MLP Fail Safe Condition H = HIGH Logic Level L = LOW Logic Level Fail Safe = Open, Shorted, Terminated (Top Through View) © 2004 Fairchild Semiconductor Corporation DS500503 www.fairchildsemi.com FIN1028 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) DC Input Voltage (RINx+, RINx−) DC Output Voltage (ROUTx) DC Output Current (IO) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260°C −0.5V to +4.6V −0.5V to +4.7V −0.5V to +6V 16 mA Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VIN) Magnitude of Differential Voltage (|VID|) Common-mode Input Voltage (VIC) Operating Temperature (TA) 0.05V to 2.35V 100 mV to VCC 3.0V to 3.6V 0 to VCC −65°C to +150°C 150°C −40°C to +85°C ≥ 6500V ≥ 300V Note 2: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol VTH VTL IIN II(OFF) VOH VOL VIK ICC CIN COUT Parameter Differential Input Threshold HIGH Differential Input Threshold LOW Input Current Power-OFF Input Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Power Supply Current Input Capacitance Output Capacitance Test Conditions See Figure 1 and Table 1 See Figure 1 and Table 1 VIN = 0V or VCC VCC = 0V, VIN = 0V or 3.6V IOH = −100 µA IOH = −8 mA IOH = 100 µA IOL = 8 mA IIK = −18 mA (RIN+ = 1V and RIN− = 1.4V) or (RIN+ = 1.4V and RIN− = 1V) 4 6 −1.5 9 VCC −0.2 2.4 0.2 0.5 −100 ±20 ±20 Min Typ (Note 3) 100 Max Units mV mV µA µA V V V mA pF pF Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLH tPHL tTLH tTHL tSK(P) tSK(LH), tSK(HL) tSK(PP) Parameter Differential Propagation Delay LOW-to-HIGH Differential Propagation Delay HIGH-to-LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 5) Part-to-Part Skew (Note 6) |VID| = 400 mV, CL = 10 pF, See Figure 1 and Figure 2 Test Conditions Min Typ (Note 4) 0.9 0.9 0.5 0.5 0.4 0.3 1.0 2.5 2.5 Max Units ns ns ns ns ns ns ns Note 4: All typical values are at TA = 25°C and with VCC = 3.3V. Note 5: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 6: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. www.fairchildsemi.com 2 FIN1028 Note A: All input pulses have frequency = 10 MHz, tR or tF = 1 ns Note B: CL includes all probe and fixture capacitances FIGURE 1. Differential Driver Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 Resulting Differential Input Voltage (mV) VID 100 −100 100 −100 100 −100 600 −600 600 −600 600 −600 Resulting Common Mode Input Voltage (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3 FIGURE 2. AC Waveforms 3 www.fairchildsemi.com FIN1028 DC /AC Typical Performance Curves FIGURE 3. Output High Voltage vs. Power Supply Voltage FIGURE 4. Output Low Voltage vs. Power Supply Voltage FIGURE 5. Output Short Circuit Current vs. Power Supply Voltage FIGURE 6. Power Supply Current vs. Frequency FIGURE 7. Power Supply Current vs. Ambient Temperature FIGURE 8. Differential Propagation Delay vs. Power Supply Voltage www.fairchildsemi.com 4 FIN1028 DC /AC Typical Performance Curves (Continued) FIGURE 9. Differential Propagation Delay vs. Ambient Temperature FIGURE 10. Differential Skew (tPLH - tPHL) vs. Power Supply Voltage FIGURE 11. Differential Skew (tPHL - tPHL) vs. Ambient Temperature FIGURE 12. Differential Propagation Delay vs. Differential Input Voltage FIGURE 13. Differential Propagation Delay vs. Common-Mode Voltage FIGURE 14. Transition Time vs. Power Supply Voltage 5 www.fairchildsemi.com FIN1028 DC /AC Typical Performance Curves (Continued) FIGURE 15. Transition Time vs. Ambient Temperature FIGURE 16. Differential Propagation Delay vs. Load FIGURE 17. Differential Propagation Delay vs. Load FIGURE 18. Transition Time vs. Load FIGURE 19. Transition Time vs. Load FIGURE 20. Power Supply Current vs. Power Supply Voltage www.fairchildsemi.com 6 FIN1028 Tape and Reel Specification TAPE FORMAT for MLP Package Ao Bo D D1 Min 1.0 E F Ko P1 TYP 8.0 Po TYP 4.0 P2 T TYP 0.3 TC W Wc TYP 5.3 ±0.10 2x2 2.30 ±0.10 2.30 ±0.05 1.55 ±0.1 1.75 ±0.1 3.5 ±0.1 1.0 ±0/05 2.0 ±0.005 0.06 ±0.3 8.0 MLP Embossed Tape Dimensions (Dimensions are in millimeters) REEL DIMENSIONS (millimeters) Tape Width 8 mm Dia A Max 330 Dim B Min 1.5 Dia C Dia D Min 20.2 Dim N Min 178 Dim W1 Dim W2 Max 14.4 Dim W3 (LSL - USL) 7.9 ∼ 10.4 +0.5/−0.2 13 +2/−0 8.4 7 www.fairchildsemi.com FIN1028 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 8 FIN1028 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package Number MAB08A 9 www.fairchildsemi.com FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Terminal Molded Leadless Package (MLP) Dual, MO-229, 2mm Square Package Number MLP08C (Preliminary) Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com