FIN1215

FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers October 2003 Revised March 2005 FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers General Description The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 21 bits of input LVTTL data are sampled and transmitted. The FIN1218 and FIN1216 receive and convert the 3 serial LVDS data streams back into 21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN1217, at a transmit clock frequency of 85 MHz, 21 bits of LVTTL data are transmitted at a rate of 595 Mbps per LVDS channel. These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Features s Low power consumption s 20 MHz to 85 MHz shift clock support s 50% duty cycle on the clock output of receiver s r1V common-mode range around 1.2V s Narrow bus reduces cable size and cost s High throughput (up to 1.785 Gbps throughput) s Up to 595 Mbps per channel s Internal PLL with no external component s Compatible with TIA/EIA-644 specification s Devices are offered in 48-lead TSSOP packages Ordering Code: Order Number FIN1215MTD FIN1215MTDX_NL (Note 1) FIN1216MTD FIN1216MTDX_NL (Note 1) FIN1217MTD FIN1218MTD Package Number MTD48 MTD48 MTD48 MTD48 MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS500876 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 TABLE 1. Serializers/De-Serializers Chip Matrix Part FIN1217 FIN1218 FIN1215 FIN1216 CLK Frequency 85 85 66 66 21 3 3 21 LVTTL IN 21 LVDS OUT 3 3 21 LVDS IN LVTTL OUT Package 48 TSSOP 48 TSSOP 48 TSSOP 48 TSSOP Block Diagrams Transmitter Functional Diagram for FIN1217 and FIN1215 Receiver Functional Diagram for FIN1218 and FIN1216 www.fairchildsemi.com 2 FIN1217 • FIN1218 • FIN1215 • FIN1216 Transmitters Pin Descriptions Pin Names TxIn TxCLKIn TxOut TxOut TxCLKOut TxCLKOut PwrDn PLL VCC PLL GND LVDS VCC LVDS GND VCC GND NC I/O Type Number of Pins I I O O O O I I I I I I I 21 1 3 3 1 1 1 1 2 1 3 4 5 Description of Signals LVTTL Level Inputs LVTTL Level Clock Input The rising edge is for data strobe. Positive LVDS Differential Data Output Negative LVDS Differential Data Output Positive LVDS Differential Clock Output Negative LVDS Differential Clock Output LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in high-impedance state. Power Supply Pin for PLL Ground Pins for PLL Power Supply Pin for LVDS Outputs Ground Pins for LVDS Outputs Power Supply Pins for LVTTL Inputs Ground pins for LVTTL Inputs No Connect Connection Diagram FIN1217 and FIN1215 (21:3 Transmitter) Pin Assignment for TSSOP 3 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 Receivers Pin Descriptions Pin Names RxIn RxIn RxCLKIn RxCLKIn RxOut RxCLKOut PwrDn PLL VCC PLL GND LVDS VCC LVDS GND VCC GND NC I/O Type I I I I O O I I I I I I I Number of Pins 3 3 1 1 21 1 1 1 2 1 3 4 5 Description of Signals Negative LVDS Differential Data Inputs Positive LVDS Differential Data Inputs Negative LVDS Differential Clock Input Positive LVDS Differential Clock Input LVTTL Level Data Outputs Goes HIGH for PwrDn LOW LVTTL Clock Output LVTTL Level Input Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table Power Supply Pin for PLL Ground Pins for PLL Power Supply Pin for LVDS Inputs Ground Pins for LVDS Inputs Power Supply for LVTTL Outputs Ground Pins for LVTTL Outputs No Connect Connection Diagram FIN1218 and FIN1216 (3:21 Receiver) Pin Assignment for TSSOP www.fairchildsemi.com 4 FIN1217 • FIN1218 • FIN1215 • FIN1216 Truth Tables Transmitter Truth Table Inputs TxIn Active Active F F X H HIGH Logic Level L LOW Logic Level X Don’t Care Z High Impedance F Floating Note 2: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V. Note 3: TxCLKOutr will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z). Outputs PwrDn (Note 2) H H H H L TxOutr L/H L/H L L Z TxCLKOutr L/H X (Note 3) L/H X (Note 3) Z TxCLKIn Active L/H/Z Active F X Receiver Truth Table Inputs RxInr Active Active F (Note 5) F (Note 5) X H HIGH Logic Level L LOW Logic Level P Last Valid State X Don’t Care Z High Impedance F Failsafe Condition Note 4: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V. Note 5: Failsafe condition is defined as the input being terminated and un-driven (Z) or shorted or open. Note 6: If RxCLKInr is removed prior to the RxInr data being removed, RxOut will be the last valid state. If RxInr data is removed prior to RxCLKInr being removed, RxOut will be HIGH. Outputs PwrDn (Note 4) H H H H L RxOut L/H P H P (Note 6) L RxCLKOut L/H H L/H H H RxCLKInr Active F (Note 5) Active F (Note 5) X 5 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 Absolute Maximum Ratings(Note 7) Power Supply Voltage (VCC) TTL/CMOS Input/Output Voltage LVDS Input/Output Voltage LVDS Output Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Maximum Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 4 seconds) ESD Rating (HBM, 1.5 k:, 100 pF) LVDS I/O to GND All Pins (FIN1215, FIN1217 only) ESD Rating (MM, 0:, 200 pF) (FIN1215, FIN1217 only) 260 qC -0.3V to +4.6V Recommended Operating Conditions Supply Voltage (VCC) Operating Temperature (TA)(Note 7) Maximum Supply Noise Voltage (VCCNPP) 100 mVP-P (Note 8) 3.0V to 3.6V 0.5V to 4.6V -0.3V to +4.6V Continuous 40°C to 85°C 65qC to 150qC 150 qC !10.0 kV !6.5 kV !400V Note 7: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. Note 8: 100mV VCC noise should be tested for frequency at least up to 2 MHz. All the specification below should be met under such a noise. Transmitter DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9) Symbol VIH VIL VIK IIN Input High Voltage Input Low Voltage Input Clamp Voltage Input Current IIK VIN VIN Transmitter LVDS Output Characteristics (Note 10) VOD Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Short Circuit Output Current Disabled Output Leakage Current 21:3 Transmitter Power Supply Current for Worst Case Pattern (With Load) (Note 11), (Note 12) (85.0 MHz Specification for FIN1217 only) ICCPDT Powered Down Supply Current 25qC and with VCC 3.3V. Parameter Test Conditions Min 2.0 GND Typ Max VCC 0.8 Units V V V Transmitter LVTTL Input Characteristics 18 mA 0.4V to 4.6V GND 0.79 1.8 1.5 10.0 10.0 250 0 450 35.0 1.25 1.375 PA mV mV V mV mA 'VOD VOS RL 100 :, See Figure 1 1.125 'VOS IOS IOZ ICCWT VOUT DO 0V 0V to 4.6V, PwrDn 0V 3.5 r1.0 28.0 29.0 34.0 39.0 10.0 5.0 r10.0 46.2 51.7 57.2 62.7 55.0 PA Transmitter Supply Current 33.0 MHz RL 100 :, 40.0 MHz 65.0 MHz 85.0 MHz PwrDn 0.8V See Figure 3 mA PA Note 9: All Typical values are at TA Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD). Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels. Note 12: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. www.fairchildsemi.com 6 FIN1217 • FIN1218 • FIN1215 • FIN1216 Transmitter AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol tTCP tTCH tTCL tCLKT tJIT tXIT tTLH tTHL tSTC tHTC tTPDD tTCCD Parameter Transmit Clock Period Transmit Clock (TxCLKIn) HIGH Time Transmit Clock Low Time TxCLKIn Transition Time (Rising and Failing) TxCLKIn Cycle-to-Cycle Jitter TxIn Transition Time Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) TxIn Setup to TxCLNIn TxIn Holds to TCLKIn Transmitter Power-Down Delay Transmitter Clock Input to Clock Output Delay Transmitter Clock Input to Clock Output Delay Transmitter Output Data Jitter (f tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tTPPB0 tTPPB1 tTPPB2 tTPPB3 tTPPB4 tTPPB5 tTPPB6 tJCC 40 MHz) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 65 MHz) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 85 MHz) (FIN1217 only) (Note 14) Transmitter Output Pulse Position of Bit 0 Transmitter Output Pulse Position of Bit 1 Transmitter Output Pulse Position of Bit 2 Transmitter Output Pulse Position of Bit 3 Transmitter Output Pulse Position of Bit 4 Transmitter Output Pulse Position of Bit 5 Transmitter Output Pulse Position of Bit 6 FIN1217 Transmitter Clock Out Jitter (Cycle-to-Cycle) See Figure 19 tTPLLS Transmitter Phase Lock Loop Set Time (Note 15) f f f 40 MHz 65 MHz 85 MHz (FIN1217 only) See Figure 16 a 1 fx7 See Figure 16 a 1 fx7 See Figure 16 a 1 fx7 1.5 0.75 0.75 2.5 0 100 5.5 3.3V) 2.8 6.8 0 a 2a 3a 4a 5a 6a 0 a 2a 3a 4a 5a 6a 0 a 2a 3a 4a 5a 6a 350 210 110 0.25 a0.25 2a0.25 3a0.25 4a0.25 5a0.25 6a0.25 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 370 230 150 10.0 ms ps (10% to 90%) See Figure 7 See Figure 6 Test Conditions Min 11.76 0.35 0.35 1.0 Typ T 0.5 0.5 Max 50.0 0.65 0.65 6.0 3.0 6.0 1.5 1.5 Units ns T T ns ns ns ns ns ns ns ns ns LVDS Transmitter Timing Characteristics See Figure 4 See Figure 6 (f 85 MHz) (FIN1217 only) See Figure 13, (Note 13) See Figure 9 (TA 25qC and with VCC 0.25 a0.25 2a0.25 3a0.25 4a0.25 5a0.25 6a0.25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Transmitter Output Data Jitter (f 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 Transmitter Output Data Jitter (f 0.2 a0.2 2a0.2 3a0.2 4a0.2 5a0.2 6a0.2 See Figure 11, (Note 14) Note 13: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and Power-Down pin is above 1.5V. Note 14: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference (see Figure 15). Figure 16 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. Note 15: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns. 7 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 Receiver DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16) Symbol VIH VIL VOH VOL VIK IIN IOFF IOS VTH VTL VICM IIN Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Clamp Voltage Input Current Input/Output Power Off Leakage Current Output Short Circuit Current Differential Input Threshold HIGH Differential Input Threshold LOW Input Common Mode Range Input Current IOH IOL IIK VIN VCC VOUT Parameter Test Conditions Min 2.0 GND Typ Max VCC 0.8 3.3 0.3 Units V V V V V LVTTL/CMOS DC Characteristics 0.4 mA 2 mA 2.7 18 mA 0V to 4.6V 0V, 0V 1.5 10.0 10.0 PA PA mA mV mV V All LVTTL Inputs/Outputs 0V to 4.6V r10.0 60.0 120 100 Receiver LVDS Input Characteristics Figure 2, Table 2 Figure 2, Table 2 Figure 2, Table 2 VIN VIN Receiver Supply Current ICCWR 3:21 Receiver Power Supply Current for Worst Case Pattern (With Load) (Note 17) (85.0 MHz Specification for FIN1218 only) ICCPDR Powered Down Supply Current PwrDn CL 8 pF, See Figure 3 33.0 MHz 40.0 MHz 65.0 MHz 85.0 MHz 0.8V (RxOut stays LOW) 56.0 75.0 92.0 NA 66.0 74.0 102 125 400 mA 2.4V, VCC 0V, VCC 3.6V or 0V 3.6V or 0V 100 0.05 2.35 r10.0 r10.0 PA PA PA Note 16: All Typical Values are at TA 25qC and with VCC 3.3V. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD). Note 17: The power supply current for the receiver can be different with the number of active I/O channels. www.fairchildsemi.com 8 FIN1217 • FIN1218 • FIN1215 • FIN1216 Receiver AC Electrical Characteristics Over supply voltage and operating temperatures, unless otherwise specified Symbol tRCOL tRCOH tRSRC tRHRC tRCOP tRCOL tRCOH tRSRC tRHRC tRCOP tRCOL tRCOH tRSRC tRHRC tROLH tROHL tRCCD tRPDD tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSPB0 tRSPB1 tRSPB2 tRSPB3 tRSPB4 tRSPB5 tRSPB6 tRSKM Parameter RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut Receiver Clock Output (RxCLKOut) Period RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut Receiver Clock Output (RxCLKOut) Period RxCLKOut LOW Time RxCLKOut HIGH Time RxOut Valid Prior to RxCLKOut RxOut Valid After RxCLKOut Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Receiver Clock Input to Clock Output Delay Receiver Power-Down Delay Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit 2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit 2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 Receiver Input Strobe Position of Bit 0 Receiver Input Strobe Position of Bit 1 Receiver Input Strobe Position of Bit 2 Receiver Input Strobe Position of Bit 3 Receiver Input Strobe Position of Bit 4 Receiver Input Strobe Position of Bit 5 Receiver Input Strobe Position of Bit 6 RxIn Skew Margin (Note 18) f f f tRPLLS Receiver Phase Lock Loop Set Time 40 MHz; See Figure 18 65 MHz; See Figure 18 85 MHz (FIN1218 only); See Figure 17 (f 85 MHz) (FIN1218 only) See Figure 17 (f 65 MHz) See Figure 17 (f 40 MHz) CL 8 pF See Figure 5 See Figure 10 (Note 19) TA 25qC and VCC 3.3V See Figure 14 1.0 4.5 8.1 11.6 15.1 18.8 22.5 0.7 2.9 5.1 7.3 9.5 11.7 13.9 0.49 2.17 3.85 5.53 7.21 8.89 10.57 490 400 252 10.0 ms ps 3.5 See Figure 8 (Rising Edge Strobe) (f 85 MHz) (FIN1218 only) See Figure 8 (Rising Edge Strobe) (f 65 MHz) See Figure 8 (Rising Edge Strobe) (f 40 MHz) Test Conditions Min 10.0 10.0 6.5 6.0 15.0 5.0 5.0 4.5 4.0 11.76 4.0 4.5 3.5 3.5 Typ 11.0 12.2 11.6 11.6 T 7.8 7.3 7.7 8.4 T 6.3 5.4 6.3 6.5 2.2 2.1 6.9 5.0 5.0 7.5 1.0 2.15 5.8 9.15 12.6 16.3 19.9 23.6 1.4 3.6 5.8 8.0 10.2 12.4 14.6 1.19 2.87 4.55 6.23 7.91 9.59 11.27 50.0 6.0 6.5 50.0 9.0 9.0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figure 18 See Figure 12 Note 18: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. Note 19: Total channel latency from serializer to deserializer is (T  tTCCD)  (2*T  tRCCD). There is the clock period. 9 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 FIGURE 1. Differential LVDS Output DC Test Circuit Note A: For all input pulses, tR or tF  1 ns. Note B: CL includes all probe and jig capacitance. FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA 1.25 1.15 2.4 2.3 0.1 0 1.5 0.9 2.4 1.8 0.6 0 VIB 1.15 1.25 2.3 2.4 0 0.1 0.9 1.5 1.8 2.4 0 0.6 Resulting Differential Input Voltage Resulting Common Mode Input Voltage (mV) VID 100 (V) VIC 1.2 1.2 2.35 2.35 0.05 0.05 1.2 1.2 2.1 2.1 0.3 0.3 100 100 100 100 100 600 600 600 600 600 600 www.fairchildsemi.com 10 FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data strobe. FIGURE 3. “Worst Case” Test Pattern FIGURE 4. Transmitter LVDS Output Load and Transition Times FIGURE 5. Receiver LVTTL/CMOS Output Load and Transition Times FIGURE 6. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe) FIGURE 7. Transmitter Input Clock Transition Time 11 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms (Continued) FIGURE 8. Receiver Setup/Hold and HIGH/LOW Times FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe) FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe) www.fairchildsemi.com 12 FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms (Continued) FIGURE 11. Transmitter Phase Lock Loop Set Time FIGURE 12. Receiver Phase Lock Loop Set Time FIGURE 13. Transmitter Power-Down Delay 13 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms (Continued) FIGURE 14. Receiver Power-Down Delay Note: This output data pulse position works for both transmitter with 21 TTL inputs except the LVDS output bit mapping difference. All the information in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. FIGURE 15. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs FIGURE 16. Transmitter Output Pulse Bit Position www.fairchildsemi.com 14 FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms (Continued) FIGURE 17. Receiver Input Strobe Bit Position Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature). FIGURE 18. Receiver LVDS Input Skew Margin 15 www.fairchildsemi.com FIN1217 • FIN1218 • FIN1215 • FIN1216 AC Loading and Waveforms (Continued) Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter r3ns (cycle-to-cycle) clock input. The specific test methodology is as follows: • • Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right when data is HIGH (by switching between CLK1 and CLK2 in Figure 11) The r3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise (VCC noise frequency 2 MHz). FIGURE 19. www.fairchildsemi.com 16 FIN1217 • FIN1218 • FIN1215 • FIN1216 LVDS 21-Bit Serializers/De-Serializers Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 17 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com