FIN324CMLX

Click to see this datasheet in Simplified Chinese! µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays July 2008 FIN324C 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Features Ultra-Low Operating Power: ~4mA at 5.44MHz Supports Dual-Display Implementations with RGB or Microcontroller Interface No External Timing Reference Needed SPI Mode Support Single Device Operates as a Serializer or Deserializer Direct Support for Motorola -Style R/W Microcontroller Interface Direct Support for Intel -Style /WE, /RE Microcontroller Interface 15MHz Maximum Strobe Frequency Utilizes Fairchild’s Proprietary CTL Serial I/O Technology Available in BGA and MLP packages W ide Parallel Supply Voltage Range: 1.60 to 3.0V Low Power Core Operation: VDDS/A=2.5 to 3.0V Voltage Translation Capability Across Pair with No External Components High ESD Protection: >15kV IEC 61000 Power-Saving Burst-Mode Operation ® ® Description The FIN324C is a 24-bit serializer / deserializer with dual strobe inputs. The device can be configured as a master or slave device through the master/slave select pin (M/S). This allows for the same device to be used as either a serializer or deserializer, minimizing component types in the system. The dual strobe inputs allow implementation of dual-display systems with a single pair of µSerDes. The FIN324C can accommodate RGB, microcontroller, or SPI mode interfaces. Read and write transactions are supported when operating with a microcontroller interface for one or both displays. Unlike other SerDes solutions, no external timing reference is required for operation. The FIN324C is designed for ultra-low power operation. Reset (/RES) and standby (/STBY) signals put the device in an ultra-low power state. In standby mode, the outputs of the slave device maintain state, allowing the system to resume operation from the last-known state. The device utilizes Fairchild’s proprietary ultra-low power, low-EMI Current Transfer Logic™ (CTL) technology. The serial interface disables between transactions to minimize EMI at the serial interface and to conserve power. CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. Related Application Notes For additional Information, please visit: http://www.fairchildsemi.com/userdes AN-5058 µSerDes™ Frequently Asked Questions AN-5061 µSerDes™ Layout Guidelines AN-6047 FIN324C Reset and Standby Applications Single or Dual 16/18-Bit RGB Cell Phone Displays Single or Dual 16/18-Bit Cell Phone Displays with Microcontroller Interface Single or Dual Mobile Display at QVGA or HVGA Resolution © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Ordering Information Order Number FIN324CMLX FIN324CGFX Operating Temperature Range -30 to 85°C -30 to 85°C Package Description 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square 42-Ball, Ultra Small Scale Ball Grid Array (USSBGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch Eco Status Green RoHS Packing Method Tape & Reel Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Typical Application Diagram LCD ‘A’ WE/PCLK CKS WE/PCLK Data/Control Baseband / Microprocessor 2 Data/Control 24 FIN324 DS FIN324 24 WE/PCLK LCD ‘B’ Supports optional seconda ry display Figure 1. Typical Application Diagram © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 2 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Pin Definitions Pin M/S I/O Type CMOS IN # Pins 1 Description of Signals Master/Slave Control Input: The master is tied to the processor. The slave is tied to the display(s). M/S=1 MASTER, M/S=0 SLAVE Reset and power-down signal /RES=0: Resets and powers down all circuitry /RES=1: Device enabled Master standby signal /STBY=0: Device powered down /STBY=1: Device enabled Slave output slew rate control SLEW=1: Fast edge rate SLEW=0: Slow edge rate Parallel / SPI display interface select PAR/SPI=1: Parallel Interface PAR/SPI=0: SPI Interface using STRB0 and WCLK0 Master clock source select input. CKSEL=1: STRB1 and WCLK1 Active CKSEL=0: STRB0 and WCLK0 Active Parallel data I/O. I/O direction controlled by M/S pin and R/W internal state. DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only) DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only) Parallel data I/O. I/O direction controlled by M/S pin M/S=1: Inputs M/S=0: Outputs Read / Write input control or output signal. M/S=1: Input M/S=0: Output Functional operation: R/W=1: Read R/W=0: Write Word latch or pixel clock input. Word latch or pixel clock output. SPI mode signal pins. The master SCLK input is shared with CNTL[5] when M/S=1 and PARI/SPI=0. The master SDAT input is shared with CNTL[4] when M/S=1 and PARI/SPI=0. The master /CS input is shared with STRB0 when M/S=1 and PAR/SPI=0. The slave SCLK output is shared with DP[6] and CNTL[5] when M/S=0 and PAR/SPI=0. The slave SDAT output is shared with DP[7] and CNTL[4] when M/S=0 and PAR/SPI=0. The slave /CS output is shared with WCLK0 when M/S=0 and PAR/SPI=0. Serial clock differential signal(1) Serial data differential signal(1) Power supply for parallel I/O and internal circuitry. Power supply for serial I/O. Power supply for internal bit clock generator. Ground Pins: BGA - C1 and D2; E3 is for supplier use only and must be tied to ground. MLP - center pad; Pin 12 is for supplier use only and must be tied to ground. /RES CMOS IN 1 /STBY CMOS IN 1 SLEW CMOS IN 1 PAR/SPI CMOS IN 1 CKSEL CMOS IN 1 DP[17:0] CMOS I/O 18 CNTL[5:0] CMOS I/O 6 R/W CMOS I/O 1 STRB0 STRB1 W CLK0 WCLK1 CMOS IN CMOS OUT 2 2 SCLK SDAT /CS CMOS I/O 2 CKS+ CKSDS+ DSVDDP VDDS VDDA GND Differential Serial I/O Differential Serial I/O Supply Supply Supply Supply 2 2 1 1 1 1-3 Note: 1. Serial I/O signals are swapped on the slave so system traces do not have to cross between master and slave. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 3 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Pin Assignments 39 CNTL[5] or SCLK 39 CNTL[5] or SCLK 38 CNTL[4] or SDAT 38 CNTL[4] or SDAT 37 CNTL[3] 36 CNTL[2] 35 CNTL[1] 34 CNTL[0] 37 CNTL[3] 36 CNTL[2] 35 CNTL[1] 34 CNTL[0] 33 WCLK0 32 WCLK1 33 STRB0 32 STRB1 31 DP[17] CKSEL CKS+ CKSVDDS VDDA DSDS+ /RES PAR/SPI M/S 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 11 30 DP[16] 29 DP[15] 28 DP[14] 27 DP[13] 26 DP[12] 25 VDDP 24 DP[11] 23 DP[10] 22 DP[9] 21 DP[8] Master M/S=1 Ground Pad VDDP DS+ DSVDDS VDDA CKSCKS+ /RES PAR/SPI M/S 31 DP[17] 30 DP[16] 29 DP[15] 28 DP[14] 27 DP[13] 26 DP[12] 25 VDDP 24 DP[11] 23 DP[10] 22 DP[9] 21 DP[8] 20 40 R/W 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 11 40 R/W Slave M/S=0 Ground Pad Figure 2. MLP Pin Assignments (40 Pins, 6x6mm, .5mm Pitch, Top View) 42 FBGA Package 3.5mm x 4.5mm (.5mm Pitch) (Top View) 1 A B C D E F G 2 3 4 5 6 Master (M/S=1) 1 A B C D E F G R/W CKSEL GND CKS+ CKSDSDS+ 2 CNTL[4] or SDAT CNTL[5] or SCLK VDDP GND VDDS VDDA /RES 3 CNTL[2] CNTL[3] CNTL[1] M/S GND PAR/SPI /STBY 4 STROB0 STROB1 CNTL[0] DP[11] DP[2] DP[0] DP[1] 5 DP[17] DP[15] DP[13] DP[9] DP[7] DP[4] DP[3] 6 DP[16] DP[14] DP[12] DP[10] DP[8] DP[6] DP[5] A B C D E F G 1 R/W VDDP GND DS+ DSCKSCKS+ 2 CNTL[4] or SDAT CNTL[5] or SCLK VDDP GND VDDS VDDA /RES SLEW GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] SCLK or DP[6] SDAT or DP[7] /STBY GND DP[0] DP[1] DP[2] DP[3] DP[4] DP[5] DP[6] DP[7] Slave (M/S=0) 3 CNTL[2] CNTL[3] CNTL[1] M/S GND PAR/SPI SLEW 4 WCLK0 WCLK1 CNTL[0] DP[11] DP[2] DP[0] DP[1] 5 DP[17] DP[15] DP[13] DP[9] DP[7] or SDAT DP[4] DP[3] 6 DP[16] DP[14] DP[12] DP[10] DP[8] DP[6] or SCLK DP[5] Figure 3. BGA Pin Assignments © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 4 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays System Control Pins (M/S) Master / Slave Selection: A given device can be configured as a master or slave device based on the state of the M/S pin. Table 1. Master/Slave M/S 0 1 Configuration Slave Mode Master Mode (/RES, /STBY) Reset and Standby Mode Functionality: Reset and standby mode functionality is determined by the state of the /RES and /STBY signals for the master device and the /RES and internal standby-detect signal for the slave device. The /RES control signal has a filter that rejects spurious pulses on /RES. Table 4. Reset and Standby Modes /RES 0 (PAR/SPI) SPI Mode Selection: The PAR/SPI signal configures STRB0(WCLK0) for SPI mode write operation. STRB1(WCLK1) always operates in parallel mode. Control signals CNTL[5:0] all pass in SPI mode. In SPI mode, the SCLK signal is used to strobe the serializer. SPI mode supports SPI writes only. Table 2. Channel 0 PAR/SPI Configuration PAR /SPI 0 1 M/S=1 MASTER SPI Mode SDAT=CNTL[4] SCLK=CNTL[5] /CS=STRB0 Parallel Mode M/S=0 SLAVE SPI Mode SDAT=DP[7] & CNTL[4] SCLK=DP[6] & CNTL[5] /CS=WCLK0 Parallel Mode 1 1 /STBY X 0 1 (2) Master Reset Mode Standby Mode Operating Mode Slave Reset Mode Standby (2) Mode Operating Mode Note: 2. The slave device is put into standby mode through control signals sent from the master device. Table 5. Reset and Standby Mode States Pin DP[17:0] CNTL[5:0] STRB[0:1] (WCLK[0:1]) Master Reset / Standby Disabled Disabled Disabled Slave Reset Low Low High Slave Standby Last data Last data High (CKSEL) Strobe Selection Signal: The CKSEL signal exists only on the master device and determines which strobe signal is active. The active strobe signal is selected by CKSEL and PAR/SPI inputs. Table 3. PAR/SPI PAR /SPI 0 0 1 1 CKSEL 0 1 0 1 Master Strobe Source CNTL[5] STRB1 STRB0 STRB1 Slave Strobe Source DP[6] & CNTL[5] WCLK1 WCLK0 WCLK1 (SLEW) Slew Control: The slew control operates only when in slave mode. This signal changes the edge rate of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0 signals to optimize edge rate for the load being driven. Master read mode outputs have “slow” edge rates. See the AC Deserializer Specifications table for “slow” and “fast” edge rates. Table 6. Slew Rate Control /STBY (SLEW) 0 1 Slave M/S=0 “Slow” “Fast” © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 5 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays CMOS I/O Signals System Control Signals The system control signals consist of M/S, /RES, /STBY(SLEW), PAR/SPI, and CKSEL. For connectivity flexibility, these signals are over-voltage tolerant to the maximum supply voltage connected to the device. This allows these signals to be tied HIGH to either a VDDS or VDDP supply without static current consumption. These signals are all CMOS inputs and should never be allowed to float. Parallel I/O Signals The parallel data port signals consist of the DP[17:0], CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals. These signals have built-in voltage translation, allowing the signals of the master and slave to be connected to different VDDP supply voltages. Serial I/O Signals CTL I/O Technology The serial I/O is implemented using Fairchild’s proprietary differential CTL I/O technology. During data transfers, the serial I/O are powered up to a normal operating mode around .5V. Upon completion of a data transfer, the serial I/O goes to a lower power mode around VDDS. Serial I/O Orientation Logic The serial I/O signal traces should not cross between the master and the slave. The pin locations have been designed to eliminate the need to cross traces. See Table 7, Figure 4 and Figure 5. Table 7. Serial Pin Orientation Master (M/S=1) (Pad/Pin #) Package MLP BGA CKS+ 2 D1 CKS3 E1 DS6 F1 DS+ 7 G1 CKS+ 7 G1 Slave (M/S=0) (Pad/Pin #) CKS6 F1 DS3 E1 DS+ 2 D1 A 20 19 18 17 16 15 14 13 12 B 6 G F E D C B A 5 4 3 2 DS+ DSCKSCKS+ 1 1 2 3 4 5 6 C D E 21 22 23 24 25 26 27 28 29 30 11 10 M/S 40 39 38 37 36 35 34 33 32 MLP Master PAR/SPI /RES DS+ DSVDDA VDD S CKSCKS+ CKSEL(H) 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 31 30 29 28 27 26 25 24 23 22 21 CKSEL(H) (DS+) (DS-) VDD S VDD A (CKS-) (CKS+) /RES PAR/SPI M/S MLP Slave B GA Slave F G 31 32 33 34 35 36 37 38 39 BGA Master 40 12 13 14 15 16 17 18 19 Figure 4. BGA Pair Figure 5. MLP Pair © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 6 20 11 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Master/Slave READ Transactions Read transactions have two phases: The Read-Control Phase, where CNTL[5:0], R/W, CKSEL are transmitted to the deserializer; and the Read-Data Phase, where the DP[17:0] signals of the slave are read and transmitted back to the master device. The slave device generates its own strobe signal for latching in the data. Slave data must be valid prior to the WCLKn signal going HIGH. Master Serializer Operation (Read Control Phase) W hen the R/W signal is asserted HIGH and the STROBE signal transitions LOW, the Read-Control Phase of the read cycle is initiated. The R/W signal must not transition until the READ cycle completes. For a READ transaction, only eight control signals are captured. The 18 DP bits are ignored during the READ operation. The following sequence must occur for data to be serialized properly: 1. CPU selects input strobe source (CKSEL=0 or 1). 2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]). 3. CPU sends LOW STROBE signal. Slave Deserializer Operation (Read-Control Phase) 1. Captures data from serial transfer. 2. Internally decodes that this is a READ transaction. 3. Outputs control signals and prepares DP pins to accept data. 4. Outputs falling edge of WCLK pulse. Slave Serializer Read Operation (Read-Data Phase) The slave serializer is enabled on the tail end of the Read-Control Phase of operation. The operation of the serializer is identical to the master serialization except that the strobe signal is generated internally and only the data bits DP[17:0] are captured. 1. Display device outputs data onto DP bus on falling edge of WCLK. 2. Captures parallel data on generated rising edge of WCLK signal. 3. Serializes data stream. Master Deserializer Read Operation (Read-Data Phase): 1. Receives valid serial stream. 2. Outputs data DP[17:0]. 3. CPU asserts rising edge of strobe signal to capture data. SPI WRITE transaction SPI mode is activated by asserting the PAR/SPI signal low on both the master and slave device. A SPI write is only performed when CKSEL=0. During a SPI transaction, SCLK must be connected to CNTL[5] and is the strobe source for serialization. SDAT is on CNTL[4] and all of the remaining control signals and STRB0 are serialized. STRB0 should be connected to the SPI mode chip select. On the rising edge of SCLK, all eight control signals (CNTL[5:0], R/W, CKSEL) are captured and serialized. The data signals are not sent. The deserializer captures the serial stream and outputs it to the parallel port. As shown in Table 2, SDAT and SCLK are output on multiple pins. The DP[7] and DP[6] connections can be used for displays with dual-mode operation and the data pins are multiplexed with the SPI signals. CNTL[5] and CNTL[4] signals can be used when the signals are not multiplexed. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 7 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams Master Baseband Processor VDDP1 VDDS/A Slave VDDP2 VDDS/A C2 E2 F2 C2 E2 F2 VDDP VDDS/A /CS PCLK R,G,B[5:0] Hsync_D/C Vsync SD OE RESET VDDP1 VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP D4:G6 C4 C3 A3 B3 A2 B2 NC A1 NC D3 F3 G3 G2 B1 VDDP2 A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1 Sub-Display Data [7:0] D/C /CS RESET P/S Main Display PCLK R,G,B [5:0] Hsync Vsync SD OE STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL GND E3 GND D2 GND C1 G1 F1 D1 E1 GPIO /STBY /RES CKSEL E3 D2 C1 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Notes: 1. 2. 3. 4. 5. Write-only Interface. Unused slave output pin must be NC (No Connection). /CS used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. Figure 6. Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display Master Baseband Processor VDDP1 VDDS/A Slave VDDP2 VDDS/A C2 E2 F2 C2 E2 F2 VDDP VDDS/A /WE PCLK R,G,B[5:0] Hsync_ADDR Vsync SD OE RESET /CS GPIO /STBY /RES CKSEL VDDP1 VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP D4:G6 C4 C3 A3 B3 A2 B2 A1 NC D3 F3 G3 G2 B1 VDDP2 A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL E3 GND D2 GND C1 GND Sub-Display Data [7:0] ADDR /WE RESET P/S /CS Main Display PCLK R,G,B [5:0] Hsync Vsync SD OE G1 F1 D1 E1 E3 D2 C1 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Notes: 1. 2. 3. 4. 5. Write-only Interface. Unused slave output pin must be NC (No Connection). /WE used to strobe sub-display data. PCLK used for RGB mode. Pin numbers for BGA package. Figure 7. Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 8 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams (Continued) Master Baseband Processor VDDP1 VDDS/A Slave VDDP2 VDDS/A F6 SCLK DP[6] C2 E2 F2 C2 E2 F2 E5 SDAT DP[7] VDDP VDDS/A /CS PCLK R,G,B[5:0] Hsync Vsync SD D/C SDAT SCLK GPIO /STBY /RES CKSEL VDDP1 VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] G1 CKS+ CNTL[2] F1 CKS- CNTL[3] CNTL[4] D1 DS+ E1 DSCNTL[5] R/W M/S PAR/SPI E3 GND SLEW D2 GND /RES C1 GND VDDP D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 NC D3 F3 G3 G2 B1 VDDP2 A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY /RES CKSEL GND D2 GND C1 GND E3 Sub-Display SCLK SDAT /CS D/C RESET P/S Main Display PCLK R,G,B [5:0] Hsync Vsync SD Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Module 1 Notes: 1. 2. 3. 4. 5. 6. Write-only interface (R/W hardwired LOW). SPI sub-display interface PAR/SPI=LOW for both master and slave. . SCLK connected to CNTL[5]; SDAT connected to CNTL[4]. Shared data pin SDAT; SCLK connections on sub-display. Unused slave output pin must be NC (No Connection). Pin numbers for BGA package. Figure 8. Dual Display with RGB Main Display and SPI Sub-Display Interface Master Baseband Processor VDDP1 VDDS/A Slave VDDP2 VDDS/A C2 E2 F2 C2 E2 F2 VDDP VDDS/A /CS0 /CS1 DATA[17:0] D/C RESET 0 RESET 1 A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 VDDP1 VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI SLEW GND GND /RES GND VDDP D4:G6 C4 C3 A3 B3 A2 B2 A1 D3 F3 G3 G2 B1 VDDP2 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] G1 DS+ F1 CNTL[5] DSR/W M/S PAR/SPI /STBY /RES CKSEL GND E3 GND D2 GND C1 Sub-Display DATA [17:0] D/C /CS0 RESET 0 P/S Main Display /CS1 DATA[17:0] D/C RESET 1 R/W G1 F1 D1 E1 NC NC NC R/W GPIO /STBY /RES CKSEL D3 F3 G3 G2 B1 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. E3 D2 C1 Module 1 Notes: 1. 2. 3. 4. R/W interface. R/W signal connected to baseband microprocessor. . Unused slave output pin must be NC (No Connection). PAR/SPI connected HIGH to indicate parallel operation. . Pin numbers for BGA package. Figure 9. R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 9 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Application Diagrams (Continued) Master Baseband Processor VDDP1 VDDS/A Slave VDDP2 VDDS/A C2 E2 F2 C2 E2 F2 VDDP VDDS/A /RE /WE DATA[17:0] ADDR /CS0 /CS1 A4 B4 D4:G6 C4 C3 A3 B3 A2 B2 A1 VDDP1 VDDP VDDS/A WCLK0 A4 WCLK1 B4 DP[17:0] CNTL[0] CNTL[1] CKS+ CNTL[2] CKS- CNTL[3] CNTL[4] DS+ CNTL[5] DSR/W M/S PAR/SPI GND SLEW GND /RES GND VDDP D4:G6 C4 C3 A3 B3 A2 NC B2 NC A1 D3 F3 G3 G2 B1 VDDP2 STRB0 STRB1 DP[17:0] CNTL[0] CNTL[1] D1 CNTL[2] CKS+ E1 CKSCNTL[3] CNTL[4] DS+ G1 CNTL[5] DS- F1 R/W M/S PAR/SPI /STBY /RES CKSEL GND D2 GND C1 GND E3 Sub-Display /RE /WE DATA[7:0] ADDR /CS0 Main Display /RE /WE DATA[17:0] ADDR G1 F1 D1 E1 /CS1 D3 F3 GPIO /STBY /RES CKSEL0 CKSEL1 G3 G2 B1 E3 D2 C1 Edge Rate Control Option SLEW must be connected to VDDP or GND for low power. Module 1 Notes: 1. 2. 3. 4. 5. Dual display R/W Intel® interface. Unused slave output pin must be NC (No Connection). GPIO signal used to select READ or WRITE functionality. Connected to CKSEL and R/W. . Displays selected via the chip selects. Pin numbers for BGA package. Figure 10. Dual R/W x86-Style Microcontroller Display Interface Additional Application Information Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Design goal of 100-ohms differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. Visit Fairchild’s website at http://www.fairchildsemi.com/products/interface/userdes.html, contact your sales rep, or contact Fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 10 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD TSTG TJ TL ESD Supply Voltage All Input/Output Voltage Parameter Min. -0.5 -0.5 -65 Max. +3.6 VDDP+0.5 +150 +150 +260 15 14 7.5 Unit V V °C °C °C kV kV kV Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 4 Seconds) IEC 61000 Board Level Human Body Model, JESD22-A114, Serial I/0, /RES, PAR/SPI Pins Human Body Model, JESD22-A114, All Other Pins Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol (3) VDDA, VDDS Parameter Supply Voltage Supply Voltage Operating Temperature Min. 2.5 1.6 -30 Max. 3.0 VDDA/S +85 Unit V V °C VDDP TA Note: 3. VDDA and VDDS supplies must be hardwired together to the same power supply. VDDP must be less than or equal to VDDA/VDDS. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 11 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Electrical Specifications Values valid for over supply voltage and operating temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL IIN VGO Z Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Serial Input Voltage Ground Offset Slave Relative to Master 70 5.44MHz 12.00MHz 15.00MHz 5.44MHz 12.00MHz 15.00MHz SLEW=0 IOH=-250µA SLEW=1 IOH=-1mA SLEW=0 IOL=250µA SLEW=1 IOL=1mA -5 0 100 4 7 8 5 8 10 1.3 mA mA mA 120 Test Conditions Min. 0.7 x VDDP GND 0.8 x VDDP 0.2 x VDDP 5 Typ. Max. VDDP 0.3 x VDDP Unit V V V V µA V Ω DC Parallel I/O and Serial Characteristics Serial Transmission Line Impedance Power Characteristics IDYN_SER Dynamic Current of Master Device VDDA/S=2.75V, M/S=1, VDDP=1.8V, /STBY=1, /RES=1 VDDA/S=2.75V M/S=0 VDDP=1.8V, /STBY=1, /RES=1, CL=0pF IDYN_DES Dynamic Current of Slave Device Burst Standby Current of Master Burst Standby Current of Slave Standby Current Reset Current IBRST_M VDDA/S=2.75V, VDDP=1.8V, M/S=1, /STBY=1, /RST=1, No STROBE Signal, CL=0pF VDDA/S=2.75V, VDDP=1.8V, M/S=0, /STBY=1, /RST=1, No STROBE Signal, CL=0pF Serializer or Deserializer VDDS/A=VDDP=3.0V, /STBY=0, /RST=1 Serializer or Deserializer VDDS/A=VDDP=3.0V, /RST=0 CKSEL=0 STRB0 CKSEL=1 STRB1 0 0 0 DP before STRBn ↑, Figure 11 DP after STRBn ↑, Figure 11 R/W, CNTL before STRBn ↓ Figure 12 R/W, CNTL after STRBn ↓ Figure 12 CKSEL before active edge (4) STRBn , CKSEL before SPI /CS, SPI /CS before CKSEL Figure 13, Figure 14 5 15 0 16 IBRST_S 1.8 mA ISTBY IRES 10 10 µA µA AC Operating Characteristics fWSTRB0 fWSTRB1 fRSTRB tR, tF tS1 tH1 tS2 tH2 W rite Strobe Frequency W rite Strobe Frequency Read Strobe Frequency Input Edge Rates (5) 8 15 2 40 MHz MHz MHz ns ns ns ns ns W rite Mode Setup Time W rite Mode Hold Time READ Mode Setup Time READ Mode Hold Time CKSEL to STRBn Setup Time tS-STRB 50 ns © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 12 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Symbol Parameter Test Conditions SLEW=0, CL=5pF 20% to 80% SLEW=1, CL=5pF 20% to 80% SLEW=0, CL=5pF 20% to 80% SLEW=1, CL=5pF 20% to 80% (5) Min. 8 8 Typ. Max. 17 10 22 17 Unit AC Deserializer Specifications (5) (5) (5) tCS CNTL[5:0],R/W to Falling Edge of WCLKn M/S=0 , CL=5pF 50% to 50% Figure 15 PAR/SPI=1 , Figure 15 PAR/SPI=1 , Figure 15 PAR/SPI=1 , Figure 17 PAR/SPI=0 , Figure 16 M/S=0, R/W=0, PAR/SPI=1 Figure 15 M/S=0, R/W=0, PAR/SPI=1 Figure 15 (5,7) (5) (5) (5) (5) (5) (5) 0 50 18 200 40 50 18 200 40 4 60 24 224 60 56 20 220 56 ns ns ns ns ns ns ns ns ns tPDV-WR0 DP, CNTL to WCLK0 ↑ tPDV-WR1 DP, CNTL to WCLK1 ↑ tPDV-RD tPDV-SPI tPWL-WR0 tPWL-WR1 tPWL-RD tPWL-SPI CNTL to WCLKn ↑ Data, CNTL to SCLK ↑ W CLK0 Pulse Width Low; Write Mode W CLK1 Pulse Width Low; Write Mode Pulse Width Low of WCLK; Read Mode Pulse Width Low of WCLK; SPI Mode (5,7) M/S=0, R/W=1, PAR/SPI=1 Figure 17 (5,7) M/S=0, R/W=0, PAR/SPI=0 Figure 16 WRITE Mode, CKSEL=0 Figure 15 WRITE Mode, CKSEL=1 Figure 15 READ Mode Figure 17 READ Mode Figure 17 READ Mode Figure 17 (8,10,11) (5,7) AC Data Latencies (8,9,10) tPD-WR0 tPD-WR1 tPD-RD tPD-RDC tPD-RDD tPD-SPI W rite Latency W rite Latency Total Read Latency Read Control Latency Read Data Latency SPI Write Latency 147 (8,9,10) ns ns 480 ns ns ns ns 111 340 (8,10,12) 276 (8,10,13) 84 (8,10,14) SPI-WRITE Mode Figure 16 115 AC Oscillator Specifications fOSC tOSC-STBY tOSC-RES Serial Operating Frequency Oscillator Stabilization Time After Standby Oscillator Stabilization Time After Reset Power Down Relative to (15) /RES VDDA=VDDS=2.75V /RES=1, /STBY ↑ Transition VDDA=VDDS=2.75V /STBY=1, /RES ↑ Transition 240 275 15 30 310 30 50 MHz µs µs AC Reset and Standby Timing tVDD-OFF Figure 19 M/S=1, /STBY=1, R/W=0 Figure 19 M/S=1, /STBY=1 Figure 19 (17) (16) 20 0 200 15 20 µs ns ns µs tSTRB-RES /RES after last STRBn ↑ tSTRB-STBY tRES-OFF Standby time after last strobe Master/Slave Reset Disable Time M/S=1 /STBY=1, /RES=↓ Figure 19 © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 13 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Symbol tVDD-SKEW tVDD-RES tRES-STBY tDVALID Parameter Test Conditions Min. -∞ Typ. Max. +∞ Unit ms µs µs µs Allowed Skew between VDDP Figure 18 (18) and VDDA/S Minimum Reset Low Time After VDD Stable /STBY Wait Time After /RES ↑ /STBY to Active Edge of Strobe M/S=0, /RES=↑ Figure 18 (19) 20 20 30 M/S=1 /RES=1, /STBY= ↑ Figure 18 M/S=0 /RES=1 Figure 18 (20) Notes: 4. Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction. 5. Characterized, but not production tested. 6. Indirectly tested through serial clock frequency and serial data bit tests. 7. Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or SLEW=1. 8. Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator frequency. 9. Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 10. Assumes propagation delay across the flex cable and through the I/Os of 20ns. 11. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase latency (tPD-RDD). tPD-RD=tPD-RDC+ tPD-RDD. 12. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable flight times and I/O propagation delays. 13. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable flight times and I/O propagation delays. 14. SPI-Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time across the flex cable and I/O propagation delays. 15. Timing allows the device to completely reset prior to powering down. 16. Internal reset filter allows assertion prior to completion of read or write date transfer. 17. Timing ensures that last write transaction is complete prior to going into standby. 18. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being consumed. Guaranteed by characterization. 19. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that /RES be held low during the power supply ramp. 20. STRBn must be held off until internal oscillator has stabilized. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 14 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Typical Performance Characteristics Setup Time STROBE DP,CNTL Data tS1 Setup Time STRBn CNTL,R/W tS2 Control Hold Time STROBE DP,CNTL Data tH1 Hold Time STRBn CNTL,R/W Control tH2 Setup: CKSEL=0 or 1, R/W=0 Setup: CKSEL=0 or 1, R/W=1 Figure 11. Master Write Setup and Hold Time Figure 12. Master Read Setup and Hold Time tS-STRB STRB0 STRB1 SPI /CS CKSEL DP,CNTL Setup: CKSEL=0 or 1, R/W=0 tS-STRB tS-STRB STRB0 STRB1 tS-STRB tS-STRB CKSEL Data CNTL Setup: CKSEL=0 or 1, R/W=1 Data Figure 13. CKSEL Write Setup Time Figure 14. CKSEL Read Setup Time STRBn CKS DS Master SCLK CKS DS tPD-WR DP CNTL WCLKn tCS tPD-SPI Slave SDAT, CNTL, /CS tPWLn tPDV Slave SCLK tCS tPWL-SPI tPDV-SPI Setup: CKSEL=0 or 1, R/W=0, PAR/SPI=1 Setup: CKSEL=0, R/W=0, PAR/SPI=0, /CS=0 Figure 15. Slave Write Mode Timing Figure 16. Slave SPI Mode Timing © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 15 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Typical Performance Characteristics (Continued) tPD-RD STRBn CKS DS t PD-RD C CNTLSLV WCLKn] tCSn tPW L-RD n tPD-RD D t PDV-RD n DPSLV DPMSTR Setup: CKSEL=0 or 1, R/W=1, PAR/SPI=1 Figure 17. Slave Read Mode Timing VDDP VDDS/A /RES /STBY DP[23:0],R/W STRBn CKS DS Deserializer tVDD-SKEW tVDD-RES tRES-STBY Standby Mode Dynamic Mode Valid Data tDVALID OFF ON Figure 18. Power-Up Timing VDDP VDDS/A /RES /STBY STROBE tRES-OFF Dynamic Mode tSTRB-STBY tSTRB-RES Standby Mode tVDDOFF Deserializer ON OFF Figure 19. Power-Down Timing © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 16 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Physical Dimensions 0.15 C 6.00 B A (0.80) 6.00 PIN #1 IDENT 6.38MIN 0.15 C 4.77MIN 4.37MAX 0.80 MAX 0.10 C (0.20) 0.20MIN X4 0.08 C 0.05 0.00 SEATING PLANE C 0.28 MAX 4.20 4.00 X40 0.50 0.30 0.50TYP E 0.50 4.20 4.00 (DATUM B) (DATUM A) PIN #1 ID 0.18-0.30 0.50 0.10 0.05 CAB C NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WJJD-2 WITH EXCEPTION THAT THIS IS A SAWN VERSION.. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP40Arev3. Figure 20. 40-Lead, Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 17 µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays Physical Dimensions (Continued) Figure 21. 42-Ball, Ball Grid Array (BGA) Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 www.fairchildsemi.com 18 www.fairchildsemi.com µSerDes™ FIN324C — 24-Bit Ultra-Low Power Serializer / Deserializer Supporting Single and Dual Displays © 2006 Fairchild Semiconductor Corporation FIN324C Rev. 1.1.2 19