FL6300AMY-FS

FL6300A Quasi-Resonant Current Mode PWM Controller for Lighting Features Description  High-Voltage Startup  Quasi-Resonant Operation  Cycle-by-Cycle Current Limiting  Peak-Current-Mode Control  Leading-Edge Blanking (LEB)  Internal Minimum tOFF  Internal 5 ms Soft-Start  Over-Power Compensation  GATE Output Maximum Voltage  Auto-Recovery Over-Current Protection (FB Pin)  Auto-Recovery Open-Loop Protection (FB Pin)  Latch Protection VDD Pin and Output Voltage (DET The FL6300A lighting power controller includes a highly integrated PWM controller and provides several features to enhance the performance of flyback converters in medium- to high-power lumens applications. Pin) OVP  Frequency Operation Below 100 kHz Applications  General LED Lighting  Industrial, Commercial, and Residential Fixtures  Outdoor Lighting: Street, Roadway, Parking, Construction, and Ornamental LED Lighting Fixtures The FL6300A is applied on quasi-resonant flyback converters, where maximum operating frequency is limited to below 100 kHz. A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled to reduce power consumption. An internal valley voltage detector ensures that the power system operates at quasi-resonant operation over a wide-range of line voltage and load conditions, as well as reducing switching loss to minimize switching voltage on the drain of the power MOSFET. To minimize standby power consumption and improve light-load efficiency, a proprietary Green-Mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching pulse. The operating frequency is limited by minimum tOFF time, which is 38 µs to 8 µs. FL6300A also provides many protection functions. Pulse-by-pulse current limiting ensures the fixed-peak current-limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. When VDD drops below the turn-off threshold voltage, the controller disables PWM output. The gate output is clamped at 18 V to protect the power MOSFET from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. When over-voltage protection (OVP) is triggered by DET or when internal overtemperature protection (OTP) is triggered, the power system enters Latch Mode until AC power is removed. Ordering Information Part Number Operating Temperature Range Package Packing Method FL6300AMY -40°C to +125°C 8-Lead, Small Outline Package (SOP) Tape & Reel © 2010 Fairchild Semiconductor Corporation FL6300A • Rev. 1.0.2 www.fairchildsemi.com FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting November 2012 Figure 1. Typical Application Circuit for Flyback Converter Internal Block Diagram HV VDD 8 6 IHV INTERNAL BIAS OVP TIMER 52ms 4.2V VREF VDD 30µs 2R SOFT-START 5ms 2 Latched 27V STARTER 2.1ms FB FB OLP TWO STEPS UVLO 16V/10V/8V 1R S CS 3 Q PWM Current Limit LEB OVER-POWER COMPENSATION VALLEY DETECTOR VDET tOFF_MIN BLANKING S/H tOFF_OUT 7 NC VDET 2.5V Latched INTERNAL OTP DET 1 5V IDET 5 GATE DET OVP IDET 0.3V tOFF_MIN 18V R FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting Application Diagram Latched 4 GND 0.3V Figure 2. Functional Block Diagram Marking Information : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (M = SOP) P: Y = Green Package M: Manufacture Flow Code Figure 3. Marking Diagram © 2010 Fairchild Semiconductor Corporation FL6300A • Rev. 1.0.2 www.fairchildsemi.com 2 DET 1 8 HV FB 2 7 NC CS 3 6 VDD GND 4 5 GATE Figure 4. Pin Assignments Pin Definitions Pin # Name Description DET This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: - Generates a zero-current detection (ZCD) signal once the secondary-side switching current falls to zero. - Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. - Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The ratio of the divider determines what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. 2 FB The feedback pin should to be connected to the output of the error amplifier for achieving the voltage control loop. The FB pin should be connected to the output of the optical coupler if the error amplifier is equipped at the secondary-side of the power converter. For primary-side control applications, FB is applied to connect a RC network to the ground for feedback-loop compensation. The input impedance of this pin is a 5 k equivalent resistance. A one-third (1/3) attenuator connected between the FB and the PWM circuit is used for the loop-gain attenuation. FL6300A performs an open-loop protection (OLP) once the FB voltage is higher than a threshold voltage (around 4.2 V) for more than 55ms. 3 CS Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. 4 GND The power ground and signal ground. A 0.1 µF decoupling capacitor placed between VDD and GND is recommended. 5 GATE Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18 V. 6 VDD Power supply. The threshold voltages for startup and turn-off are 16 V and 10 V, respectively. The startup current is less than 20 µA and the operating current is lower than 4.5 mA. 7 NC No connect 8 HV High-voltage startup 1 © 2010 Fairchild Semiconductor Corporation FL6300A • Rev. 1.0.2 FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting Pin Configuration www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit 30 V VVDD DC Supply Voltage VHV HV 500 V VH GATE -0.3 25.0 V VL VFB, VCS, VDET -0.3 7.0 V PD Power Dissipation 400 mW TJ Operating Junction Temperature +150 °C +150 °C +270 °C TSTG TL ESD Storage Temperature Range -55 Lead Temperature (Soldering 10 Seconds) Human Body Model, JEDEC:JESD22-A114 3.0 Charged Device Model, JEDEC:JESD22-C101 1.5 KV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2010 Fairchild Semiconductor Corporation FL6300A • Rev. 1.0.2 Min. Max. Unit -40 +125 °C FL6300A — Quasi-Resonant Current Mode PWM Controller for Lighting Absolute Maximum Ratings www.fairchildsemi.com 4 Unless otherwise specified, VDD=10~25 V, TA=-40°C~125°C (TA=TJ). Symbol Parameter Conditions Min. Typ. Max. Unit 25 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage 15 16 17 V VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage 7 8 9 V IDD-ST Startup Current VDD=VDD-ON -0.16 V GATE Open 10 20 µA IDD-OP Operating Current VDD=15 V, fS=60 kHz, CL=2 nF 4.5 5.5 mA IDD-GREEN Green-Mode Operating Supply Current (Average) VDD=15 V, fS=2 kHz, CL=2 nF 3.5 mA IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF-0.5 V 70 80 90 µA VDD-OVP VDD Over-Voltage Protection (Latch-Off) 26 27 28 V tVDD-OVP VDD OVP Debounce Time 100 150 200 µs IDD-LATCH VDD OVP Latch-Up Holding Current VDD=5 V 42 µA HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on Pin HV IHV Supply Current Drawn from Pin HV VAC=90 V (VDC=120 V) VDD=0 V Leakage Current After Startup HV=500 V, VDD=VDD-OFF +1 V IHV-LC 50 V 4.0 mA 1 20 µA 1/2.75 1/3.00 1/3.25 V/V 3 5 7 KΩ 1.2 2.0 mA 1.5 Feedback Input Section AV=VCS/VFB, 0