FM25C020

FM25C020U 2K-Bit SPI Interface Serial CMOS EEPROM February 2002 FM25C020U 2K-Bit SPI™ Interface Serial CMOS EEPROM General Description The FM25C020U is a 2K (2,048) bit serial interface CMOS EEPROM (Electrically Erasable Programmable Read-Only Memory). This device fully conforms to the SPI 4-wire protocol which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Dataout (SO) pins to synchronously control data transfer between the SPI microcontroller and the EEPROM. In addition, the serial interface allows a minimal pin count, packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. This SPI EEPROM family is designed to work with the 68HC11 or any other SPI-compatible, high-speed microcontroller and offers both hardware (/WP pin) and software ("block write") data protection. For example, entering a 2-bit code into the STATUS REGISTER prevents programming in a selected block of memory and all programming can be inhibited by connecting the /WP pin to VSS; allowing the user to protect the entire array or a selected section. In addition, SPI devices feature a /HOLD pin, which allows a temporary interruption of the datastream into the EEPROM. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption for a continuously reliable non-volatile solution for all markets. Functions I SPI MODE 0 interface I 2,048 bits organized as 256 x 8 I Extended 2.7V to 5.5V operating voltage I 2.1 MHz operation @ 4.5V - 5.5V I Self-timed programming cycle I "Programming complete" indicated by STATUS REGISTER polling I /WP pin and BLOCK WRITE protection Features I Sequential read of entire array I 4 byte "Page write" mode to minimize total write time per byte I /WP pin and BLOCK WRITE protection to prevent inadvertent programming as well as programming ENABLE and DISABLE opcodes. I /HOLD pin to suspend data transfer I Typical 1µA standby current (ISB) for "L" devices and 0.1µA standby current for "LZ" devices. I Endurance: Up to 1,000,000 data changes I Data retention greater than 40 years Block Diagram /CS /HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS /WP Address Counter/ Register Program Enable VPP High Voltage Generator and Program Timer Decoder EEPROM Array Read/Write Amps Data In/Out Register 8 Bits Data Out Buffer SO Non-Volatile Status Register SPI™ is a trademark of Motorola Corporation © 2002 Fairchild Semiconductor Corporation FM25C020U Rev. B 1 www.fairchildsemi.com FM25C020U 2K-Bit SPI Interface Serial CMOS EEPROM Connection Diagram Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8) /CS SO /WP VSS 1 2 FM25C020U 3 4 6 5 SCK SI 8 7 VCC /HOLD Top View See Package Number N08E (N), M08A (M8), and MTC08 (MT8) Pin Names /CS SO /WP VSS SI SCK /HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply Ordering Information FM 25 C XX U LZ E XX Package Letter Description N M8 MT8 None V E Blank L LZ Ultralite Density/Mode Interface 020 C 25 FM 8-pin DIP 8-pin SO 8-pin TSSOP 0 to 70°C -40 to +125°C -40 to +85°C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and