FM27C040NE120

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM January 2000 FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM General Description The FM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 512K words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The “Don’t Care” feature on VPP during read operations allows memory expansions from 1M to 8 Mbits with no printed circuit board changes. The FM27C040 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 120ns access time provides high speed operation with high-performance CPUs. The FM27C040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The FM27C040 is manufactured using Fairchild’s advanced CMOS AMG™ EPROM technology. Features I High performance CMOS — 120, 150ns access time* I Simplified upgrade path —VPP is a “Don’t Care” during normal read operation I Manufacturer’s identification code I JEDEC standard pin configuration — 32-pin PDIP — 32-pin PLCC — 32-pin CERDIP *Note: New revision meets 70ns. Please check with factory for availability. Block Diagram VCC GND VPP OE CE/PGM Output Enable, Chip Enable, and Program Logic Data Outputs O0 - O7 Output Buffers Y Decoder .. Y Gating A0 - A18 Address Inputs ....... 4,194,304-Bit Cell Matrix X Decoder DS800033-1 AMG™ is a trademark of WSI, Inc. © 1999 Fairchild Semiconductor Corporation FM27C040 Rev. A 1 www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Connection Diagrams 27C010 FM27C040 XX/VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 27C010 XX/VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND Note: VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 VCC XX/PGM NC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 DS800033-2 Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin. Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10% Parameter/Order Number FM27C040 Q, N, V 90 FM27C040 Q, N, V 120 FM27C040 Q, N, V 150 Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10% Parameter/Order Number FM27C040 QE, NE, VE 90 FM27C040 QE, NE, VE 120 FM27C040 QE, NE, VE 150 Package Types: FM27C040 Q, N,V XXX Q = Quartz-Windowed Ceramic DIP N = Plastic DIP Access Time (ns) 90 120 150 Access Time (ns) 90 120 150 • All versions are guaranteed to function for slower speeds. Pin Names A0–A18 CE/PGM OE O0–O7 XX Addresses Chip Enable/Program Output Enable Outputs Don’t Care (During Read) V = PLCC • All packages conform to the JEDEC standard. 2 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Absolute Maximum Ratings (Note 1) Storage Temperature All Input Voltages except A9 with Respect to Ground VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground ESD Protection -65°C to +150°C -0.6V to +7V -0.6V to +14V -0.6V to +7V >2000V All Output Voltages with Respect to Ground VCC +1.0V to GND - 0.6V Operating Range Range Commercial Industrial Temperature 0°C to +70°C -40°C to +85°C VCC +5V +5V Tolerance ±10% ±10% Read Operation DC Electrical Characteristics Over operating range with VPP = VCC Symbol VIL VIH VOL VOH ISB1 ISB2 ICC IPP VPP ILI ILO Parameter Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) VCC Standby Current VCC Active Current VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current Test Conditions Min -0.5 2.0 Max 0.8 VCC +1 0.4 Units V V V V IOL = 2.1 mA IOH = -2.5 mA CE = VCC ± 0.3V CE = VIH CE = OE = VIL, I/O = 0 mA VPP = VCC VCC - 0.4 VIN = 5.5V or GND VOUT = 5.5V or GND -1 -10 f=5 MHz 3.5 100 1 30 10 VCC 1 10 µA mA mA µA V µA µA AC Electrical Characteristics Over operating range with VPP = VCC Symbol tACC tCE tOE tDF (Note 2) tOH (Note 2) Parameter Min Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Output Hold from Addresses CE or OE , Whichever Occurred First 0 120 Max 120 120 50 45 0 150 Min Max 150 150 50 55 Units ns Capacitance TA = +25°C, f = 1 MHz (Note 2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ 9 12 Max 15 15 Units pF pF 3 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM AC Test Conditions Output Load 1 TTL Gate and CL = 100 pF (Note 8) ≤5 ns 0.45V to 2.4V Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level (Note 10) Inputs 0.8V and 2V Outputs` 0.8V and 2V AC Waveforms (Notes 6, 7, 9) ADDRESSES 2V 0.8V Addresses Valid CE 2V 0.8V t CE t CF (Note 4, 5) OE 2V 0.8V t OE (Note 3) t DF (Note 4, 5) Valid Output Hi-Z t OH DS800033-4 OUTPUT 2V 0.8V Hi-Z t ACC (Note 3) Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max. 4 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Programming Waveform (Note 13) Program ADDRESSES 2V 0.8V Program Verify Address N t AS DATA 2V 0.8V Data In Stable ADD N t AH Hi-Z Data Out Valid ADD N t DS 6.25V t DH t DF VPP 12.75V t VCS VCC t VPS 2V 0.8V CE/PGM t PW OE 2V 0.8V t OES t OE DS800033-5 Programming Characteristics (Notes 11, 12, 13, 14) Symbol tAS tOES tDS tVPS tVCS tAH tDH tDF tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT Parameter Address Setup Time OE Setup Time Data Setup Time VPP Setup Time VCC Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage Conditions Min 1 1 1 1 1 0 1 Typ Max Units µs µs µs µs µs µs µs CE/PGM = X 0 45 50 60 105 100 30 30 ns µs ns mA mA °C V V ns CE/PGM = X CE/PGM = VIL 20 6.25 12.5 5 -0.1 2.4 0.8 0.8 25 6.5 12.75 30 6.75 13.0 0.0 4.0 0.45 V V 2.0 2.0 V V Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device. Note 14: During power up the CE/PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP. 5 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Turbo Programming Algorithm Flow Chart VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION PROGRAM ONE 50µs PULSE INCREMENT n NO DEVICE FAILED YES n = 10? FAIL VERIFY BYTE PASS LAST ADDRESS ? YES NO INCREMENT ADDRESS n=0 ADDRESS = FIRST LOCATION VERIFY BYTE INCREMENT ADDRESS NO PASS FAIL PROGRAM ONE 50 µs PULSE LAST ADDRESS ? YES CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V DS800033-6 Note: The standard National Semiconductor algorithm may also be used with it will have longer programming time. FIGURE 1. 6 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.25V during the three programming modes, and at 5V in the other three modes. supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 µF capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the pro-gramming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE/PGM has been low and addresses have been stable for at least tACC -tOE. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like in-puts (including OE) of the parallel EPROMs may be com-mon. A TTL low level program pulse applied to an EPROM’s CE/PGM input with VPP at 12.75V will program that EPROM. A TTL high level CE/ PGM input inhibits the other EPROMs from being programmed. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE). Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify. Output OR-Typing Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for FM27C040 is “8F08”, where “8F” designates that it is made by Fairchild Semiconductor, and “08” designates a 4 Megabit (512K x 8) part. The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A18, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 –O7 . Proper code access is only guaranteed at 25°C ± 5°C. Programming CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. The EPROM is in the programming mode when the VPP power 7 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Functional Description (Continued) ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å–4000Å range. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity X exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time increases by factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. Mode Selection The modes of operation of the FM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature. TABLE 1. Modes Selection Pins Mode Read Output Disable Standby Programming Program Verify Program Inhibit Note 15: X can be VIL or VIH CE/PGM VIL X VIH VIL X VIH OE VIL VIH X VIH VIL VIH VPP X (Note 15) X X 12.75V 12.75V 12.75V VCC 5.0V 5.0V 5.0V 6.25V 6.25V 6.25V Outputs DOUT High Z High Z DIN DOUT High Z TABLE 2. Manufacturer’s Identification Code Pins Manufacturer Code Device Code A0 (12) VIL VIH A9 (26) 12V 12V O7 (21) 1 0 O6 (20) 0 0 O5 (19) 0 0 O4 (18) 0 0 O3 (17) 1 1 O2 (15) 1 0 O1 (14) 1 0 O0 (13) 1 0 Hex Data 8F 08 8 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted 1.660 MAX 32 17 R 0.025 0.585 MAX 1 R 0.030-0.055 TYP 16 UV WINDOW SIZE AND CONFIGURATION DETERMINED BY DEVICE SIZE 0.005 MIN TYP 0.225 MAX TYP 0.125 MIN TYP 0.050-0.060 TYP Glass Sealant 0.175 MAX 0.10 MAX 0.590-0.620 0.015 -0.060 TYP 86°-94° TYP 0.150 MIN TYP 90° - 100° TYP 0.008-0.012 TYP +0.025 -0.060 0.060-0.100 TYP 0.090-0.110 TYP 0.015-0.021 TYP 0.685 32-Lead EPROM Ceramic Dual-In-Line Package (Q) Order Number FM27C040QXXX Package Number J32AQ 9 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted 0.485-0.495 [12.32-12.57] 0.007[0.18] S B D-E S 0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74] -H- Base Plane 0.015 [0.38] Min Typ 0.007[0.18] S B D-E S 0.002[0.05] S B -D4 5 1 30 29 0.541-0.545 [13.74-13-84] 60 ° ( [10.16] ) 0.400 0.490-0530 [12.45-13.46] 0.015[0.38] S C D-E, F-G S 0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11] -G- -FSee detail A -J13 14 0.002[0.05] S A 0.007[0.18] S A F-G S 0.013-0.021 TYP [0.33-0.53] 0.007[0.18] M 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 Max [0.13] 0.0100 [0.254] C D-E, F-G S 21 20 -E- 0.007[0.18] S A F-G S 0.118-0.129 [3.00-3.28] 0.010[0.25] L B A D-E, F-G S B 0.042-0.048 45°X [1.07-1.22] B 0.026-0.032 Typ [0.66-0.81] 0.007[0.18] S H D-E, F-G S ; ; 0.025 [0.64] Min 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64] 0.050 0.123-0.140 [3.12-3.56] 0.045 [1.14] 0.025 [0.64] Min 0.021-0.027 [0.53-0.69] Detail A Typical Rotated 90° R 0.030-0.040 [0.76-1.02] 0.065-0.071 [1.65-1.80] 0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84] Section B-B Typical 32-Lead PLCC Package (V) Order Number FM27C040VXXX Package Number VA32A 10 FM27C040 Rev. A www.fairchildsemi.com FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted 1.64 – 1.66 (41.66 – 42.164) 32 17 0.062 TYP (1.575) RAD 0.490 – 0.550 (12.446 – 13.97) 1 Pin No. 1 IDENT 16 0.580 (14.73) MIN 0.600 – 0.620 (15.240 – 15.748) 0.050 (1.270) TYP 0.125 – 0.165 (3.175 – 4.191) 0.145 – 0.210 (3.683 – 5.334) 90°–105° 0.008 - 0.015 (0.203 – 0.381) 0.040 - 0.090 (1.016 – 2.286) 86°- 94° TYP 0.018 ±0.003 (0.457 ±0.078) 0.015 (0.381) 0.120 – 0.150 (3.048 – 3.81) 0.100 ±0.010 (2.540 ±0.254) 0.035 – 0.07 (0.889 – 1.778) 32-Lead PDIP Package Order Number FM27C040NXXX Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 11 FM27C040 Rev. A www.fairchildsemi.com