FMS9874

www.fairchildsemi.com FMS9874 Graphics Digitizer 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps Features • • • • • • • • 3-channels 108 Ms/s conversion rate Programmable Clamps 500ps PLL clock jitter Adjustable Gain and offset Internal Reference Voltage I2C/SMBus compatible Serial Port 100-pin package 1600 x 1200/75Hz. ADC sampling clock can be derived from either an external source or incoming horizontal sync signal using the internal PLL. Output data is 24-bit RGB. Setup and control is via registers, accessible through an SMBus/I2C compatible serial port. Input amplitude range is 500–1000mV with either DC or AC coupling. Lower reference of AC coupled inputs is established with input clamps that are either internally generated or externally provided. Common to the three channels are clamp pulses, a bandgap reference voltage and clocks derived from a PLL or an external source. Digital data levels are 2.5–3.3 volt CMOS compliant. Power can be derived from a single +3.3 Volt power supply. Package is a 100-lead MQFP. Performance specifications are guaranteed over 0°C to 70°C range. Applications • Flat panel displays and projectors • RGB Graphics Processing Description As a fully integrated analog interface, the FMS9874 can directly digitize RGB graphics with resolutions up to 1024 x 768/85Hz and 1280 x 1024/60Hz; or using alternate pixel sampling, Block Diagram Clamp Gain & Offset A/D Converter DR7-0 RIN GIN Clamp Gain & Offset A/D Converter DG7-0 BIN Clamp Gain & Offset A/D Converter DB7-0 VREFIN CLAMP INVSCK XCK HSIN COAST LPF SDA SCL A0 A1 PWRDN HS PLL PXCK SCK Reference VREFOUT Timing Generator ICLAMP DCK DCK HSOUT Control ACSIN SYNC STRIPPER DCSOUT REV. 1.5 11/10/00 PRODUCT SPECIFICATION FMS9874 Architectural Overview Three separate digitizer channels are controlled by common timing signals derived from the Timing Generator. A/D clock signals can be derived from either a PLL or an external clock XCK. With the PLL selected, A/D clocks track the incoming horizontal sync signal connected to the HSIN input. Setup is controlled by registers that are accessible through the serial interface. VREFIN is the source of reference voltage for the three A/D converters. VREFIN can be connected to either the internal bandgap voltage, VREFOUT or an external voltage. Output Data Configuration Output data number format for each channel is binary: 00 corresponds to the lowest input; FF corresponds to the highest input. Conversion Channels Typical RGB graphics signals, RIN, GIN, BIN are ground referenced with 700mV amplitude. If a sync signal is embedded then the usual format is sync on green with the sync tip at ground, the black level elevated to 300mV and peak green at 1000mV. AC coupled video signals must be level shifted to establish the lower level of the conversion range by clamping to the black level of the back porch (see Figure 1). Clamp pulses are derived from internal Timing and Control logic or from the external CLAMP input. Timing and Control Timing and Control logic encompasses the Timing Generator, PLL and Serial Interface. Timing Generator All internal clock and synchronization signals are generated by the Timing Generator. Master Clock source is either the PLL or the external clock input, XCK. Bit XCKSEL selects the Master Clock source. Two clocks are generated. Sampling clock, SCK is supplied to all three A/D converters. Phase of SCK can be adjusted in 32 11.25 degree phase increments using the 5-bit PHASE register. DCK is the output data clock. DCK and DCK are supplied as outputs for synchronizing data transfer from the digitizer outputs. Horizontal sync applied to the input, HSIN is propagated by the Timing and Control to the HSOUT output with a delay that aligns leading and trailing edges with the output data. Phase Locked Loop With a horizontal sync signal connected to the HSIN input pin, the PLL generates a high frequency internal clock signal, PXCK that is fed to the Timing and Control logic. Frequency of PXCK is set by the register programmable PLL divide ratio, PLLN. COAST is an input that disables the PLL lock to the horizontal sync input, HSIN. If HSIN is to be disregarded for a period such as the vertical sync interval, COAST allows the VCO frequency to be maintained. Missing horizontal sync pulses during the vertical interval can cause tearing at the top of a picture, if COAST is not used. Two pixels per clock mode is set by programming the PLL to half the pixel rate. By toggling the INVCK pin between frames, even and odd pixels can be read on alternate frames. Serial Interface Registers are accessed through an I2C/SMBus compatible serial port. Four serial addresses are pin selectable. RIN, GIN, BIN ICLAMP Figure 1. Clamping to the back-porch Gain and Offset Gain and Offset registers serve two functions: adjustment of contrast and brightness by setting RGB values in tandem; matching the gain and offsets between channels, by setting RGB values individually to obtain the same output levels. A/D conversion range can be matched to the amplitude of the incoming video signal by programming Gain Registers GR, GG and GB, which vary sensitivity (LSB/volt) over a 2:1 range. Incoming video signal amplitudes varying from 0.5 to 1.0 volt can be accommodated. Input offset voltage of each converter is programmable in 1 LSB steps through the 6-bit OSR, OSG and OSB registers. Range of adjustment is equivalent to –31 to +32 LSB. A/D Converter Each A/D converter digitizes the analog input into 8-bit data words. Latency is 5–51/2 clock cycles, depending upon the state of CHINV. 2 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Pin Assignments 100-Lead MQFP (KG) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 REV. 1.5 11/10/00 Name GND RIN VDDA GND VDDA GND ACSIN GIN VDDA GND VDDA GND BIN VDDA GND VDDA GND INVSCK CLAMP SDA SCL A0 A1 VDDP VDDP No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name GND GND HSIN COAST GND VDDP XCK LPF NC GND VDDP GND VDDP GND GND GND NC NC NC NC NC NC NC GND VDDO No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND VDDO GND VDDO DG7 DG6 DG5 DG4 DG3 DG2 DG1 DG0 GND VDDO NC NC NC No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 GND VDDO DCK DCK HSOUT DCSOUT GND VDDO GND GND GND VDDA PWRDN VREFOUT VREFIN VDDA VDDA 3 PRODUCT SPECIFICATION FMS9874 Pin Descriptions Pin Name RIN, GIN, BIN DR7-0 DG7-0 DB7-0 CLAMP INVSCK Pin No. 2, 8, 13 76–83 63–70 51–58 19 18 Type/Value Input Output Output Output Input Input Pin Function Description Analog Inputs. Red Channel A Data Output. Green Channel A Data Output. Blue Channel A Data Output. External Clamp Input. Invert Sampling Clock. Inverts SCK, the internal clock sampling the analog inputs. Supports Alternate Pixel Sampling mode for capture pixel rates up to 216Ms/s. External Clock input. Enabled if register bit, XCKSEL = H. Replaces PXCK clock generated by PLL. If unused, connect to ground through a 10kΩ resistor. Output Data Clock. Clock for strobing output data to external logic. Output Data Clock Inverted. Inverted clock for strobing output data to external logic. Horizontal Sync Output. Reconstructed HSYNC delayed by FMS9874 latency and synchronized with DCK. Leading edge is synchronized to start of data output. Polarity is always active HIGH. Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source should be clamped at 3.3V or current limited to prevent overdriving ESD protection diodes. PLL Coast. Maintain frequency of PLL output clock PXCK, disregarding HSIN. If horizontal sync is missing during the vertical sync interval, PXCK clock frequency can be maintained by asserting COAST. PLL Low Pass Filter. Connect recommended PLL filter to LPF pin. (see Figure 13.) Analog Composite Sync Input. Input to sync stripper with 150mV threshold. Digital Composite Sync Output. Output from sync stripper. Bi-directional Serial Port Data. Bi-directional data. Input Input Input Input Serial Port Clock. Clock input. Address bit 0. Lower bit of serial port address. Address bit 1. Upper bit of serial port address. Power Down/Output Control. Powers down the FMS9874 and tri-states the outputs. Converter Channels Timing Generator XCK 32 Input DCK DCK HSOUT 86 87 88 Output Output Output Phase Locked Loop HSIN 28 Schmitt COAST 29 Input LPF Sync Stripper ACSIN DCSOUT Control SDA SCL A0 A1 PWRDN 33 Passive 7 89 20 21 22 23 96 4 REV. 1.5 11/10/00 PRODUCT SPECIFICATION FMS9874 Pin Descriptions Pin Name Power and Ground VDDA VDDP VDDO GND 3, 5, 9, 11, 14, 16, 95, 99, 100 ADC Supply Voltages. Provide a quiet noise free voltage. 24, 25, 31, 36, 38 50, 60, 62, 72, 85, 91 1, 4, 6, 10, 12, 15, 17, 26, 27, 30, 35, 37, 39, 40, 41, 49, 59, 61, 71, 84, 90, 92, 93, 94 98 97 PLL Supply Voltage. Most sensitive supply voltage. Provide a very quiet noise free voltage. Digital Output Supply Voltage. Decouple judiciously to avoid propagation of switching noise. Ground. Returns for all power supplies. Connect ground pins to a solid ground plane. Voltage Reference Input. Common reference input to RGB converters. Connect to VREFOUT, if internal reference is used. Voltage Reference Output. Internal band-gap reference output. Tie to ground through a 0.1µF capacitor. Pin No. Pin Function Description VREFIN VREFOUT Addressable Memory Register Map Name PLLN11-4 PLLN3-0 Address 00 01 Function PLL divide ratio, MSBs. PLLN + 1 = total number of pixels per horizontal line. PLL divide ratio, LSBs. PLLN + 1 = total number of pixels per horizontal line. PLLN3-0 stored in the four upper register bits 7-4. PLLN3–0 GR7-0 GG7-0 GB7-0 OSR5-0 02 03 04 05 XXXX 80 80 80 80 Default (hex) 69 (1693) D0 (1693) Gain, red channel. Adjustable from 70 to 140%. Gain, green channel. Adjustable from 70 to 140%. Gain, blue channel. Adjustable from 70 to 140%. Offset, red channel. OSR5-0 stored in the six upper register bits 7-2.Default value is decimal 32. OSR5–0 XX OSG5-0 06 Offset, green channel. OSR5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSG5–0 XX 80 OSB5-0 07 Offset, blue channel. OSR5-0 stored in the six upper register bits 7-2. Default value is decimal 32. OSB5–0 XX 80 CD7-0 CW7-0 CONFIG 1 PHASE7-0 08 09 0A 0B Clamp delay. Delay in pixels from trailing edge of horizontal sync. Clamp width. Width of clamp pulse in pixels. Configuration Register No. 1 Sampling clock phase. PHASE4-0 stored in upper register bits 7-3. PHASE sets the sampling clock phase in 11.25° increments. Default value is decimal 16. PHASE4–0 XXX 80 80 F4 10 5 REV. 1.5 11/10/00 PRODUCT SPECIFICATION FMS9874 Name PLLCTRL CONFIG 2 Address 0C 0D 0E 0F Function PLL Control Configuration Register No. 2 Reserved Reserved Default (hex) 24 00 0X 00 Register Definitions Configuration Register 1 (0A) Bit no. 0 1 XCKSEL R/W External Clock Select. Select internal clock source. 0: Internal PLL 1: XCK input. External Clamp Polarity. Select clamp polarity. 0: Active L. 1: Active H. External Clamp Select. Select clamp source. 0: Internally generated by PLL referenced to HSIN. 1: External CLAMP input. Coast Polarity. Select COAST input polarity. 0: Active L. 1: Active H. HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected edge: 0: Falling edge. 1: Rising edge. 0: Default must be 0. 0: Default must be 0. Name Type Description 2 XCLAMPOL R/W 3 XCLAMP R/W 4 COASTPOL R/W 5 HSPOL R/W 6 7 — — R/W R/W PLL Configuration Register (0C) Bit no. 1-0 4-2 Name — IPUMP2-0 R/W Charge Pump Current. Selects Charge Pump current (µA). (see Table 5. Charge Pump Current Codes) 000: 50 001: 100 010: 150 011: 250 100: 350 101: 500 110: 750 111: 1500 VCO Frequency Range. Selects VCO frequency range (MHz). 00: 20–90 01: 20–90 10: 80–108 11: — Reserved. 0: Run. 1: (reserved). REV. 1.5 11/10/00 Type Description 6-5 FVCO1-0 R/W 7 — R/W 6 FMS9874 PRODUCT SPECIFICATION Configuration Register 2 (0D) Bit no. 0 3-1 4 Name — REV OUTPHASE Type — R W Description Reserved. Set to 0. Revision Number. Die revision number. Output Data Phase. In the alternate pixel mode, selects either odd (1, 3, 5, …) or even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted from output data ports. 0: Even samples 1: Odd samples Reserved. Set to 00. 7-5 - R/W Functional Description There are two major sections within the FMS9874 Digitizer: 1. 2. Analog-to-digital Converter Channels, one for each channel, RGB and the voltage reference. Timing and Control comprising the PLL, Timing Generator, Sync Stripper and Serial Interface. Clamps If the incoming signals are not ground referenced, a clamp must be used to set the incoming video range relative to ground. Prior to each A/D converter, each channel includes a clamp that allows a capacitively coupled input to be referenced to the A/D converter bottom reference voltage when the clamp pulse is active. Source of the clamp signal is determined by the XCLAMP bit. Internal clamp timing is generated by the Timing and Control Block. Position and width of the internal clamp pulse, ICLAMP are programmable through registers CD and CW. External clamp input is selected by register bit XCLAMP and the external clamp polarity selected through register bit XCLAMPOL. To disable the clamp for DC coupled inputs, set XCLAMP = 1 with either of these conditions: 1. 2. XCLAMPOL = 0 with input CLAMP = H. XCLAMPOL = 1 with input CLAMP = L. A/D Converter Channels Each of the three RGB channels consists of: 1. 2. 3. A clamp to set the lower reference level of an AC coupled input. Gain and offset stages to tune the converter to input signal levels. An Analog-to-Digital Converter to digitize the analog input. Analog Inputs Input signal range is 500 to 1000mV to support conversion of single-ended signals with a typical amplitude of 700mV p-p. With the clamp active, each input accommodates a negative 300mV excursion. Inputs are optimized for a source resistance of 37.5 to 75Ω. To reduce noise sensitivity, the ultra-wide 500MHz input bandwidth may be reduced by adding a small series inductor prior to the 75Ω terminating resistor. See Applications Section. Best performance will be achieved with the clamp set active for most of the black signal level interval between the trailing edge of horizontal sync and the start of active video. Insufficient clamping can cause brightness changes at the top of the image and slow recovery from large changes in Average Picture Level (APL). Recommended value of CD is 0x10 to 0x20 for most standard video sources. Analog-to-Digital Converter Figure 2 is a block diagram of the ADC core with gain and offset functions. G7-0, OS5-0, RGBIN and PD7-0 generically refer to the gain and offset register values, analog input and parallel data output of any RGB channel. REV. 1.5 11/10/00 7 PRODUCT SPECIFICATION FMS9874 VREF G7-0 Gain Register D/A IBIAS + IOFFSET Offset Register OS5-0 Current D/A RGBIN VOS RLEVEL + Track & Hold - A/D Core A/D PD7-0 SCK Figure 2. A/D Converter Architecture Core of the ADC block is a high speed A/D encoder with differential inputs. Within the A/D converter core are the following elements: 1. 2. Differential track and hold. Differential analog-to-digital converter. Voltage offset from the common mode voltage at the inverting input of the Track and Hold is: 255 + G 7–0 500 -• • V OS = ( OS 5–0 – 31 ) • ---------------------------- • -------255 255 Setting the gain register value G7-0 (GR7-0, GG7-0, GB7-0), establishes the gain D/A converter voltage which is the A/D reference voltage. Increasing video gain reduces the contrast of the picture since the number of output codes is reduced. Conversion range is defined by the gain setting according to Table 1. Table 1. Gain Calibration D/A converter gain tracks A/D gain with 1 LSB of offset corresponding to 1LSB of gain. Increasing the offset of a video signal increases brightness of the picture. Data output from the A/D converter is: D 7–0 = S • V IN – ( OS 5–0 – 31 ) • Impact of the offset values OSR5-0, OSG5-0, and OSB5-0 is shown in Table 2. Conversion Range (mV) 500 700 1000 Table 2. Offset Calibration G7-0 0 66h FFh OS5-0 0 1Fh FFh Equivalent Offset (bits) -31d 0 32d A/D Converter sensitivity is: 255 255 • S = -------- • ---------------------------- LSB ⁄ mV -• 500 255 + G 7 – 0 Sampling Clock PHASE Adjustment Picture quality is strongly impacted by the PHASE4-0 value. If PHASE is not set correctly, any section of an image consisting of vertical lines may exhibit tearing. Figure 3 shows how an analog input, RINGINBIN is sampled by the rising edge of SCK after a delay PHASE from the rising edge of either PXCK or XCK. SCK can be delayed up to 32 steps in 11.25° increments by adjusting the register value, PHASE4-0. Output data, DCK and DCK are delayed in tandem with SCK relative to PXCK or XCK. There is a 5-61/2 clock latency between the data sample Sn and the corresponding data out DA7-0. Offset is set through the Single-Ended to Differential Amplifier which translates the ground referenced input to a differential voltage centered around A/D common mode bias voltage. The 6-bit Offset D/A converter injects a current into RLEVEL with two components: 1. 2. IBIAS to establish the A/D common mode voltage. IOFFSET to set the offset from the common mode level. 8 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION PHASE PXCK/XCK SCK VIN DCK DA Sn Figure 3. Internal Sampling Clock, SCK Timing Ideally, incoming pixels would be trapezoidal with fast risetimes and the sampling edge of the A/D clock, SCK would be positioned along the level section of the incoming pixel waveform as shown in Figure 4. There is a narrow zone of uncertainly where sampling during pixel rise time would cause an error in the value of the A/D data output, D7-0, which is shown as a value, 0-255. Zones of Uncertainty sampling clock jitter. To avoid corruption of the image, setting the value PHASE7-0 is critical. PHASE4-0 should be trimmed to position the sampling edge of SCK within the zone of serendipity. Zones of Uncertainty RIN, GIN, BIN RIN, GIN, BIN SCK SCK D7-0 D7-0 Figure 6. Improper Pixel Sampling Voltage References Figure 4. Ideal Pixel Sampling In practice, high-resolution pixels have long rise-times. As shown in Figure 5, there are narrow zones of serendipity when the pixel amplitude is level. Samples are valid in these zones. Zones of Serendipity An on-chip voltage reference is generated from a bandgap source. VREFOUT is the buffered output of this source that can be connected to VREFIN to supply a voltage reference that is common to the three converter channels. VREFIN, with a nominal voltage of 1.25V, is the source of the differential reference voltages for each A/D converter. Reference voltages supplied to the differential inputs of the comparators in the A/D converters are derived from VREFIN. RIN, GIN, BIN SCK Digital Data Outputs Input horizontal sync HSIN and outgoing data, D[7..0] are resynchronized to the delayed sample clock, SCK. Output timing characteristics are defined in Figure 4. Latency of the first pixel, N varies according to the mode: 1. Normal. Alternate pixel sampling. D7-0 Figure 5. Acceptable Pixel Sampling 2. Referring to Figure 6, when the sample clock, SCK has some jitter, if the sampling edge occurs anywhere within the zone of uncertainty where the pixel rise time is steep, there will be amplitude modulation of the digitized data, D7-0, due to the REV. 1.5 11/10/00 Levels are 3.3 volt CMOS with the output supply variable between 2.5 and 3.3 V. PWRDN = L sets the outputs high-impedance. PWRDN = H enables the outputs. 9 PRODUCT SPECIFICATION FMS9874 HSIN PHASE N PXCK/XCK SCK RGBIN DCK tDH DCK tDO D[7..0] D0 S0 HSOUT Figure 7. Output Timing Figures 8 through 10 depict data output timing relative to the sampling clock and inputs for all modes. Timing is referenced to the leading edge of HSIN when the first sample is taken at the rising edge of SCK. Register bit OUTPHASE, determines if odd or even samples are directed to the data ports. Note the timing of the HSOUT waveform: 1. 2. 3. HSOUT is always active HIGH. Only the leading edge of HSOUT is active or selected by the HSPOL register bit. HSOUT is aligned with DCK. RGBIN HSIN PXCK HS 5 PIPE DELAY SCK DATACK D7-0 HSOUT D0 P0 P1 P2 P3 P4 P5 P6 4. 5. Trailing edge is linked to HSIN. If MSIN does not terminate before mid-line, HSOUT is forced low. A 50% duty cycle indicates that HSPOL is incorrectly set. HS is the internal sync pulse generated from HSYNC. SCK is the internal A/D converter sampling clock. Output data transitions are synchronized with the falling edge of DCK. Output data should be strobed on the rising edge of DCK. A 5 to 5.5 clock cycle delay must be flushed before valid data is available. P7 D1 D2 D3 D4 D5 D6 D7 Figure 8. Normal Mode 10 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION RGBIN HSIN PXCK HS P0 P1 P2 P3 P4 P5 P6 P7 5.5 PIPE DELAY SCK DATACK D7-0 HSOUT D1 D3 D5 D7 Figure 9. Alternate Pixel Sampling Mode, (Even Pixels) RGBIN HSIN PXCK HS SCK DATACK D7-0 HSOUT P0 P1 P2 P3 P4 P5 P6 P7 5 PIPE DELAY D0 D2 D4 D6 Figure 10. Alternate Pixel Sampling Mode, (Odd Pixels) Alternate Pixel Sampling Mode A logic H on the CKINV pin inverts the sampling phase of SCK. In the Alternate Pixel Sampling Mode: 1. 2. The PLL is run at half rate. SCK, DCK and DCK are half rate. CKINV is toggled between frames. O O O O O O O O O O O E E E E E E E E E E E O O O O O O O O O O O E E E E E E E E E E E O O O O O O O O O O O E E E E E E E E E E E O O O O O O O O O O O E E E E E E E E E E E O O O O O O O O O O O E E E E E E E E E E E O O O O O O O O O O O E E E E E E E E E E E On one frame, even pixels are sampled. On the other, odd pixels are sampled. Alternate Pixel Sampling is similar to interlacing used in broadcast video, except that the columns of pixels are interlaced instead of lines. O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 O1 E1 O1E1 O1 E1O1E1O1E1O1E1O1E1 Figure 12. Odd Pixels from Frame 1 Figure 11. Odd and Even Pixels in a Frame REV. 1.5 11/10/00 11 PRODUCT SPECIFICATION FMS9874 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1E2 O1E2 O1E2 O1E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 Figure 13. Even Pixels from Frame 2 Figure 14. Subsequent Output Combining Frames 2 and 3 Figure 15. Combined Frames 2 and 3 Timing and Control Timing and Control logic encompasses the PLL, Timing Generator and Sync Stripper. The PLL consists of a phase comparator, charge pump VCO and ÷N counter, with the charge pump connected through the LPF pin to an external filter. These elements must be programmed to match the incoming video source to be captured. Values of IPUMP and FVCO for Standard VESA timing parameters are shown in Table 3. Timing of many computer video outputs does not comply with VESA recommendations. PLLN should be optimized to avoid vertical noise bars on the displayed image. Modes marked 2X are 2X-oversampled modes where the number of samples per horizontal line is doubled. To select this mode, the Phase-locked Loop Divide Ratio value must changed from PLL1x to: PLL 2x = 2 • ( PLL 1x + 1 ) – 1 Phase Locked Loop Two clock types originate in the PLL: 1. 2. Data clocks DCK and DCK. Internal sampling clock SCK. DCK and DCK are used to strobe data from the FMS9874 to following digital circuits. SCK is the ADC sample clock which has adjustable phase controlled through the PHASE register. DCK and DCK are phase aligned with SCK. Reference for the PLL is the horizontal sync input, HSIN with polarity selected by the HSPOL bit. Frequency of the HSIN input is multiplied by the value PLLN + 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN + 1 should equal the number of pixels per horizontal line including active and blanked sections. Typically blanking is 20–30% of active pixels. Divide ratios from 2–4095 are supported. SCK, DCK and DCK run at a rate PLLN + 1 times the HSIN frequency. Values of IPUMP and FVCO are set through the PLL Configuration Register (0x0C). Recommended external filter components are shown in Figure 16. RF quality ±10% ceramic capacitors with X7R dielectric are recommended. Table 3. Recommended IPUMP and FVCO values for Standard Display Formats1 Standard VGA Resolution 640 X 480 Refresh Rate 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 67 Hz 72 Hz 75 Hz 70 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz Horizontal Frequency 31.5 kHz 37.7 kHz 37.5 kHz 43.3 kHz 31.5 kHz 35 kHz 37.7 kHz 37.5 kHz 31.5 kHz 35.1 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz Sample Rate 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 50 MHz 62.5 MHz 63 MHz 63 MHz 56.6 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 56.250 MHz FVCO1-0 01 01 01 01 01 01 01 01 01 01 01 01 01 01 IPUMP2-0 100 100 100 100 100 100 100 100 100 111 111 111 111 2X 640 X 480 720 X 400 SVGA 800 X 600 12 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Table 3. Recommended IPUMP and FVCO values for Standard Display Formats1 (continued) Standard XGA Resolution 1024 X 768 Refresh Rate 60 Hz 70 Hz 75 Hz 80 Hz 85 Hz 60 Hz Horizontal Frequency 48.4 kHz 56.5 kHz 60.0 kHz 64.0 kHz 68.3 kHz 64.0 kHz Sample Rate 65.000 MHz 75.000 MHz 78.750 MHz 85.500 MHz 94.500 MHz 108.000 MHz FVCO1-0 01 01 10 IPUMP2-0 111 111 111 SXGA 1280 X 1024 10 111 Notes: 1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others. VDDP C1 0.18µF R1 1.5K C2 0.018µF COAST = H disables PLL lock to HSIN, while the VCO frequency is retained. VCO frequency remains stable over several lines without updates from HSIN. COAST can be connected directly to the vertical sync signal or supplied by the graphics controller. RMS Clock jitter is less than 3% of pixel period in all operating modes. At lower frequencies below 40MHz, the jitter rises but can be reduced by over-sampling at a 2X clock rate. See Performance section for jitter specifications and plots. LPF Figure 16. Schematic, PLL Filter. Loop performance is established by setting: COAST 1. 2. 3. VCO frequency range through FVCO1-0. (see Table 4) Charge Pump Current through IPUMP2-0. (see Table 5) External loop filter component values. COAST = H disables PLL lock to HSIN, while the VCO frequency is retained. VCO frequency remains stable over several lines without updates from HSIN. COAST can be connected directly to the vertical sync signal or supplied by the graphics controller. Operation of COAST is depicted in Figure 17. HSOUT polarity is always positive. When COAST = L, HSOUT tracks HSIN (shown with postive polarity in Figure 1 ): 1. 2. HSOUT rising edge tracks HSIN delayed by a few pixels. HSOUT falling edge tracks the trailing edge of HSIN with no delay. Table 4. VCO Frequency Bands FVCO2-0 Frequency Range (MHz) KVCO (MHz/V) 00 01 10 11 20–90 75–108 — 60 90 — Table 5. Charge Pump Current Levels IPUMP2-0 000 001 010 011 100 101 110 111 Current (µA) 50 100 150 250 350 500 750 1500 When COAST = H, the PLL flywheels, disregarding the incoming HSIN references, while the HSOUT waveform depends upon the state of HSIN. 1. If HSIN = H: a.) HSOUT rising edge remains locked to the PLL. b.) HSOUT trailing edge falls after 50% of the HSOUT period has expired. 2. HSIN transitions: a.) HSOUT rising edge remains locked to the PLL. b.) HSOUT falling edge is terminated by the trailing edge of HSIN. 3. If HSIN = L, then HSOUT = L Setting SPHASE4-0 selects the sampling phase of SCK relative to PXCK in 32 steps of 11.25°. Phase of the output data, DCK and DCK is slaved to the SCK phase. REV. 1.5 11/10/00 13 PRODUCT SPECIFICATION FMS9874 HSIN Trailing edge terminates HSOUT COAST HSOUT 50% Timeout Figure 17. Timing Generator Timing and Control logic generates: 1. 2. 3. 4. Internal sampling clock, SCK. Output data clocks, DCK and DCK. Output horizontal sync, HSOUT. Internal clamp pulse, ICLAMP. Serial Interface Register access is via a 2-wire I2C/SMBus compatible interface. As a slave device, the 7-bit address is selected by the A1-0 pins (see Table 6). Serial port pins SDA and SCL communicate with the host SMBus/I2C controller which act as a master. Since the serial control port is design to interface with 3.3V logic, the pins must be protected by series connected 150Ω resistors if SDA and SCL signals originate from 5V logic. (See Applications Section) Table 6. Serial Interface Address Codes With HSPOL set correctly, ICLAMP delay follows the trailing edge of horizontal sync in (HSIN). Delay is set by the CD register. Width of ICLAMP is set by the CW register. Range of CD and CW values is 1–255 pixels. Sync Stripper Some video signals include embedded composite sync rather than separate horizontal and vertical sync signals, typically sync on green. Composite sync is extracted from Composite Video at the ACSIN pin. When the ACSIN signal falls below a 150mV ground referenced threshold, sync is detected. Composite Sync Output, DCSOUT reflects the ACSIN sync timing with non-inverted CMOS digital levels. A1-0 00 01 10 11 7-Bit Address 4C 4D 4E 4F Two signals comprise the bus: clock (SCL) and bi-directional data (SDA). When receiving and transmitting data through the serial interface, the FMS9874 acts as a slave, responding only to commands by the I2C/SMBus master. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA may change only when SCL = L. An SDA transition while SCL = H is interpreted as a start or stop signal. Power Down PWRDN = L minimizes FMS9874 power consumption. Data outputs become high impedance. Clocks generation is stopped. Register contents are maintained. Sync stripping and the internal voltage reference function. 14 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION SDA tBUFF tSTAH SCL tDAH tDHO tDAL tDSU tSTASU tSTOSU Figure 18. Serial Bus: Read/Write Timing SDA bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ACK SCL Figure 19. SerialBus: Typical Byte Transfer SDA A6 A5 A4 A3 A2 A1 A0 R/W\ ACK SCL Figure 20. Serial Bus: Slave Address with Read/Write Bit There are five steps within an I2C/SMBus cycle: 1. 2. 3. 4. 5. Start signal Slave address byte Pointer register address byte Data byte to read or write Stop signal Data Transfer via Serial Interface If a slave device, such as the FMS9874 does not acknowledge the master device during a write sequence, SDA remains HIGH so the master can generate a stop signal. During a read sequence, if the master device does not acknowledge by bringing SDA = L, the FMS9874 interprets SDA = H as “end of data.” SDA remains HIGH so the master can generate a stop signal. To write data to a specific FMS9874 control register, three bytes are sent: 1. 2. 3. Write the slave address byte with bit R/W = L. Write the pointer byte. Write to the control register indexed by the pointer. When the Serial Bus interface is inactive, SCL = H and SDA = H. Communications are initiated by sending a start signal (Figure 14, left waveform) that is a HIGH-to-LOW transition on SDA while SCL is HIGH. A start signal alerts all slaved devices that a data transfer sequence is imminent. After a start signal, the first eight bits of data comprise a seven bit slave address followed a single R/W bit (Read = H, Write = L) to set the direction of data transfer: read from; or write to the slave device. If the transmitted slave address matches the address of the FMS9874 which set by the state of the ADD pin, the FMS9874 acknowledges by pulling SDA LOW on the 9th SCL pulse (see Figure 16). If the addresses do not match, the FMS9874 does not acknowledge. For each byte of data read or written, the MSB is the first bit of the sequence. After each byte is written, the pointer auto-increments to allow multiple data byte transfers within one write cycle. Data is read from the control registers of the FMS9874 in a similar manner, except that two data transfer operations are required: 1. 2. 3. 4. Write the slave address byte with bit R/W = L. Write the pointer byte. Write the slave address byte with bit R/W = H Read the control register indexed by the pointer. REV. 1.5 11/10/00 15 PRODUCT SPECIFICATION FMS9874 After each byte is read, the pointer auto-increments to allow multiple data byte transfers within one read cycle. Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop cycle. After the last read, there must be a stop cycle comprising a LOW-to-HIGH transition of SDA while SCL is HIGH. (see Figure 18, right waveform) A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. Read from one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Stop signal Read from four registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte (= base address) 4. Stop signal (optional) 5. Start signal 6. Slave Address byte (R/W bit = HIGH) 7. Data byte from base address 8. Data byte from (base address + 1) 9. Data byte from (base address + 2) 10. Data byte from (base address + 3) 11. Stop signal Serial Interface Read/Write Examples Examples below show how serial bus cycles can be linked together for multiple register read and write access cycles. For sequential register accesses, each ACK handshake initiates further SCL clock cycles from the master to transfer the next data byte. Write to one register 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Stop signal Write to four consecutive registers 1. Start signal 2. Slave Address byte (R/W bit = LOW) 3. Pointer byte 4. Data byte to base address 5. Data byte to (base address + 1) 6. Data byte to (base address + 2) 7. Data byte to (base address + 3) 8. Stop signal 16 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Absolute Maximum Ratings Parameter Power Supply Voltages VCC (Measured to GND) Digital Inputs Applied voltage (Measured to GND)2 Forced current Analog Inputs Applied Voltage (Measured to GND)2 Forced current 3, 4 3, 4 (beyond which the device may be damaged)1 Min -0.5 -0.3 -5.0 -0.5 -10.0 -0.5 -6.0 -8.0 6.0 8.0 1 150 300 220 -65 150 ±150 Typ Max 4 VDDA 5.0 VDDA 10.0 Unit V V mA V mA V mA mA second °C °C °C °C V Digital Outputs Applied voltage (Measured to GND)2 Forced current Forced current Temperature Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage Electrostatic Discharge5 3, 4 3, 4 Short circuit duration (single output in HIGH state to ground) Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Parameter VDDA VDDP VDDO TA ADC Power Supply Voltage PLL Power Supply Voltage Output Power Supply Voltage Ambient Temperature, Still Air A/D analog input range, min. A/D analog input range, max. 1000 Min 3.0 3.0 2.2 0 Nom 3.3 3.3 3.3 Max 3.6 3.6 3.6 70 500 Units V V V °C mV p-p mV p-p REV. 1.5 11/10/00 17 PRODUCT SPECIFICATION FMS9874 Electrical Characteristics1 Parameter Power Supply Currents IDDA IDDD IDDP PD IPD PDD CI IIH IIL VIH VIL IOHD IOHC IOLD IOLC VOH VOL VSMIH VSMIL VSMOL ISMOH ISMOL IB EOS Supply current, ADC Supply current2, Digital Output Supply current, PLL Power dissipation Power-down current Powered-down disspation Input Capacitance Input Current, HIGH Input Current, LOW Input Voltage, HIGH Input Voltage, LOW Output Current, HIGH, data Output Current, HIGH, clock Output Current, LOW, data Output Current, LOW, clock Output Voltage, HIGH Output Voltage, LOW (VDD3) Input Voltage, HIGH Input Voltage, LOW Output Voltage, LOW Output Current, HIGH Output Current, HIGH Input bias current Input Offset Voltage Output Voltage Temperature Coefficient Notes: 1. Unless otherwise stated, 0 to 70°C 2. DCK, DCK load = 15 pF; data load = 5 pF. Conditions Operating, 25°C Operating, 25°C Operating, 25°C 0 to 70°C 0 to 70°C 0 to 70°C 25°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C IOH = max., 0 to 70°C IOL = max., 0 to 70°C 0 to 70°C 0 to 70°C ISMOL = max. 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C Min Typ 211 47 30 800 23 10 3 Max Unit mA mA mA mW mA mW pF µA Digital Inputs/Outputs -1 +1 2.5 0.8 4 8 4 8 VDDO–0.1 0.1 2.5 0.8 0.1 µA V V mA mA mA mA V V V V V µA mA Serial Bus I/O Analog Inputs 1 7 1.20 50 µA mV V ppm/°C Reference Output 1.25 1.30 ±50 18 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Switching Characteristics Parameter Analog-to-Digital Converters Conversion rate tSKEW Data to clock skew HSIN input frequency Maximum PLL clock rate Minimum PLL clock rate PLL Jitter1 Sampling phase tempco Serial Bus Interface tDAL tDAH tSTAH tSTASU tSTOSU tBUFF tDSU tDHO Notes: 1. FVCO = 10, IPUMP = 110, PLLN = 137510. Conditions 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 25°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C Min. 10 -0.5 15 108 Typ. Max. 108 2.0 110 20 Unit Ms/s ns kHz MHz MHz µs p-p ps/°C µs µs µs µs µs µs ns ns Timing Generator 1.8 15 4.7 4.0 4.0 4.7 4.0 4.7 250 0 SCL Pulse Width, LOW SCL Pulse Width, HIGH SDA Start Hold Time SCL to SDA Setup Time (Stop) SCL to SDA Setup Time (Start) SDA Stop Hold Time Setup SDA to SCL Data Setup Time SDA to SCL Data Hold Time System Performace Characteristics Parameter Analog to Digital Converter ELI ELD Integral Linearity Error Differential Linearity Error Missing Codes Input full scale matching Offset adjustment range Gain tempco BW tOV SNR Analog bandwidth, full power Transient response Over-voltage recovery time SNR without harmonics 25°C 0 to 70°C 25°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C 25°C 25°C 25°C 25°C 5 25 280 500 2 1.5 45 -1.4 -2.5 -1.0 -1.0 ±0.5 ±0.8 1.4 2.5 1.15 1.25 0 %FS %FS ppm/°C MHz ns ns dB LSB LSB LSB LSB Conditions Min Typ1 Max Unit REV. 1.5 11/10/00 19 PRODUCT SPECIFICATION FMS9874 System Performace Characteristics (continued) Parameter Phase Locked Loop tPP Peak-to-peak PLL Jitter @ MHz 25.175 31.5 36 40 49.5 56.25 66 78.75 108 tRMS RMS PLL Jitter @ MHz 25.175 31.5 36 40 49.5 56.25 66 78.75 108 Thermal θJC θJA Resistance, junction-to-case Resistance, junction-to-ambient 44 °C/W °C/W 25°C 25°C 7.1 6.9 6.5 4.6 2.8 2.4 2.2 2.1 1.8 900 700 600 600 400 300 300 250 250 ps ns Conditions Min Typ1 Max Unit Notes: 1. External pixel clock. 8.0 7.0 6.0 5.0 Jitter (ns) 4.0 3.0 2.0 1.0 0.0 0 20 40 60 Pixel Clock (MHz) 80 100 120 RMS P-P Figure 21. Pixel Clock Jitter vs. Frequency 20 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Applications Information To minimize component count, use of the following on-chip circuits is recommended: 1. 2. 3. ADC sampling clock. Clamp. Voltage reference AC Coupled Digitizer Shown in Figure 22 is an implementation of a video digitizer with AC coupled RGB inputs. Horizontal sync input, HS is passed through a voltage divider which attenuates the 5.0 V logic HIGH excursion to the 3.3 V HIGH input level of the FMS9874. Vertical sync is also attenuated to make the VSOUT level compatible with 3.3 V pixel processing following the FMS9874. Output data is three channel 24-bit pixels with a maximum rate of 140Ms/s. Data is clocked out on the negative edge of DCK. HSOUT defines the active video along a line, while incoming vertical sync, VSIN is propagated as VSOUT to the output data to synchronize handling of digitized frames of output data. Control is through the serial port with 150Ω resistors inserted to allow interfacing with 5V logic. If the serial bus is operates with 3.3V levels, these resistors are unnecessary. Optimum PLL Configuration Register (address 0x0C) settings for typical graphics modes are listed in Table 3. Unless otherwise indicated, all modes are compliant with VESA specifications. For unlisted modes, values should be adjusted to optimize performance. By adjusting the values in the gain (GR, GG, GB) and offset (OSR, OSG, OSB) registers, the input conversion range can be matched to the incoming analog signals. C1 .047µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RED GREEN BLUE C2 .047µF VDDA VDDP VDDO R1 75 24 25 31 36 38 2 8 3 5 9 11 14 16 95 99 100 VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA U1 FMS9874 VDDP VDDP VDDP VDDP VDDP RIN GIN BIN VDDO VDDO VDDO VDDO VDDO VDDO C3 .047µF R3 75 50 60 62 72 85 91 R2 75 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DG7 DG6 DG5 DG4 DG3 DG2 DG1 DG0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DCK 51 52 53 54 55 56 57 58 63 64 65 66 67 68 69 70 76 77 78 79 80 81 82 83 86 87 88 89 34 42 43 44 45 46 47 48 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 GA7 GA6 GA5 GA4 GA3 GA2 GA1 GA0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 BA[7..0] GA[7..0] VDDP R4 1K 13 18 19 INVSCK CLAMP HSIN COAST XCK LPF SDA SCL A0 A1 C1 0.18µF R1 1.5K C4 0.018µF R5 1.8K 28 29 32 33 RA[7..0] SCL SDA COAST VDD 20 21 22 23 7 R7 10K 73 74 75 98 96 97 DCK DCK HSOUT DCK HSOUT ACSIN DCSOUT NC9 NC10 NC11 VREFIN PWRDN VREFOUT NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 1 4 6 10 12 15 17 26 27 30 35 37 39 40 41 49 59 61 71 84 90 92 93 94 C8 0.1µF GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSOUT Figure 22. Schematic, VGA Digitizer, AC Coupled RGB REV. 1.5 11/10/00 21 PRODUCT SPECIFICATION FMS9874 Printed Wiring Board Design Guidelines Recommended strategy is to mount the FMS9874 over a ground plane with carefully routed analog inputs and digital outputs. All connections should be treated as transmission lines to ensure that reflections due to mismatches are minimized and ground return currents do not interfere with critical signals. Analog Inputs Recommendations: 1. 2. Keep analog trace lengths short to minimize crosstalk. Terminate analog inputs with 75Ω resistors, placed close to the FMS9874 analog inputs, RIN, GIN and BIN. By matching transmission line impedances, reflections will be minimized. Layout traces as 75Ω transmission lines. Avoid running analog traces near digital traces. Due to the wide input bandwidth (500MHz) digital noise can easily leak into analog inputs. If necessary, limit bandwidth by adding a ferrite bead in series with each RGB input as shown in Figure 23. A Fair-Rite #2508051217Z0 is recommended. Further bandwidth reduction using a shunt 10pF capacitor may reduce snow (intensity noise) caused by HF noise riding on the RGB input. Mismatches, reflections and noise may cause ringing or distortion of the incoming video signals. Locate the PLL filter clear of other signals. Bypass the reference with a 0.1µF capacitor to ground. L1 BEAD R, G, B INPUT R1 75 C1 47nF RIN, GIN, BIN C2 10pF Digital I/O Recommendations: 1. 2. 3. 4. 5. 6. 7. Route digital I/O signals clear of analog inputs. Terminate clock lines to reduce reflections. Treat clock lines as transmission lines. Scale the HSIN input to 3.3V, using a resistor network or a series 1 kΩ resistor. Limit Serial Port inputs SDA and SDL with 150Ω resistors connected directly to the pins. If necessary terminate the HSIN input with 330/220Ω. If necessary, to reduce reflections, EMI or spikes add a 50–200Ω resistor at each data output pin. To minimize noise within the FMS9884A, restrict the capacitive load at the digital outputs to < 10pF. 3. 4. Power and Ground A schematic of the recommended power distribution is shown in Figure 24. Note that: 1. 2. 3. 4. 5. Analog and digital circuits are layed out over a common solid ground plane. Each FMS9874 pin is decoupled with a 0.1µF capacitor. A group of pins may be de-coupled through a common capacitor if no pin is more than 5 mm from the capacitor. A separate regulated supply is used for the phase-locked loop power supply, VDDP. Capacitors are attached to each PLL pin or pin-pair. 5. 6. 7. Figure 23. RGB Input Filter Option 22 REV. 1.5 11/10/00 FMS9874 PRODUCT SPECIFICATION Pins 33, 34 C2 0.01µF VPLL L1 BEAD U3 RC1117-3.3 2 OUT 4 OUT IN ADJ/GND 1 3 C1 0.1µF Pin 43 C3 0.1µF Pin 48 C4 0.01µF U2 RC1117-3.3 2 OUT 4 OUT IN ADJ/GND 1 L2 BEAD 3 C7 0.1µF Power Input + C8 10µF Pin 50 C5 0.1µF + C6 10 µF VADC Pins C10 C11 C12 C13 C14 C15 C16 C17 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF + C26 10µF U3 RC1117-3.3 2 OUT 3 ADJ/GND IN 4 OUT + C25 10µF 1 C9 0.1µF VDD Pins C18 C19 C20 C21 C22 C23 C24 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF L3 BEAD Figure 24. Recommended Power Distribution Physical placement of PLL power supply decoupling components is critical. Bearing in mind the following suggestions: 1. 2. 3. All components should be placed in close proximity to the FMS9874 pins. Routing through vias should be avoided, if possible. Each VDDP/GND pin pair: 24&25/26, 31/30, 36/35, and 38/37 should be decoupled with a 100–1000p/10µF pair of capacitors (see Figure 24). If board space is limited, use as many capacitor pairs as possible. Use Fair-rite 274 301 9447 bead. 4. 2. If PLLN + 1 does not equal the number of pixels, there will be irregular intensities on text and an interference pattern on a vertical grill pattern. Calibrate Offset and Gain by first setting each input to 0mV. Then adjust OSR, OSG, and OSB to set each RGB data output D7-0 = 0x00. Next with 700mV input, adjust GR, GG and GB so that each RGB data output D7-0 = (same value), typically 240 decimal. Clamp registers, CD and CW, should be programmed to maximize the period of the clamp during the backporch, while not encroaching into the sync or active video periods. PHASE must be trimmed to minimize onscreen snow (intensity noise) when a vertical grill pattern is displayed. FVCO must be set to encompass the incoming frequency range. IPUMP must be set to minimize intensity noise. 3. 4. Firmware Best performance can be achieved by correctly setting the FMS9874 registers. Here are some recommendations: 1. Set the value of PLLN equal to the number of pixels to be sampled minus one. With this setting, the number of samples per horizontal line equals the number of pixels. 5. 6. REV. 1.5 11/10/00 23 PRODUCT SPECIFICATION FMS9874 Mechanical Dimensions 100-Lead MQFP (KG) Package Symbol Min. A A1 A2 D D1 D2 L N e b — — 2.62 Millimeters Typ. 2.82 0.15 Max 3.00 — 2.77 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1994. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254mm per side. 3. "N" is the number of terminals, 25 per side. 3, 5 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm in excess of the "b" dimension at the maximum material condition. 2.67 17.20 BSC 14.00 BSC 12.00 BSC 0.73 0.88 100 0.50 BSC — 1.03 4 0.17 0.27 .40 Min. 0° Min. 0.13 R Min. Datum Plane e .13/.30 R D2 D1/2 D 1.60 Ref. Lead Detail L 0–7° A2 A A1 B Seating Plane See Lead Detail Base Plane -CLEAD COPLANARITY ccc C 24 REV. 1.5 11/10/00 PRODUCT SPECIFICATION FMS9874 Ordering Information Product Number FMS9874KGC100 Temperature Range 0°C to 70°C Screening Commercial Package 100 Lead MQFP Package Marking 9874KGC100 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 11/10/00 0.0m 003 Stock#DS30009874  2000 Fairchild Semiconductor Corporation