FQA12P20

FQA12P20 May 2000 QFET FQA12P20 200V P-Channel MOSFET General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters. TM Features • • • • • • -12.6A, -200V, RDS(on) = 0.47Ω @VGS = -10 V Low gate charge ( typical 31 nC) Low Crss ( typical 30 pF) Fast switching 100% avalanche tested Improved dv/dt capability S ! ● ● G! ▶▲ ● G DS TO-3P FQA Series ! D Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FQA12P20 -200 -12.6 -7.9 -50.4 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) 810 -12.6 15 -5.5 150 1.2 -55 to +150 300 - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Thermal Resistance, Junction-to-Ambient Typ -0.24 -Max 0.83 -40 Units °C/W °C/W °C/W ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Elerical Characteristics Symbol Parameter TC = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = -250 µA ID = -250 µA, Referenced to 25°C VDS = -200 V, VGS = 0 V VDS = -160 V, TC = 125°C VGS = -30 V, VDS = 0 V VGS = 30 V, VDS = 0 V -200 -------------1 -10 -100 100 V V/°C µA µA nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = -250 µA VGS = -10 V, ID = -6.3 A VDS = -40 V, ID = -6.3 A (Note 4) -3.0 --- -0.36 6.6 -5.0 0.47 -- V Ω S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = -25 V, VGS = 0 V, f = 1.0 MHz ---920 190 30 1200 250 40 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = -100 V, ID = -11.5 A, RG = 25 Ω (Note 4, 5) -------- 20 195 40 60 31 8.1 16 50 400 90 130 40 --- ns ns ns ns nC nC nC VDS = -160 V, ID = -11.5 A, VGS = -10 V (Note 4, 5) Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = -12.6 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = -11.5 A, dIF / dt = 100 A/µs (Note 4) ------ ---180 1.44 -12.6 -50.4 -5.0 --- A A V ns µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 7.65mH, IAS = -12.6A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ -11.5A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Typical Characteristics 10 1 -I D , Drain Current [A] -I D, Drain Current [A] VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V Top : 10 1 150℃ 10 0 10 0 25℃ -55℃ -1 ※ Notes : 1. 250μ Pulse Test s 2. TC = 25℃ ※ Notes : 1. VDS = -40V 2. 250μ Pulse Test s 10 -1 10 -1 10 0 10 1 10 2 4 6 8 10 -VDS, Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 2.0 RDS(on) [ Ω ], Drain-Source On-Resistance VGS = - 10V -I DR , Reverse Drain Current [A] 1.5 10 1 VGS = - 20V 1.0 10 0 0.5 ※ Note : TJ = 25℃ 150℃ -1 25℃ ※ Notes : 1. VGS = 0V 2. 250μ Pulse Test s 0.0 0 10 20 30 40 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -ID , Drain Current [A] -VSD , Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 2400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = -40V 10 2000 VDS = -100V VDS = -160V -V GS , Gate-Source Voltage [V] 1600 8 Capacitance [pF] Ciss 1200 Coss ※ Notes : 1. VGS = 0 V 2. f = 1 MHz 6 800 4 Crss 400 2 ※ Note : ID = -11.5 A 0 -1 10 0 10 0 10 1 0 5 10 15 20 25 30 35 -VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Typical Characteristics (Continued) 1.2 2.5 -BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.0 RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 1.5 1.0 1.0 0.9 ※ Notes : 1. VGS = 0 V A 2. ID = -250 μ 0.5 ※ Notes : 1. VGS = -10 V 2. ID = -5.75 A 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 15 10 2 Operation in This Area is Limited by R DS(on) 12 100 µs -I D, Drain Current [A] 10 1 -I D, Drain Current [A] 2 1 ms 10 ms DC 9 6 10 0 ※ Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 3 10 -1 10 0 10 1 10 0 25 50 75 100 125 150 -VDS, Drain-Source Voltage [V] TC, Case Temperature [℃] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature ( t) , T h e r m a l R e s p o n s e 10 0 D = 0 .5 0 .2 10 -1 0 .1 0 .0 5 0 .0 2 0 .0 1 s in g le p u ls e ※ N o te s : 1 . Z θ J C ( t ) = 0 . 8 3 ℃ /W M a x . 2 . D u ty F a c t o r , D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C( t ) PDM t1 t2 Z θ JC 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Gate Charge Test Circuit & Waveform 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS Qg -10V Qgs Qgd VGS DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD td(on) t on tr td(off) t off tf VGS 10% -10V DUT VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD tp Time VDS (t) VDD VDD ID (t) IAS BVDSS -10V ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG Compliment of DUT (N-Channel) VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V I SD ( DUT ) Body Diode Reverse Current IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop Body Diode Recovery dv/dt VDD ©2000 Fairchild Semiconductor International Rev. B, May 2000 FQA12P20 Package Dimensions TO-3P 15.60 ±0.20 3.80 ±0.20 13.60 ±0.20 ø3.20 ±0.10 9.60 ±0.20 4.80 ±0.20 1.50 –0.05 +0.15 12.76 ±0.20 19.90 ±0.20 16.50 ±0.30 3.00 ±0.20 1.00 ±0.20 3.50 ±0.20 2.00 ±0.20 13.90 ±0.20 23.40 ±0.20 18.70 ±0.20 1.40 ±0.20 5.45TYP [5.45 ±0.30] 5.45TYP [5.45 ±0.30] 0.60 –0.05 +0.15 ©2000 Fairchild Semiconductor International Rev. B, May 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  DISCLAIMER FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. G