FQPF7N60

FQPF7N60 April 2000 QFET FQPF7N60 600V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply. TM Features • • • • • • 4.3A, 600V, RDS(on) = 1.0Ω @VGS = 10 V Low gate charge ( typical 29 nC) Low Crss ( typical 16 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! " G! GD S !" " " TO-220F FQPF Series ! S Absolute Maximum Ratings

Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) FQPF7N60 600 4.3 2.7 17.2 ±
30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) 580 4.3 4.8 4.5 48 0.38 -55 to +150 300 - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8
from case for 5 seconds Thermal Characteristics Symbol RθJC RθJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient Typ --Max 2.60 62.5 Units °CW °CW ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Electrical Characteristics




T Symbol Parameter C = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 600 V, VGS = 0 V VDS = 480 V, TC = 125°C VGS = 30 V, VDS = 0 V VGS = -30 V, VDS = 0 V 600 ------0.67 ------10 100 100 -100 V V/°C µA µA nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VGS = 10 V, ID = 2.2 A VDS = 50 V, ID = 2.2 A (Note 4) 3.0 --- -0.8 6.4 5.0 1.0 -- V Ω S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---1100 135 16 1430 175 21 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 480 V, ID = 7.4 A, VGS = 10 V (Note 4, 5) VDD = 300 V, ID = 7.4 A, RG = 25 Ω (Note 4, 5) -------- 30 80 65 60 29 7 14.5 70 170 140 130 38 --- ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 4.3 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 7.4 A, dIF / dt = 100 A/µs (Note 4) ------ ---320 2.4 4.3 17.2 1.4 --- A A V ns µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 57.6mH, IAS = 4.3A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD
7.4A, di/dt
200A/µs, VDD
BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width
300µs, Duty cycle
2% 5. Essentially independent of operating temperature ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Typical Characteristics 10 1 10 0 ID, Drain Current [A] ID, Drain Current [A] VGS 15.0 V 10.0 V 8.0 V 7.5 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V Top : 10 1 10 0 150
25
-55

Notes : 1. VDS = 50V 2. 250 Pulse Test s 10 -1
Notes : 1. 250 Pulse Test s 2. TC = 25 10 -1 10 0 10 1 10 -1 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 2.5 2.0 VGS = 10V VGS = 20V 10 1 Drain-Source On-Resistance 1.5 1.0 IDR, Reverse Drain Current [A] R DS(ON) [
], 10 0 0.5
Note : TJ = 25 150
-1 25

Notes : 1. VGS = 0V 2. 250 Pulse Test s 0.0 0 5 10 15 20 25 10 ID, Drain Current [A] 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 2000 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = 120V 10 V GS , Gate-Source Voltage [V] 1600 VDS = 300V VDS = 480V Ciss 8 Capacitance [pF] 1200 Coss 6 800 Crss 400
Notes : 1. VGS = 0 V 2. f = 1 MHz 4 2
Note : ID = 7.4A 0 0 -1 10 0 5 10 15 20 25 30 35 10 0 10 1 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Typical Characteristics (Continued) 1.2 3.0 2.5 BV DSS , (Norm alized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 2.0 1.0 1.5 1.0
Notes : 1. VGS = 10 V 2. ID = 3.7 A 0.9
Notes : 1. VGS = 0 V 2. ID = 250  A 0.5 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Tem perature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 5 10 2 Operation in This Area is Limited by R DS(on) 4 ID , Drain Current [A] 1 ms 10 ms 10 0 ID , Drain Current [A] 3 10 1 100 µ s 3 100 ms DC 2 10 -1
Notes : 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 1 10 -2 10 0 10 1 10 2 10 0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [
] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature (t), T h e rm a l R e s p o n s e 10 0 D = 0 .5 0 .2 0 .1 0 .0 5
N otes : 1 . Z
J C ( t ) = 2 . 6 0  /W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T C = P D M * Z
J C( t ) 10 -1 0 .0 2 0 .0 1 s in g le p u ls e 10 -2 PDM t1 t2 Z
JC 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t1 , S q u a r e W a v e P u ls e D u r a tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Gate Charge Test Circuit & Waveform 50K
12V 200nF 300nF Same Type as DUT VDS VGS Qg 10V Qgs Qgd VGS DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD VDS 90% 10V DUT VGS 10% td(on) t on tr td(off) t off tf Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG VDD DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS ID (t) VDD tp 10V VDS (t) Time ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2000 Fairchild Semiconductor International Rev. A, April 2000 FQPF7N60 Package Dimensions TO-220F 3.30 ±0.10 10.16 ±0.20 (7.00) ø3.18 ±0.10 2.54 ±0.20 (0.70) 6.68 ±0.20 15.80 ±0.20 (1.00x45°) MAX1.47 9.75 ±0.30 0.80 ±0.10 (3 ) 0° 0.35 ±0.10 2.54TYP [2.54 ±0.20] #1 0.50 –0.05 2.54TYP [2.54 ±0.20] 4.70 ±0.20 +0.10 2.76 ±0.20 9.40 ±0.20 ©2000 Fairchild Semiconductor International 15.87 ±0.20 Rev. A, April 2000 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOS™ FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench® QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production ©2000 Fairchild Semiconductor International Rev. A, January 2000