FSD210M

www.fairchildsemi.com FSD210, FSD200 Features Green Mode Fairchild Power Switch (FPSTM) • Single Chip 700V Sense FET Power Switch • Precision Fixed Operating Frequency (134kHz) • Advanced Burst-Mode operation Consumes under 0.1W at 265Vac and no load (FSD210 only) • Internal Start-up Switch and Soft Start • Under Voltage Lock Out (UVLO) with Hysteresis • Pulse by Pulse Current Limit • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Frequency Modulation for EMI • FSD200 does not require an auxiliary bias winding OUTPUT POWER TABLE 230VAC ±15%(3) PRODUCT FSD210 FSD200 FSD210M FSD200M 85-265VAC Open Open Adapter(1) Adapter(1) Frame(2) Frame(2) 5W 5W 5W 5W 7W 7W 7W 7W 4W 4W 4W 4W 5W 5W 5W 5W Applications • Charger & Adaptor for Mobile Phone, PDA & MP3 • Auxiliary Power for White Goods, PC, C-TV & Monitor Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit Description The FSD200 and FSD210 are integrated Pulse Width Modulators (PWM) and Sense FETs specially designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are monolithic high voltage power switching regulators which combine an LDMOS Sense FET with a voltage mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/turnoff driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSD200 and FSD210 reduce total component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. The FSD200 eliminates the need for an auxiliary bias winding at a small cost of increased supply power. Both devices are a basic platform well suited for cost effective designs of flyback converters. AC IN DC OUT Vstr PWM Vfb Drain Vcc Source Figure 1. Typical Flyback Application using FSD210 AC IN DC OUT Vstr PWM Vfb Drain Vcc Source Figure 2. Typical Flyback Application using FSD200 Rev.1.0.3 ©2004 Fairchild Semiconductor Corporation FSD210, FSD200 Internal Block Diagram Vstr 8 Vcc 5 UVLO Voltage Ref Internal Bias 8.7/6.7V Frequency Modulation 5uA 250uA L H 7 Drain Vck OSC DRIVER S Q SFET Vfb 4 BURST R V BURST LEB OLP Reset S R TSD Iover Q Vth Rsense V SD A/R S/S 3mS 1, 2, 3 GND Figure 3. Functional Block Diagram of FSD210 Vstr 8 Vcc 5 7V HV/REG UVLO Voltage Ref. INTERNAL BIAS ON/OFF 7 Drain Frequency Modulation 5uA 250uA Vck OSC DRIVER S Q SFET Vfb 4 BURST R V BURST LEB OLP Reset S R TSD Iover Vth Q Rsense V SD A/R S/S 3mS 1, 2, 3 GND Figure 4. Functional Block Diagram of FSD200 showing internal high voltage regulator 2 FSD210, FSD200 Pin Definitions Pin Number 1, 2, 3 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. The feedback voltage pin is the inverting input to the PWM comparator with nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source connected internally while a capacitor and opto coupler are typically connected externally. A feedback voltage of 4V triggers overload protection (OLP). There is a time delay while charging between 3V and 4V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. FSD210 Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 8 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (8.7V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. FSD200 This pin is connected to a storage capacitor. A high voltage regulator connected between pin 8 (Vstr) and this pin, provides the supply voltage to the FSD200 at startup and when switching during normal operation. The FSD200 eliminates the need for auxiliary bias winding and associated external components. The Drain pin is designed to connect directly to the primary lead of the transformer and is capable of switching a maximum of 700V. Minimizing the length of the trace connecting this pin to the transformer will decrease leakage inductance. The startup pin connects directly to the rectified AC line voltage source for both the FSD200 and FSD210. For the FSD210, at start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once this reaches 8.7V, the internal current source is disabled. For the FSD200, an internal high voltage regulator provides a constant supply voltage. 4 Vfb 5 Vcc 7 Drain 8 Vstr Pin Configuration 7-DIP 7-LSOP GND GND GND Vfb 1 2 3 4 5 8 7 Vstr Drain Vcc Figure 5. Pin Configuration (Top View) 3 FSD210, FSD200 Absolute Maximum Ratings (Ta=25°C unless otherwise specified) Parameter Maximum Supply Voltage (FSD200) Maximum Supply Voltage (FSD210) Input Voltage Range Operating Junction Temperature. Operating Ambient Temperature Storage Temperature Range Symbol VCC,MAX VCC,MAX VFB TJ TA TSTG Value 10 20 −0.3 to VSTOP +150 −25 to +85 −55 to +150 Unit V V V °C °C °C Thermal Impedance Parameter 7DIP Junction-to-Ambient Thermal Junction-to-Case Thermal 7LSOP Junction-to-Ambient Thermal Junction-to-Case Thermal Note: 1. Free standing without heat sink. 2. Measured on the GND pin close to plastic interface. 3. Soldered to 100mm2 copper clad. 4. Soldered to 300mm2 copper clad. Symbol Value 74.07(3) 60.44 (4) Unit °C/W °C/W °C/W °C/W °C/W °C/W θJA(1) θJA(1) θJC(2) θJA(1) θJA(1) θJC(2) 22.00 - 4 FSD210, FSD200 Electrical Characteristics (Ta=25°C unless otherwise specified) Parameter Sense FET SECTION Drain-Source Breakdown Voltage Startup Voltage (Vstr) Breakdown Off-State Current On-State Resistance Rise Time Fall Time CONTROL SECTION Output Frequency Output Frequency Modulation Feedback Source Current Maximum Duty Cycle Minimum Duty Cycle UVLO Threshold Voltage (FSD200) UVLO Threshold Voltage (FSD210) Supply Shunt Regulator (FSD200) Internal Soft Start Time BURST MODE SECTION VBURH Burst Mode Voltage PROTECTION SECTION Drain to Source Peak Current Limit Current Limit Delay(1) (1) Symbol BVDSS BVSTR IDSS RDS(ON) TR TF FOSC FMOD IFB DMAX DMIN VSTART VSTOP VSTART VSTOP VCCREG TS/S Condition VCC = 0V, ID = 100µA VDS = 560V Tj = 25°C, ID = 25mA Tj = 100°C, ID = 25mA VDS = 325V, ID = 50mA VDS = 325V, lD = 25mA Tj = 25°C Tj = 25°C Vfb = 0V Vfb = 3.5V Vfb = 0V After turn on After turn on - Min. 700 700 126 0.22 60 0 6.3 5.3 8.0 6.0 0.58 Typ. 28 42 100 50 134 ±4 0.25 65 0 7 6 8.7 6.7 7 3 0.64 0.58 60 0.320 220 145 4.0 5 600 700 1 700 - Max. 100 32 48 142 0.28 70 0 7.7 6.7 9.4 7.4 0.7 0.64 0.365 160 4.5 7 1.2 900 - Unit V V µA Ω Ω ns ns kHz kHz mA % % V V V V V ms V V mV A ns °C V µA ns µA µA mA µA V VBURL Hysteresis IOVER TCLD TSD VSD IDELAY TLEB IOP IOP ISTART ISTART Tj = 25°C 0.5 0.275 Tj = 25°C Vfb = 4.0V 125 3.5 3 200 Thermal Shutdown Temperature (Tj) Shutdown Feedback Voltage Feedback Shutdown Delay Current Leading Edge Blanking Time(2) TOTAL DEVICE SECTION Operating Supply Current (FSD200) Operating Supply Current (FSD210) Start Up Current (FSD200) Start Up Current (FSD210) Vstr Supply Voltage Vcc = 7V Vcc = 11V Vcc = 0V Vcc = 0V Vcc = 0V 20 Note: 1. These parameters, although guaranteed, are not 100% tested in production 2. This parameter is derived from characterization 5 FSD210, FSD200 Comparison Between FSDH565 and FSD210 Function Soft-Start FSDH0565 not applicable 3mS FSD210 FSD210 Advantages • Gradually increasing current limit during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Smaller transformer • Reduced conducted EMI • Improve light load efficiency • Reduces no-load consumption • Transformer audible noise reduction • Greater immunity to acting as a result of build-up of dust, debris and other contaminants Switching Frequency Frequency Modulation Burst Mode Operation 100kHz not applicable not applicable 134kHz ±4kHz Yes-built into controller 3.56mm DIP 3.56mm LSOP Drain Creepage at Package 1.02mm 6 FSD210, FSD200 Typical Performance Characteristics (These characteristic graphs are normalized at Ta=25℃) 1.2 Operating Current (A) -25 0 25 50 75 100 125 1.0 Fosc (kHz) 0.8 0.6 0.4 0.2 0.0 Junction Temperature (℃) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) Frequency vs. Temp Operating Current vs. Temp 1.2 Peak Current Limit (A) 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) Feedback SOurce Current (A) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) Peak Current Limit vs. Temp Feedback Source Current vs. Temp 1.20 1.00 Vstart (V) Vstop (V) -25 0 25 50 75 100 125 0.80 0.60 0.40 0.20 0.00 Junction Temperature (℃) 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -25 0 25 50 75 100 125 Junction Temperature (℃) Vstart Voltage vs. Temp Vstop Voltage vs. Temp 7 FSD210, FSD200 Typical Performance Characteristics (Continued) (These characteristic graphs are normalized at Ta=25℃) 1.8 On State Resistance (Ω) 1.6 1.4 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) BVdss (V) 1.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) On State Resistance vs. Temp Breakdown Voltage vs. Temp 1.2 Vcc Regulation Voltage (V) 1.0 0.8 1.2 1.0 0.8 VSD (V) 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 0.6 0.4 0.2 0.0 Junction Temperature (℃) -25 0 25 50 75 100 125 Junction Temperature (℃) Vcc Regulation Voltage vs. Temp (for FSD200) Shutdown Feedback Voltage vs. Temp 1.4 1.2 1.0 Istart (A) 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) Istart (A) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Junction Temperature (℃) Start Up Current vs. Temp (for FSD210) Start Up Current vs. Temp (for FSD200) 8 FSD210, FSD200 Functional Description 1. Startup : At startup, the internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in figure 7. In the case of the FSD210, when Vcc reaches 8.7V the device starts switching and the internal high voltage current source is disabled (see figure 1). The device continues to switch provided that Vcc does not drop below 6.7V. For FSD210, after startup, the bias is supplied from the auxiliary transformer winding. In the case of FSD200, Vcc is continuously supplied from the external high voltage source and Vcc is regulated to 7V by an internal high voltage regulator (HVReg), thus eliminating the need for an auxiliary winding (see figure 2). Vin,dc Istr i = Is tr - m ax 1 00 u A i = Istr-max 100uA Vcc ma max 100uA Vstr J-FET UVLO Vref Vcc FSD2xx Vin,dc Istr Vin,dc Istr UVLO start Vcc must not drop to UVLO stop Vstr Vcc HV Reg. 7V Vstr Vcc L UVLO stop Auxiliary winding voltage H 8.7V/ 6.7V FSD210 FSD200 t Figure 6. Internal startup circuit Figure 7. Charging the Vcc capacitor through Vstr Calculating the Vcc capacitor is an important step to designing in the FSD200/210. At initial start-up in both the FSD200/210, the stand-by maximum current is 100uA, supplying current to UVLO and Vref Block. The charging current (i) of the Vcc capacitor is equal to Istr - 100uA. After Vcc reaches the UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At this time Vcc oscillates. In order to prevent this ripple it is recommended that the Vcc capacitor be sized between 10uF and 47uF. 3. Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by the primary side capacitance and secondary side rectifier diode reverse recovery. Exceeding the pulse-by-pulse current limit could cause premature termination of the switching pulse (see Protection Section). To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the over current comparator for a short time (TLEB) after the Sense FET is turned on. 2. Feedback Control : The FSD200/210 are both voltage mode devices as shown in Figure 8. Usually, a H11A817 optocoupler and KA431 voltage reference (or a FOD2741 integrated optocoupler and voltage reference) are used to implement the isolated secondary feedback network. The feedback voltage is compared with an internally generated sawtooth waveform, directly controlling the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases pulling down the feedback voltage and reducing the duty cycle. This event will occur when either the input voltage increases or the output load decreases. Vcc 5uA OSC Vref 0.25mA Gate driver R Vo Vfb FB 4 Cfb KA431 VSD OLP Figure 8. PWM and feedback circuit 4. Protection Circuit : The FSD200/210 has 2 self protection functions: over load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC with no external components, system 9 FSD210, FSD200 reliability is improved without a cost increase. If either of these thresholds are triggered, the FPS starts an auto-restart cycle. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage (6.7V:FSD210, 6V:FSD200), the protection is reset and the internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage (8.7V:FSD210,7V:FSD200), the device attempts to resume normal operation. If the fault condition is no longer present start up will be successful. If it is still present the cycle is repeated (see figure 10). to detect the temperature of the Sense FET. When the temperature exceeds approximately 145°C, thermal shutdown is activated. Vfb under Vstop of UVLO OLP 4V 3V FPS Switching Area Idelay (5uA) charges Cfb OSC IC Reset t 5uA 250uA Vfb 4 R + 3V OLP S R Q GATE DRIVER t1 t2 t3 Cfb S RESET Q t1